CN107994788B - Line compensation circuit and switching power supply - Google Patents

Line compensation circuit and switching power supply Download PDF

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Publication number
CN107994788B
CN107994788B CN201711436678.4A CN201711436678A CN107994788B CN 107994788 B CN107994788 B CN 107994788B CN 201711436678 A CN201711436678 A CN 201711436678A CN 107994788 B CN107994788 B CN 107994788B
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nmos
capacitor
voltage
compensation circuit
constant current
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CN107994788A (en
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应征
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BCD Shanghai Micro Electronics Ltd
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BCD Shanghai Micro Electronics Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0016—Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters
    • H02M1/0019—Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters the disturbance parameters being load current fluctuations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a line compensation circuit and a switching power supply, wherein the circuit comprises an amplifier adjustable resistor, a diode, a capacitor, a first NMOS (N-channel metal oxide semiconductor), a first constant current source and a signal generator, wherein the anode of the diode is connected with the output end of the amplifier, and the cathode of the diode is respectively connected with the drain electrode of the first NMOS, the control end of the adjustable resistor and the first end of the capacitor; the second end of the capacitor is grounded; the source electrode of the first NMOS is connected with the input end of the first constant current source, and the grid electrode of the first NMOS is connected with the signal output end of the signal generator; the output end of the first constant current source is grounded. When the output current is switched from full load to no load, the voltage of the feedback pin FB is only slightly lower than the standby threshold. When the output current is switched from no-load to full-load, the voltage of the feedback pin FB can quickly rise to the standby threshold value, so that the undershoot phenomenon of the output voltage is greatly relieved.

Description

Line compensation circuit and switching power supply
Technical Field
The invention relates to the technical field of switching power supplies, in particular to a line compensation circuit. The invention also relates to a switching power supply.
Background
With the development of science and the progress of technology, electronic devices are increasingly widely used in life of people, and a portable electronic device switching power supply is generated.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a switching power supply. The CC/CV controller 101 samples an output voltage through a voltage dividing resistor R1 and a resistor R2, amplifies an error signal of the output voltage Vout and a reference voltage CVref through an amplifier, directly controls an NMOS connected with the amplifier and serving as an adjustable resistor, and indirectly controls a light emitter of the optocoupler 102, the optocoupler 102 feeds back to the PWM control chip 103 on the primary side, and the PWM control chip 103 on the primary side further controls a board end to output the voltage Vout by adjusting a peak current in the NMOS 104, where vout=cvref× (r1+r2)/R1.
In order to shorten the charging time of the electronic equipment, the charging current of the switching power supply of the portable electronic equipment can reach more than 1.8A. During charging, a voltage drop Vcable (Vcable may be calculated from the product of the resistance Rcable of the charging line and the current Iload of the charging line, i.e., vcable=iload×rcable) will be generated on the charging line, and as the charging current changes, the voltage drop on the charging line will also change, so when the output voltage Vout of the switching power supply is fixed, because vcable_end=vout-Vcable, the voltage value vcable_end of the line-end voltage (i.e., the charged end) will change significantly.
To compensate the voltage drop on the charging line and maintain the voltage at the line end stable, a line compensation circuit with a line compensation function needs to be integrated in the CC/CV controller, and the basic principle is as follows: detecting the output current, and increasing the output voltage of the plate terminal along with the increase of the output current, so as to maintain the terminal voltage within a constant range.
Referring to fig. 2 and 3, fig. 2 is a schematic diagram of a line compensation circuit in the prior art, and fig. 3 is an output waveform of each signal corresponding to the circuit in fig. 2. As shown in fig. 2, the input signal at the non-inverting input terminal of the amplifier 201 is a secondary sampling voltage Load, and the secondary sampling voltage Load is proportional to the output current Iout, namely: load=iout×rsen×16, where Rsen is the resistance value of the sampling resistor 105; the output voltage CVref of the Current Mirror (Current Mirror) 202 is used as a reference voltage; the voltage at the non-inverting input of the buffer 203 is the fixed reference voltage Vref. As can be seen from fig. 2, when the secondary sampling voltage is changed, the reference voltage is changed rapidly in synchronization with the secondary sampling voltage.
As shown in fig. 3, when the output current is switched from full load to no load, the secondary side sampling voltage and the output current change simultaneously, and the reference voltage in the CC/CV controller can be adjusted correspondingly according to the change of the secondary side sampling voltage in real time, that is, the reference voltage can be quickly reduced along with the quick reduction of the secondary side sampling voltage, and meanwhile, the output voltage of the system is in a slow discharge state due to the effect of the output capacitor 106. Since Vctrl > CVref, the output out of the CC/CV controller is low and is transmitted to the primary side through the optocoupler 102, so that the feedback pin FB voltage is pulled down, and the control chip 103 stops outputting when the feedback pin FB voltage is lower than the standby threshold. If the output current is switched to full load at this time, the reference voltage rises rapidly with the rapid rise of the secondary sampling voltage, and the output voltage will rise due to Vctrl < CVref, and thus the feedback pin voltage will rise, but there is a certain delay time from the rise of the output voltage to the rise of the feedback pin voltage to above the standby threshold (i.e. the primary control chip 103 starts to output), and the output voltage is maintained only by the output capacitor 106 during this delay time. If the delay time is long, a large voltage undershoot is generated in the output voltage.
Therefore, how to provide a line compensation circuit and a switching power supply for solving the above technical problems is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a line compensation circuit which reduces undershoot phenomenon of output voltage in the using process; another object of the present invention is to provide a switching power supply including the above line compensation circuit, which has improved stability in use.
In order to solve the technical problems, the invention provides a line compensation circuit which is applied to a switching power supply, wherein the line compensation circuit comprises an amplifier, an adjustable resistor, a first resistor, a second resistor, a current mirror and a buffer, and a non-inverting input end of the amplifier is connected with a secondary side sampling voltage; the first end of the adjustable resistor is connected with the input end of the current mirror, and the second end of the adjustable resistor is respectively connected with the first end of the first resistor and the inverting input end of the amplifier; the second end of the first resistor is grounded; the output end of the current mirror is connected with the first end of the second resistor, and the common end of the current mirror outputs a reference voltage; the second end of the second resistor is connected with the output end of the buffer; the input end of the buffer is connected with a fixed reference voltage; the line compensation circuit further comprises a diode, a capacitor, a first NMOS, a first constant current source and a signal generator for outputting pulse signals, wherein:
the anode of the diode is connected with the output end of the amplifier, and the cathode of the diode is respectively connected with the drain electrode of the first NMOS, the control end of the adjustable resistor and the first end of the capacitor;
the second end of the capacitor is grounded;
the source electrode of the first NMOS is connected with the input end of the first constant current source, and the grid electrode of the first NMOS is connected with the signal output end of the signal generator;
the output end of the first constant current source is grounded.
Preferably, the compensation circuit further includes a PMOS, a second constant current source, an inverter, and a second NMOS, wherein:
the grid electrode of the PMOS is connected with the first end of the capacitor, the source electrode of the PMOS is respectively connected with the output end of the second constant current source and the drain electrode of the second NMOS, and the drain electrode of the PMOS is grounded;
the source electrode of the second NMOS is connected with the input end of the first constant current source, and the grid electrode of the second NMOS is connected with the output end of the inverter;
the input end of the inverter is connected with the signal output end of the signal generator.
Preferably, the compensation circuit further comprises a third NMOS and a comparator, wherein:
the drain electrode of the third NMOS is connected with the first end of the capacitor, the source electrode of the third NMOS is connected with the drain electrode of the first NMOS, and the grid electrode of the third NMOS is connected with the output end of the comparator;
the non-inverting input end of the comparator is connected with the inverting input end of the amplifier, and the inverting input end of the comparator is connected with the non-inverting input end of the amplifier.
Preferably, the buffer is a voltage follower.
Preferably, the adjustable resistor is a fourth NMOS, and the first end of the adjustable resistor is a drain of the fourth NMOS; the second end of the adjustable resistor is the source electrode of the fourth NMOS, and the control end of the adjustable resistor is the grid electrode of the fourth NMOS.
Preferably, the duty cycle of the pulses is 1/100.
Preferably, the capacitance is 15PF.
The invention also provides a switching power supply comprising the line compensation circuit described in any one of the above.
The invention provides a line compensation circuit which comprises an amplifier, an adjustable resistor, a first resistor, a second resistor, a current mirror and a buffer, and further comprises a diode, a capacitor, a first NMOS, a first constant current source and a signal generator, wherein the anode of the diode is connected with the output end of the amplifier, and the cathode of the diode is respectively connected with the drain electrode of the first NMOS, the control end of the adjustable resistor and the first end of the capacitor; the second end of the capacitor is grounded; the source electrode of the first NMOS is connected with the input end of the first constant current source, and the grid electrode of the first NMOS is connected with the signal output end of the signal generator; the output end of the first constant current source is grounded; the signal transmitted by the signal amplifier is a pulse.
When the invention is applied to a switching power supply, when the output current is switched from full load to no load, the secondary sampling voltage can be rapidly reduced, and meanwhile, the capacitor can be discharged, and the capacitor can be discharged through the first constant current source due to the characteristic of reverse cut-off of the diode; the first constant current source is controlled by the first NMOS, pulses sent by the signal generator are enabled to have an extremely small CLK duty ratio through design, the first constant current source is enabled to have extremely small discharging current, the discharging rate of the capacitor is reduced, the terminal voltage of the capacitor is enabled to be slowly reduced, and therefore the reference voltage is also slowly reduced, and accordingly the voltage of the feedback pin FB is enabled to be slowly reduced, and the voltage of the feedback pin FB is enabled to be only slightly lower than the standby threshold value. When the output current is switched from no-load to full-load, the voltage of the feedback pin FB can quickly rise to the standby threshold value, so that the undershoot phenomenon of the output voltage is greatly relieved.
The invention provides a switching power supply including a line compensation circuit, which improves the stability of the switching power supply.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the prior art and the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a switching power supply;
FIG. 2 is a schematic diagram of a prior art line compensation circuit;
FIG. 3 is a diagram showing waveforms of the output signals of the line compensating circuit in FIG. 2;
FIG. 4 is a schematic diagram of a line compensation circuit according to the present invention;
FIG. 5 is a diagram showing waveforms of the output signals of the line compensating circuit of FIG. 4;
fig. 6 is a schematic diagram of another line compensation circuit according to the present invention.
Detailed Description
The invention provides a line compensation circuit, which reduces the undershoot phenomenon of output voltage in the using process; the invention also provides a switching power supply comprising the line compensation circuit, and the stability of the switching power supply is improved when the switching power supply is used.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
Referring to fig. 4 and 5, fig. 4 is a schematic structural diagram of a line compensation circuit according to the present invention, and fig. 5 is an output waveform diagram of signals corresponding to the line compensation circuit in fig. 4, where the line compensation circuit is applied to a switching power supply, and the line compensation circuit includes:
the non-inverting input end of the amplifier 401 is connected with the secondary sampling voltage; a first end of the adjustable resistor 404 is connected with an input end of the current mirror 408, and a second end of the adjustable resistor 404 is respectively connected with a first end of the first resistor 409 and an inverting input end of the amplifier 401; the second end of the first resistor 409 is grounded; an output terminal of the current mirror 408 is connected to a first terminal of the second resistor 410, and a common terminal thereof outputs a reference voltage; a second terminal of the second resistor 410 is connected to an output terminal of the buffer 411; the input of buffer 411 is connected to a fixed reference voltage; the line compensation circuit further includes a diode 402, a capacitor 403, a first NMOS 405, a first constant current source 406, and a signal generator 407 for outputting a pulse signal, wherein:
an anode of the diode 402 is connected with an output end of the amplifier 401, and a cathode of the diode 402 is respectively connected with a drain electrode of the first NMOS 405, a control end of the adjustable resistor 404 and a first end of the capacitor 403;
the second terminal of the capacitor 403 is grounded;
the source of the first NMOS 405 is connected with the input end of the first constant current source 406, and the grid of the first NMOS 405 is connected with the signal output end of the signal generator 407;
the output of the first constant current source 406 is grounded.
In particular, when the output current is switched from full load to no load, as shown in fig. 5, the output current is rapidly reduced to zero, and the secondary sampling voltage is rapidly reduced due to the synchronous change of the secondary sampling voltage and the output current, and it is noted that, due to the capacitor 403, the reference voltage is not changed synchronously with the secondary sampling voltage but is changed synchronously with the voltage at the end of the capacitor 403. The capacitor 403 will discharge while the secondary sampling voltage is rapidly reduced, and because the diode 402 has the characteristic of reverse cut-off, the capacitor 403 can only discharge through the first constant current source 406, and the discharge rate of the capacitor 403 directly affects the rate of voltage drop at the terminal of the capacitor 403, thereby affecting the drop rate of the reference voltage. If the falling rate of the reference voltage is lower than the falling rate of the output voltage of the switching power supply, the falling rate of the voltage of the feedback-introduced FB can be slowed down to a certain extent, and then the undershoot phenomenon of the output voltage is relieved.
It will be appreciated that in order to obtain a sufficiently low rate of drop of the reference voltage, one can start from two aspects, on the one hand the capacitance of the capacitor 403 is sufficiently large; on the other hand, the discharge rate of the capacitor 403 is slow enough, i.e., the discharge current of the capacitor 403 is small enough. However, due to practical limitations (e.g., the volume of the capacitor 403), the capacitance of the capacitor 403 may not be too large, and thus may be considered from the perspective of the discharge current based on the constant capacitance of the capacitor 403.
As can be seen from the above, the first constant current source 406 can be controlled to have a small discharge current, so that the discharge current of the capacitor 403 can be reduced, the discharge rate of the capacitor 403 can be further reduced, the voltage drop rate of the terminal voltage of the capacitor 403 can be reduced, the reference voltage drop rate can be reduced, the voltage drop condition of the feedback pin FB can be further slowed down, and finally the undershoot phenomenon of the output voltage can be relieved.
Specifically, the first constant current source 406 is controlled by the first NMOS 405, and when the gate of the first NMOS 405 is at a high level, the first constant current source 406 can be turned on, and the capacitor 403 can be discharged; the signal output terminal of the signal generator 407 is connected to the gate of the first NMOS 405, and by setting the pulse output by the signal generator 407 to have a minimum CLK duty ratio duty, for example, the discharge current of the first constant current source 406 is Id, then a minimum discharge current Idischarge (idischarge=id×duty) of the capacitor 403 is obtained, and the voltage drop rate at the terminal of the capacitor 403 is reduced, so that the reference voltage drop rate is also reduced, and the voltage drop of the feedback pin FB is further slowed down, and finally the voltage of the feedback pin FB is only slightly lower than the standby threshold (at this time, the voltage of the feedback pin FB is higher than the voltage of the feedback pin FB in the prior art under the same condition).
On the basis of the above, when the output current is switched from no-load to full-load, the output current can rise rapidly, the secondary sampling voltage can also change synchronously, the voltage of the feedback pin FB can rise at the moment, and the voltage of the feedback pin FB can rise to be larger than the standby threshold rapidly because the voltage of the feedback pin FB is only slightly lower than the standby threshold.
The invention provides a line compensation circuit which comprises an amplifier, an adjustable resistor, a first resistor, a second resistor, a current mirror and a buffer, and further comprises a diode, a capacitor, a first NMOS, a first constant current source and a signal generator, wherein the anode of the diode is connected with the output end of the amplifier, and the cathode of the diode is respectively connected with the drain electrode of the first NMOS, the control end of the adjustable resistor and the first end of the capacitor; the second end of the capacitor is grounded; the source electrode of the first NMOS is connected with the input end of the first constant current source, and the grid electrode of the first NMOS is connected with the signal output end of the signal generator; the output end of the first constant current source is grounded; the signal transmitted by the signal amplifier is a pulse.
When the invention is applied to a switching power supply, when the output current is switched from full load to no load, the secondary sampling voltage can be rapidly reduced, and meanwhile, the capacitor can be discharged, and the capacitor can be discharged through the first constant current source due to the characteristic of reverse cut-off of the diode; the first constant current source is controlled by the first NMOS, and the pulse sent by the signal generator is enabled to have an extremely small CLK duty ratio, so that the first constant current source is enabled to have extremely small discharge current, the discharge rate of the capacitor is reduced, the terminal voltage of the capacitor is enabled to be slowly reduced, and therefore the reference voltage is also slowly reduced, the voltage of the feedback pin FB is enabled to be slowly reduced, and the voltage of the feedback pin FB is enabled to be only slightly lower than the standby threshold value. When the output current is switched from no-load to full-load, the voltage of the feedback pin FB can quickly rise to the standby threshold value, so that the undershoot phenomenon of the output voltage is greatly relieved.
Example two
Referring to fig. 6, fig. 6 is a schematic structural diagram of another line compensation circuit according to the present invention, wherein the line compensation circuit is based on the first embodiment:
preferably, the compensation circuit further includes a PMOS 414, a second constant current source 413, an inverter 415, and a second NMOS412, wherein:
the PMOS 414 is connected to the first end of the capacitor 403, the source of the PMOS 414 is connected to the output end of the second constant current source 413 and the drain of the second NMOS412, respectively, and the drain of the PMOS 414 is grounded; the source of the second NMOS412 is connected to the input of the first constant current source 406, and the gate of the second NMOS412 is connected to the output of the inverter 415; an input terminal of the inverter 415 is connected to a signal output terminal of the signal generator 407.
When the first NMOS 405 is turned off, the input voltage of the first constant current source 406 is reduced to 0, and the discharge current Id of the first constant current source 406 increases when the first NMOS 405 is turned on until the input voltage of the first constant current source 406 exceeds the minimum operating voltage (about 400 mV), thereby increasing the actual discharge current of the capacitor 403 and increasing the discharge rate of the capacitor 403 to some extent.
In order to stabilize the discharge current Id of the first constant current source 406, the input voltage of the first constant current source 406 needs to be stabilized. To achieve this, the present application adds PMOS 414, second constant current source 413, inverter 415, and second NMOS412 to the line compensation circuit in the first embodiment. Wherein PMOS 414 acts as a source follower clamp and the second constant current source 413 current is greater than the first constant current source 406. When the gate of the first NMOS 405 inputs a low level and the first NMOS 405 is turned off, the signal generator 407 inputs a high level to the gate of the second NMOS412 through the inverter 415, and the second NMOS412 is turned on, so that the output terminal of the second constant current source 413 is connected to the input terminal of the first constant current source 406, and the voltage value of the input terminal of the first constant current source 406 can be kept stable and always exceeds the minimum operating voltage thereof due to the clamping effect of the PMOS 414, so that the discharge current Id of the first constant current source 406 can be kept stable, and the discharge current of the capacitor 403 can be kept stable, so that the capacitor 403 has a stable and small discharge rate.
Preferably, the compensation line further comprises a second NMOS412 and a comparator 418, wherein:
the drain of the second NMOS412 is connected to the first end of the capacitor 403, the source of the second NMOS412 is connected to the drain of the first NMOS 405, and the gate of the second NMOS412 is connected to the output end of the comparator 418; the non-inverting input of the comparator 418 is connected to the inverting input of the amplifier 401, and the inverting input of the comparator 418 is connected to the non-inverting input of the amplifier 401.
When the load increases, the capacitor 403 is charged, and since the signal generator 407 is connected to the gate of the first NMOS 405, there may be a pulse that transfers charge to the capacitor 403 through the coupling action of the gate capacitor of the first NMOS 405, so that an interference signal is introduced into the capacitor 403. In order to reduce the occurrence of the above, a second NMOS412 and a comparator 418 are provided between the capacitor 403 and the first NMOS 405, and the capacitor 403 is allowed to discharge only in the case of a reduced load.
Specifically, the non-inverting input terminal of the comparator 418 is connected to the inverting input terminal of the amplifier 401, and the inverting input terminal of the comparator 418 is connected to the non-inverting input terminal of the amplifier 401. When the load increases, the secondary sampling voltage increases, and the voltage of the inverting input terminal of the comparator 418 is greater than the voltage of the non-inverting input terminal of the comparator 418, so the comparator 418 outputs a low level, and the second NMOS412 is turned off; when the load decreases, the secondary sampling voltage decreases, the voltage of the inverting input terminal of the comparator 418 is smaller than the voltage of the non-inverting input terminal of the comparator 418, the comparator 418 outputs a high level, and the second NMOS412 is turned on, so that the capacitor 403 discharges. Therefore, the second NMOS412 and the comparator 418 in the line compensation circuit provided in the embodiment of the present invention can allow the capacitor 403 to discharge only when the load is reduced, thereby reducing the possibility of introducing an interference signal into the capacitor 403.
Preferably, the buffer 411 is a voltage follower.
Preferably, the adjustable resistor 404 is a fourth NMOS, and the first end of the adjustable resistor 404 is the drain of the fourth NMOS; the second end of the adjustable resistor 404 is the source of the fourth NMOS, and the control end of the adjustable resistor 404 is the gate of the fourth NMOS.
Preferably, the duty cycle of the pulses is 1/100.
Of course, the duty ratio of the pulse may be not only 1/100, but also other suitable values, and the embodiment of the present invention is not particularly limited herein, so long as the object of the present invention can be achieved.
Preferably, the capacitor 403 has a size of 15PF
The capacitor 403 may be not only 15PF, but also other suitable values, and the embodiment of the present invention is not limited thereto, and may be determined according to practical situations.
The invention also provides a switching power supply which comprises the line compensation circuit.
It should be noted that, for the description of the line compensation circuit in the switching power supply provided by the present invention, reference is made to the above circuit embodiment, and the disclosure is not repeated here.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (8)

1. The line compensation circuit is applied to a switching power supply and comprises an amplifier, an adjustable resistor, a first resistor, a second resistor, a current mirror and a buffer, wherein the non-inverting input end of the amplifier is connected with a secondary side sampling voltage; the first end of the adjustable resistor is connected with the input end of the current mirror, and the second end of the adjustable resistor is respectively connected with the first end of the first resistor and the inverting input end of the amplifier; the second end of the first resistor is grounded; the output end of the current mirror is connected with the first end of the second resistor, and the common end of the current mirror outputs a reference voltage; the second end of the second resistor is connected with the output end of the buffer; the input end of the buffer is connected with a fixed reference voltage; the line compensation circuit is characterized by further comprising a diode, a capacitor, a first NMOS, a first constant current source and a signal generator for outputting pulse signals, wherein:
the anode of the diode is connected with the output end of the amplifier, and the cathode of the diode is respectively connected with the drain electrode of the first NMOS, the control end of the adjustable resistor and the first end of the capacitor;
the second end of the capacitor is grounded;
the source electrode of the first NMOS is connected with the input end of the first constant current source, and the grid electrode of the first NMOS is connected with the signal output end of the signal generator;
the output end of the first constant current source is grounded.
2. The line compensation circuit of claim 1 further comprising a PMOS, a second constant current source, an inverter, and a second NMOS, wherein:
the grid electrode of the PMOS is connected with the first end of the capacitor, the source electrode of the PMOS is respectively connected with the output end of the second constant current source and the drain electrode of the second NMOS, and the drain electrode of the PMOS is grounded;
the source electrode of the second NMOS is connected with the input end of the first constant current source, and the grid electrode of the second NMOS is connected with the output end of the inverter;
the input end of the inverter is connected with the signal output end of the signal generator.
3. The line compensation circuit of claim 1 further comprising a third NMOS and comparator, wherein:
the drain electrode of the third NMOS is connected with the first end of the capacitor, the source electrode of the third NMOS is connected with the drain electrode of the first NMOS, and the grid electrode of the third NMOS is connected with the output end of the comparator;
the non-inverting input end of the comparator is connected with the inverting input end of the amplifier, and the inverting input end of the comparator is connected with the non-inverting input end of the amplifier.
4. The line compensation circuit of claim 1 wherein the buffer is a voltage follower.
5. The line compensation circuit of claim 1 wherein the adjustable resistor is a fourth NMOS, the first end of the adjustable resistor being a drain of the fourth NMOS; the second end of the adjustable resistor is the source electrode of the fourth NMOS, and the control end of the adjustable resistor is the grid electrode of the fourth NMOS.
6. The line compensation circuit of claim 1 wherein the duty cycle of the pulses is 1/100.
7. The line compensation circuit of claim 1 wherein the capacitance is 15PF in magnitude.
8. A switching power supply comprising a line compensation circuit as claimed in any one of claims 1 to 7.
CN201711436678.4A 2017-12-26 2017-12-26 Line compensation circuit and switching power supply Active CN107994788B (en)

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