JP2017169340A - Control circuit and slope generation circuit for switching power supply - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a circuit scale.SOLUTION: A control circuit for a switching power supply includes a feedback circuit 11, an oscillator circuit 12-1 and a slope generation circuit 13-1. The feedback circuit 11 outputs a voltage signal according to a feedback voltage VFB fed back from the secondary side output of a transformer. The oscillator circuit 12-1 converts the voltage signal into a current signal, to charge a capacitor with a charge current which is proportional to the current signal so as to generate the clock signal of a predetermined oscillation frequency to output a triangle wave voltage Vosc0 synchronized with the clock signal. The slope generation circuit 13-1 generates, from a current obtained by converting the triangle wave voltage Vosc0 by a resistor R41, a slope compensating current Is by a current mirror circuit, to subtract a voltage, which is obtained by converting the slope compensating current Is through a resistor R42, from a divided voltage Vd which is obtained by dividing an input voltage VFB, so as to generate a slope voltage Vslope.SELECTED DRAWING: Figure 1

Description

  The present technology relates to a control circuit and a slope generation circuit of a switching power supply device.

  As a power supply device, a current mode control switching power supply device that feeds back an inductor current of a transformer together with an output voltage to make the output voltage constant is widely used. In the switching power supply device of current mode control, the subharmonic oscillation of the current mode control pulse signal is suppressed to stabilize the output voltage.

  Subharmonic oscillation is a phenomenon in which oscillation at a frequency lower than the switching frequency occurs when a power transistor used as a switching element is operated at a duty cycle of 50% or more.

  The generation mechanism is that the initial value and final value in the switching period of the inductor current flowing in the transformer connected in series with the power transistor are shifted over time without matching the rise and fall of the inductor current. is there.

The absolute value of this deviation gradually increases and then decreases after a certain number of cycles. And this increase / decrease in the deviation is repeated to cause low frequency oscillation.
In order to suppress subharmonic oscillation, slope compensation is performed to correct the deviation between the rising slope and the falling slope of the inductor current with the slope voltage.

  For example, as a conventional technique of slope compensation, a technique has been proposed in which a rectified output voltage is detected by a voltage detection unit, and a slope generation circuit subtracts a slope compensation signal from a voltage detection signal output from the voltage detection unit (for example, Patent Document 1). The prior art of such slope compensation will be described below.

  FIG. 8 is a diagram illustrating a configuration example of a switching power supply device for current mode control. The switching power supply device 100 includes a bridge diode BD1, capacitors C11 to C13, resistors R21 to R23, diodes D1 and D2, a transformer T1, a switching element PT1, a photocoupler PC1, a control circuit 10, and a voltage detection circuit 120.

  Note that an NMOS transistor is used as the switching element PT1. The transformer T1 includes a primary winding Tn1, a secondary winding Tn2, and further has an auxiliary winding Tn3.

  Regarding the connection relationship of the circuit elements, the two input terminals of the bridge diode BD1 are connected to the AC voltage source a1. One output terminal of the bridge diode BD1 is connected to the positive terminal of the capacitor C11 and one end of the primary winding Tn1 of the transformer T1.

  The other output terminal of the bridge diode BD1 is the negative terminal of the capacitor C11, one end of the resistor R22, the ground terminal GND of the control circuit 10, the emitter of the phototransistor of the photocoupler PC1, the negative terminal of the capacitor C12, and the auxiliary of the transformer T1. Connected to one end of the winding Tn3.

  The output terminal OUT of the control circuit 10 is connected to one end of the resistor R21, and the other end of the resistor R21 is connected to the gate of the switching element PT1. The drain of the switching element PT1 is connected to the other end of the primary winding Tn1 of the transformer T1, and the source of the switching element PT1 is connected to the other end of the resistor R22 and one end of the resistor R23. The other end of the resistor R23 is connected to the current detection terminal CS of the control circuit 10.

  The power supply terminal VCC of the control circuit 10 is connected to the positive terminal of the capacitor C12 and the cathode of the diode D1, and the anode of the diode D1 is connected to the other end of the auxiliary winding Tn3 of the transformer T1. The feedback terminal FB of the control circuit 10 is connected to the phototransistor collector of the photocoupler PC1.

  One end of the secondary winding Tn2 of the transformer T1 is connected to the anode of the diode D2, and the cathode of the diode D2 is connected to the positive terminal of the capacitor C13, the output terminal b1, and one voltage detection terminal of the voltage detection circuit 120. .

  The other end of the secondary winding Tn2 of the transformer T1 is connected to the negative side terminal of the capacitor C13, the output terminal b2, and the other voltage detection terminal of the voltage detection circuit 120. The output terminals b1 and b2 are connected to the load 2. The cathode and anode of the photodiode of the photocoupler PC1 are connected to the voltage detection signal output terminal of the voltage detection circuit 120, respectively.

  Here, the switching power supply device 100 is configured as a flyback DC / DC converter, and is generated on the secondary side of the transformer T1 by turning on and off the current flowing in the primary side of the transformer T1 by the switching element PT1. The pulsating flow is rectified and output to the load.

  In the switching power supply device 100, commercial alternating current is full-wave rectified by the bridge diode BD1, and the full-wave rectified voltage is smoothed by the capacitor C11 to form a series circuit of the primary winding Tn1 of the transformer T1 and the switching element PT1. Supply.

  The control circuit 10 made of a semiconductor integrated circuit turns on and off the switching element PT1, thereby rectifying and smoothing the pulsating current generated in the secondary winding Tn2 of the transformer T1 by the diode D2 and the capacitor C13. 2 is supplied.

  The output voltage to the load 2 is detected by the voltage detection circuit 120, and the detection signal is fed back through the photocoupler PC1 and input to the feedback terminal FB of the control circuit 10.

  In addition to the feedback terminal FB, the control circuit 10 includes a power supply terminal VCC to which a power supply voltage is input, a ground terminal GND at a GND level, an output terminal OUT of a PWM (Pulse Width Modulation) signal, and a current detection signal to which a current detection signal is input. A terminal CS is provided.

  A DC voltage obtained by rectifying and smoothing the output of the auxiliary winding Tn3 of the transformer T1 with the diode D1 and the capacitor C12 is input to the power supply terminal VCC. A current detection signal obtained by converting the current flowing through the switching element PT1 into a voltage by the current detection resistor R22 is input to the current detection terminal CS via the resistor R23. The output terminal OUT outputs a PWM signal for switching the switching element PT1.

  FIG. 9 is a diagram showing a schematic overall configuration example of the control circuit 10 shown in FIG. An example of the internal configuration around the feedback terminal FB, current detection terminal CS, and output terminal OUT of the control circuit 10 is shown.

  The control circuit 10 includes a feedback circuit 11, an oscillator circuit 12, a slope generation circuit 13, a PWM comparator 21, an RS flip-flop 22 and a buffer 23. The feedback circuit 11 includes resistors R10, R31 to R34, diodes D1, D2, and a transistor Tr0. Note that the inside of the feedback circuit 11 shown in FIG. 9 shows only a part of the circuit, and the detailed configuration will be described later. The diode in the feedback circuit 11 is actually composed of a transistor (described later).

  Here, the positive input terminal of the PWM comparator 21 is connected to the current detection terminal CS, and the current detection signal voltage VCS is input thereto. The slope voltage V_slope is input to the negative input terminal of the PWM comparator 21.

  The reset terminal R of the RS flip-flop 22 is connected to the output terminal of the PWM comparator 21, and the clock signal ck is input to the set terminal S of the RS flip-flop 22.

  The output terminal Q of the RS flip-flop 22 is connected to the input terminal of the buffer 23, and the output terminal of the buffer 23 is connected to the output terminal OUT. A drive signal VOUT for switching the switching element PT1 is output from the output terminal OUT.

FIG. 10 is a diagram for explaining the stabilization control of the output voltage in the switching power supply device. The horizontal axis is time, and the vertical axis is voltage.
[S1] The oscillator circuit 12 outputs a clock signal ck having a fixed period.

  [S1a] The signal from the output terminal Q of the RS flip-flop 22 set by the clock signal ck is output from the output terminal OUT through the buffer 23 as the drive signal VOUT.

  [S2] When the switching element PT1 is turned on by the drive signal VOUT (VOUT = H), a current flows through the primary winding Tn1 of the transformer T1, and the current detection signal voltage VCS applied to the current detection terminal CS increases.

  [S3] The slope generation circuit 13 generates a slope voltage V_slope from the feedback terminal voltage VFB applied to the feedback terminal FB in synchronization with the clock signal ck. The slope voltage V_slope is a voltage that gradually decreases from the voltage Vr generated from the feedback terminal voltage VFB.

  [S4] The PWM comparator 21 compares the slope voltage V_slope with the current detection signal voltage VCS, and outputs an H level signal when the current detection signal voltage VCS reaches the slope voltage V_slope.

  [S5] When the RS flip-flop 22 is reset by the H level signal output from the PWM comparator 21, and the drive signal VOUT from the output terminal OUT becomes L level, the switching element PT1 is turned off (VOUT = L). At this time, the current detection signal voltage VCS becomes 0 V, and the output of the PWM comparator 21 also becomes L level.

  Thereafter, this operation is repeated with a clock signal ck having a fixed period, and the feedback terminal voltage VFB changes according to the load 2, whereby the duty of the drive signal VOUT is changed to control the switching of the switching element PT1. Thereby, it controls so that the output voltage of a switching power supply device may become a setting value.

  Next, a conventional control circuit using an operational amplifier for the slope generation circuit will be described. 11 and 12 are diagrams showing a configuration example of the control circuit. The control circuit 10 includes a feedback circuit 11, an oscillator circuit 12, and a slope generation circuit 13. FIG. 11 shows the feedback circuit 11 and the oscillator circuit 12, and FIG. 12 shows the slope generation circuit 13. In the following, the symbol representing resistance is also applied as the resistance value of the resistor.

  The feedback circuit 11 includes resistors R0, R1, R2, R10, R31 to R34, transistors Tr0, Tr1, Tr10, NMOS transistor N1, PMOS transistors P1, P2, and a current source I1.

Note that NPN transistors are used as the transistors Tr0, Tr1, and Tr10. The current source I1 is a constant current source of 1 μA, for example.
The oscillator circuit 12 includes a resistor R3, capacitors C1 and C2, transistors Tr2 to Tr4, NMOS transistors N2 and N3, PMOS transistors P3 to P7, a current source I2, comparators comp1 and comp2, and an RS flip-flop IC1.

  Note that PNP transistors are used for the transistors Tr2 and Tr4, and NPN transistors are used for the transistor Tr3. The current source I2 is a constant current source of 1 μA, for example.

  The slope generation circuit 13 includes resistors R4 and R5, a capacitor C3, transistors Tr5 to Tr8, NMOS transistors N4 and N5, a PMOS transistor P8, current sources I3 to I6, and a voltage subtraction circuit 13a. The voltage subtraction circuit 13a includes resistors R11 to R14 and an operational amplifier OP1.

  Note that an NPN transistor is used as the transistor Tr6, and a PNP transistor is used as the transistors Tr5, Tr7, and Tr8. The current source I3 is, for example, a constant current source of 5 μA, and the current sources I4 to I6 are, for example, constant current sources of 20 μA.

  Next, the connection relationship of the circuit elements of the control circuit 10 will be described. The collector of the transistor Tr10 is connected to the power supply terminal VCC, and the emitter of the transistor Tr10 is connected to one end of the resistor R10.

  A power supply line L1 connected to the internal power supply VDD (5 V) of the control circuit 10 is connected to the base of the transistor Tr10, the input ends of the current sources I1 to I6, the sources of the PMOS transistors P1 to P4 and P6, and the collector of the transistor Tr6.

  The other end of the resistor R10 is connected to the feedback terminal FB, the base of the transistor Tr0, the collector of the transistor Tr0, and one end of the resistor R0, and the other end of the resistor R0 is connected to the drain of the NMOS transistor N1.

  The emitter of the transistor Tr0 is connected to one end of the resistor R31, and the other end of the resistor R31 is connected to one end of the resistor R32. The other end of the resistor R32 is connected to one end of the resistor R33, and the other end of the resistor R33 is connected to one end of the resistor R34 and the base of the transistor Tr8.

  The gate of the NMOS transistor N1 is connected to the output terminal of the current source I1, the drain of the PMOS transistor P1, the gates of the PMOS transistors P1 and P2, and the collector of the transistor Tr1. The back gate of the NMOS transistor N1 is connected to GND.

  The source of the NMOS transistor N1 is connected to the base of the transistor Tr1, and the emitter of the transistor Tr1 is connected to one end of the resistors R1 and R2. The drain of the PMOS transistor P2 is connected to the other end of the resistor R2 and the base of the transistor Tr2.

  The output terminal of the current source I2 is connected to the emitters of the transistors Tr2 and Tr4 and the base of the transistor Tr3. A voltage Va (for example, 2.5 V) is applied to the base of the transistor Tr4. The collector of the transistor Tr3 is connected to the drain of the PMOS transistor P3 and the gates of the PMOS transistors P3, P4, and P6.

  The emitter of the transistor Tr3 is connected to one end of the resistor R3, the drain of the PMOS transistor P4 is connected to the source of the PMOS transistor P5, and the drain of the PMOS transistor P6 is connected to the source of the PMOS transistor P7.

The drain of the PMOS transistor P5 is connected to the positive side input terminal of the comparator comp1, one end of the capacitor C1, and the drain of the NMOS transistor N2.
A voltage Vb (for example, 2.5 V) is applied to the negative input terminal of the comparator comp1, and the output terminal of the comparator comp1 is connected to the set terminal S of the RS flip-flop IC1.

The drain of the PMOS transistor P7 is connected to the positive side input terminal of the comparator comp2, one end of the capacitor C2, and the drain of the NMOS transistor N3.
A voltage Vc (for example, 0.6 V) is applied to the negative input terminal of the comparator comp2, and the output terminal of the comparator comp2 is connected to the reset terminal R of the RS flip-flop IC1.

  The output terminal Q of the RS flip-flop IC1 is connected to the gates of the PMOS transistors P5 and P8 and the gates of the NMOS transistors N2, N4 and N5. The output terminal (inverted output terminal) Qn of the RS flip-flop IC1 is connected to the gate of the PMOS transistor P7 and the gate of the NMOS transistor N3.

  The source of the PMOS transistor P8 is connected to the output terminal of the current source I3, and the drain of the PMOS transistor P8 is connected to the drain of the NMOS transistor N4, one end of the capacitor C3, and the base of the transistor Tr5. The source of the NMOS transistor N4 is connected to the other end of the capacitor C3 and GND.

  The emitter of the transistor Tr5 is connected to the output terminal of the current source I4 and the base of the transistor Tr6. The emitter of the transistor Tr6 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the drain of the NMOS transistor N5, the base of the transistor Tr7, and one end of the resistor R5.

  The emitter of the transistor Tr7 is connected to the output end of the current source I5 and one end of the resistor R11, and the emitter of the transistor Tr8 is connected to the output end of the current source I6 and one end of the resistor R12.

  The other end of the resistor R11 is connected to the negative input terminal of the operational amplifier OP1 and one end of the resistor R13, and the other end of the resistor R12 is connected to one end of the resistor R14 and the positive input terminal of the operational amplifier OP1. Is connected to the output terminal of the operational amplifier OP1.

  The ground line L2 connected to the GND of the control circuit 10 includes the other ends of the resistors R34, R1, R3, R5, and R14, the collectors of the transistors Tr2, Tr4, Tr5, Tr7, and Tr8, the other ends of the capacitors C1 and C2, and the NMOS transistor N2. , N3, N5.

  Here, the relationship between the feedback terminal voltage VFB applied to the feedback terminal FB of the control circuit 10 and the frequency of the clock signal ck generated by the oscillator circuit 12 will be described. When the feedback terminal voltage VFB increases from 0V, the frequency of the clock signal ck begins to increase from 0.7V of the feedback terminal voltage VFB, and when the feedback terminal voltage VFB reaches 1.15V, the frequency of the clock signal ck is increased. 60 kHz. The slope at which the frequency of the clock signal ck increases is 132 kHz / V. When the feedback terminal voltage VFB is 1.15 V or higher, the increase in frequency stops, and the frequency of the clock signal ck becomes constant at 60 kHz.

  Next, the operation of the feedback circuit 11 will be described. In the feedback circuit 11, a current is input to the base of the transistor Tr1, the transistor Tr1 is turned on, and a voltage is output through resistors R1 and R2 connected to the emitter of the transistor Tr1.

  Note that a resistor R0 and an NMOS transistor N1 are inserted between the feedback terminal FB and the base of the transistor Tr1 so as not to draw too much current from the feedback terminal FB to the base of the transistor Tr1.

  The resistor R0 and the NMOS transistor N1 serve to limit the base current flowing into the base of the transistor Tr1. Further, the transistor Tr1 can output a current from the emitter as long as the hFE (current amplification factor) is sufficiently high even if the base current is small. Since the base current is small, the influence on the voltage of the feedback terminal FB by drawing the current from the feedback terminal FB can be ignored. Further, the voltage drop from the voltage at the feedback terminal FB to the base voltage of the transistor Tr1 can be ignored.

  Here, when the transistor Tr1 whose base current is limited by the resistor R0 and the NMOS transistor N1 is turned on, the transistor Tr1 forms an emitter follower circuit. Therefore, the emitter voltage of the transistor Tr1, that is, the resistance R1, R2 is divided. The potential of the node n0 that is the pressure point is (VFB-Vbe). VFB is an input voltage applied to the feedback terminal FB, and Vbe is a base-emitter voltage of the transistor.

  Then, at the same time as the potential of the node n0 becomes (VFB−Vbe), a current flows through the PMOS transistor P1. Since the PMOS transistors P1 and P2 form a current mirror circuit, when a current flows through the PMOS transistor P1, a current also flows through the PMOS transistor P2.

  As a result, the voltage (VFB−Vbe) is amplified according to the resistance ratio ((R1 + R2) / R1), and the voltage signal ((R1 + R2) / R1) · (VFB−Vbe) is output from the feedback circuit 11. This is applied to the base of the transistor Tr2 of the oscillator circuit 12.

  Strictly speaking, the current flowing through the resistor R1 is the sum of the current flowing through the PMOS transistor P1 and the current flowing through the PMOS transistor P2, and the current flowing through the resistor R2 is the current flowing through the PMOS transistor P2. There is a difference between the currents flowing through the resistors R1 and R2. The current flowing through the PMOS transistor P2 needs to be sufficiently larger than the current flowing through the PMOS transistor P1 to such an extent that this difference can be ignored, and the mirror ratio between the PMOS transistor P1 and the PMOS transistor P2 is increased. For example, the mirror ratio is (current flowing in the PMOS transistor P1) :( current flowing in the PMOS transistor P2) = 1: 1.

  The current source I1 is, for example, a constant current source for supplying 1 μA, and serves as a drive current source for starting a current to flow through the PMOS transistor P1 when the transistor Tr1 is turned on.

  With the configuration described above, the feedback circuit 11 outputs a voltage with a magnification of ((R1 + R2) / R1) corresponding to the feedback terminal voltage VFB, that is, ((R1 + R2) / R1) · (VFB−Vbe). .

  Next, the operation of the oscillator circuit 12 will be described. In the oscillator circuit 12, first, looking at the relationship between the transistor Tr2 and the transistor Tr3, the transistor Tr2 constitutes an emitter follower circuit, so that the emitter voltage ((R1 + R2) / R1) · ( VFB−Vbe) + Vbe is applied to the base of the transistor Tr3.

  Since the transistor Tr3 also constitutes an emitter follower circuit, the emitter voltage of the transistor Tr3 is {((R1 + R2) / R1) · (VFB−Vbe) + Vbe} −Vbe. That is, the emitter voltage of the transistor Tr3 is ((R1 + R2) / R1) · (VFB−Vbe), which is the same voltage as the output of the feedback circuit 11 (the transistors Tr2 and Tr3 function as a buffer for canceling Vbe. Play).

  On the other hand, the transistor Tr4 serves to limit the upper limit of the emitter voltage of the transistor Tr3 to the voltage Va. Since the transistor Tr3 also constitutes an emitter follower circuit, and the transistor Tr4 is connected between the transistor Tr2 and the transistor Tr3, the base voltage of the transistor Tr3 is the base voltage Va between the transistor Tr4 and the base-emitter. Clamped by the sum (Va + Vbe) with the voltage Vbe.

  Therefore, the emitter voltage Ve of the transistor Tr3 is the smaller of the base voltage of the transistor Tr2 or the base voltage of the transistor Tr4. That is, the base voltage of the transistor Tr2 is the output voltage of the feedback circuit 11 described above. If the base voltage Va of the transistor Tr4 is 2.5 V, the emitter voltage Ve of the transistor Tr3 is expressed by the following equation (1). It can be expressed as Note that min {a, b} indicates that a smaller value of a or b is selected.

  As a result, the current IR3 flowing through the resistor R3 is expressed by Equation (2). If the emitter current and collector current of the transistor Tr3 are the same, the current IR3 also flows through the PMOS transistor P3.

  On the other hand, in the oscillator circuit 12, the current IR3 obtained by performing the VI conversion (voltage-current conversion) is 1 / M times (M = 1, 2,...) By the current mirror circuit of the PMOS transistors P3, P4 and P6. The clock signal ck is generated by charging the capacitors C1 and C2 using the current (charging current).

  For example, in order to charge the capacitor using the current IR3 made 1/4 by the current mirror circuit of the PMOS transistors P3, P4 and P6, the mirror ratio of the PMOS transistors P3, P4 and P6 is 4: 1. : 1.

  FIG. 13 is a diagram showing operation waveforms of the oscillator circuit. The horizontal axis is time, and the vertical axis is voltage. The voltage Vb applied to the negative input terminal (−) of the comparator comp1 is 2.5V, the voltage Vc applied to the negative input terminal (−) of the comparator comp2 is 0.6V, and the VDD voltage is 5V. explain.

  The voltage Vosc1 is a voltage at the node n1 in the oscillator circuit 12 shown in FIG. 11, and becomes the charging voltage of the capacitor C1. The node n1 is a portion connected to the drain of the PMOS transistor P5, the positive input terminal (+) of the comparator comp1, one end of the capacitor C1, and the drain of the NMOS transistor N2.

  When the capacitor C1 is charged with a constant current, the time dt1 is a time from when the capacitor C1 starts to be charged with an initial value of 0V until the charging voltage Vosc1 becomes 2.5V.

  Since the voltage Vosc1 is input to the positive input terminal (+) of the comparator comp1 and 2.5V is input to the negative input terminal (−), the voltage Vosc1 of the comparator comp1 is 2. An H level signal is output only when the voltage reaches 5V.

As described above, the voltage comp1out having a pulse-like waveform as shown in FIG. 13 is output from the output terminal of the comparator comp1 which repeats the L level and the H level.
On the other hand, the voltage Vosc2 is a voltage at the node n2 in the oscillator circuit 12 shown in FIG. 11, and becomes the charging voltage of the capacitor C2. Note that the node n2 is a portion connected to the drain of the PMOS transistor P7, the positive input terminal (+) of the comparator comp2, one end of the capacitor C2, and the drain of the NMOS transistor N3.

  When the capacitor C2 is charged with a constant current, the time dt2 is a time from when the capacitor C2 starts to be charged with an initial value of 0 V until the charging voltage Vosc2 reaches a voltage of 0.6V.

  Further, since the voltage Vosc2 is input to the positive input terminal (+) of the comparator comp2 and 0.6V is input to the negative input terminal (−), the voltage Comp of the comparator comp2 is 0. Only when the voltage reaches 6V, the H level signal is output.

As described above, the voltage comp2out having a pulse-like waveform as shown in FIG. 13 is output from the output terminal of the comparator comp2.
On the other hand, the output signal comp1out of the comparator comp1 is input to the set terminal S of the RS flip-flop IC1, and the output signal comp2out of the comparator comp2 is input to the reset terminal R of the RS flip-flop IC1.

  By using the output signal of the RS flip-flop IC1 and performing the following control, the output signal comp1out of the comparator comp1 and the output signal comp2out of the comparator comp2 are oscillated so as not to simultaneously become H level. Yes. The oscillation operation will be described below.

  During the charging time dt1 of the capacitor C1, the L level is output from the output terminal Q of the RS flip-flop IC1, and the H level is output from the output terminal Qn of the RS flip-flop IC1.

  In this case, since the output terminal Q of the RS flip-flop IC1 is at the L level, the PMOS transistor P5 is turned on, the NMOS transistor N2 is turned off, and the capacitor C1 is charged with the charging current flowing through the PMOS transistor P5.

  Since the output terminal Qn of the RS flip-flop IC1 is at the H level, the PMOS transistor P7 is turned off, the NMOS transistor N3 is turned on, and the capacitor C2 is discharged.

  On the other hand, during the charging time dt2 of the capacitor C2, the H level is output from the output terminal Q of the RS flip-flop IC1, and the L level is output from the output terminal Qn of the RS flip-flop IC1.

  In this case, since the output terminal Q of the RS flip-flop IC1 is at the H level, the PMOS transistor P5 is turned off, the NMOS transistor N2 is turned on, and the capacitor C1 is discharged.

  Since the output terminal Qn of the RS flip-flop IC1 is at the L level, the PMOS transistor P7 is turned on, the NMOS transistor N3 is turned off, and the capacitor C2 is charged with the charging current flowing through the PMOS transistor P7.

  Thus, in the time zone dt1, the capacitor C1 is charged and the capacitor C2 is discharged. In the time zone dt2, the capacitor C1 is discharged and the capacitor C2 is charged. By repeating such charge and discharge, a clock signal ck having a frequency as shown in FIG. 13 is generated.

  Hereinafter, the generation operation of the oscillation frequency will be described using mathematical expressions. If the charging current for charging both the capacitors C1 and C2 is the current Ich, the current Ich is ¼ of the current IR3 based on the mirror ratio of the current mirror circuit, and is given by Equation (3).

Further, if the charge of the capacitor is Q, the capacitance value is C, the charging current is i, the charging time is t, and the charging voltage of the capacitor is V, i = dQ / dt = d (CV) / dt = C · dV / dt.
Therefore, the following equation (4a) is established for charging the capacitor C1, and the following equation (4b) is established for charging the capacitor C2.

  The clock signal ck that is the output of the oscillator circuit 12 is the output of the RS flip-flop IC1 that is set by the output of the comparator comp1 and reset by the output of the comparator comp2, and the cycle dt of the clock signal ck is dt = dt1 + dt2.

  Therefore, the frequency fosc of the clock signal ck is calculated by the following expression (5) based on the expressions (4a) and (4b).

  Next, the operation of the slope generation circuit 13 will be described. The operational amplifier OP1 included in the voltage subtracting circuit 13a in the slope generating circuit 13 subtracts the voltage at the node nB in the slope generating circuit 13 from the voltage at the node nC in the feedback circuit 11 to generate the slope voltage V_slope.

The voltage at the node nB is a voltage obtained by dividing the voltage at the node nA by the resistors R4 and R5 in the process of charging the capacitor C3 during the charging time dt1.
Note that the node nA is a portion connected to the drain of the PMOS transistor P8, the base of the transistor Tr5, the drain of the NMOS transistor N4, and one end of the capacitor C3.

  The node nB is a location connected to one end of the resistors R4 and R5, the drain of the NMOS transistor N5 and the base of the transistor Tr7, and the node nC is a location connected to one end of the resistors R33 and R34.

  Here, the voltage at the node nA is (5 μA × t) / C3, where the output current of the current source I3 is 5 μA and the time from the start of charging the capacitor C3 is t. Therefore, the voltage at the node nB is ((5 μA × t) / C3) × (R5 / (R4 + R5)). This is because, similarly to the transistors Tr2 and Tr3, the transistors Tr5 and Tr6 constitute an emitter follower circuit and cancel each other's Vbe, so that the voltage at the node nA and the emitter voltage of the transistor Tr6 are equal.

  The voltage at the node nC is a voltage obtained by dividing the feedback terminal voltage VFB by the resistors R31 to R34 with respect to the voltage obtained by dropping the feedback terminal voltage VFB by the base-emitter voltage Vbe of the transistor Tr0.

  That is, the voltage at the node nC is (VFB−Vbe) × R34 / (R31 + R32 + R33 + R34). If all the resistors R31 to R34 are 20 kΩ, the voltage is (VFB−Vbe) / 4.

  FIG. 14 is a diagram illustrating operation waveforms of the slope generation circuit. The horizontal axis is time, and the vertical axis is voltage. When the capacitor C3 is charged with a constant current from 0V, when the charging time dt1 ends, the A voltage at the node nA becomes (5 μA × dt1) / C3.

  Further, as the A voltage at the node nA increases from 0V toward the final value (5 μA × dt1) / C3, the B voltage at the node nB increases from 0 V to the final value ((5 μA × dt1) / C3) × ( It rises towards R5 / (R4 + R5)).

Here, the maximum value of the slope voltage V_slope is max1 (V_slope), and the minimum value of the slope voltage V_slope is min1 (V_slope).
As the B voltage increases from 0 V toward ((5 μA × dt1) / C3) × (R5 / (R4 + R5)) as the capacitor C3 is charged, the slope voltage V_slope is changed from max1 (V_slope) to min1 (V_slope). It gradually decreases toward

  In this case, the maximum value max1 (V_slope) of the slope voltage V_slope is the following equation (6a), and the minimum value min1 (V_slope) of the slope voltage V_slope is the following equation (6b). The resistance values of the resistors R11 to R14 are R11 = R12 = R13 = R14.

  Therefore, the change amount Var of the slope voltage V_slope per time is calculated by the following equation (7).

  Note that the increase in the voltage at the node nC due to the base current of the transistor Tr8 of the slope generation circuit 13 flowing into the resistance R34 of the feedback circuit 11 is ignored because the base current of the transistor Tr8 is small. ing.

  Hereinafter, calculation is performed using specific numerical values. R1 = 60 kΩ, R2 = 270 kΩ, R3 = 224 kΩ, R4 = 475 kΩ, R5 = 25 kΩ, C1 = C2 = 15 pF, C3 = 20 pF.

  In order to obtain the VFB range when the output voltage ((R1 + R2) / R1) · (VFB−Vbe) from the feedback circuit 11 to the oscillator circuit 12 becomes 2.5V or more, ((R1 + R2) / R1) · ( Substituting the above numerical values for VFB−Vbe) ≧ 2.5V, VFB ≧ 1.15V.

  Therefore, when VFB ≧ 1.15V, if the above numerical value is substituted into the equation (5), the frequency fosc of the clock signal ck = 60 kHz is calculated as in the equation (8).

  Further, the change amount Var of the slope voltage V_slope per time at this time is calculated as Var = −10 mV / μs as shown in equation (9) when the above numerical value is substituted into equation (7).

  On the other hand, in order to obtain the VFB range when the output voltage ((R1 + R2) / R1) · (VFB−Vbe) of the feedback circuit 11 is 2.5V or less, ((R1 + R2) / R1) · (VFB−Vbe) ) Substituting the above numerical value into ≦ 2.5V, VFB ≦ 1.15V is obtained.

  Here, assuming that the change width of the frequency fosc of the clock signal ck in the minute change section is Δfosc and the change width of the feedback terminal voltage VFB in the minute change section is ΔVFB, the frequency fosc of the clock signal ck when VFB ≦ 1.15V The rate of change from the feedback terminal voltage VFB is Δfosc / ΔVFB.

  Therefore, when VFB ≦ 1.15V, if the above numerical value is substituted into Expression (5), the change rate Δfosc / ΔVFB is calculated as shown in Expression (10), and Δfosc / ΔVFB = 132 kHz / V Is calculated.

  From the equation (10), the rate of change of the frequency of the clock signal ck is a resistance ratio ((R1 + R2) which is a magnification set by the feedback circuit 11 to a value obtained by dividing the upper limit frequency 60 kHz determined by 2.5V by 2.5V. ) / R1) = 5.5.

JP 2007-336742 A

  In the conventional control circuit 10 as described above, a slope generation circuit that generates the slope voltage V_slope is configured by a subtraction circuit using the operational amplifier OP1 shown in FIG. However, when a circuit is configured using an operational amplifier, the circuit scale and cost increase.

  The present invention has been made in view of the above points, and is a switching power supply that realizes the same function as the conventional control circuit 10 by a simple circuit configuration without using an operational amplifier and reduces the circuit scale. An object of the present invention is to provide a control circuit and a slope generation circuit of an apparatus.

  In order to solve the above-described problem, a control circuit for a current mode control switching power supply device that provides a constant voltage by feeding back an inductor current of a transformer is provided. The control circuit of the switching power supply device includes a feedback circuit, an oscillator circuit, and a slope generation circuit.

  The feedback circuit outputs a voltage signal corresponding to the feedback voltage fed back from the secondary side output of the transformer. The oscillator circuit converts a voltage signal into a current signal, charges a capacitor with a charging current proportional to the current signal, and generates a clock signal having a predetermined oscillation frequency and a triangular wave voltage synchronized with the clock signal. The slope generation circuit generates a slope compensation current using a current mirror circuit from a current obtained by converting a triangular wave voltage using a first resistor, and converts the slope compensation current into a voltage and a feedback voltage of the voltage using a second resistor. A slope voltage is generated by subtracting from the divided voltage.

  A slope generation circuit is also provided. The slope generation circuit includes a slope compensation source current generation circuit and a voltage subtraction circuit. The slope compensation original current generation circuit is generated by charging the capacitor with a charging current proportional to the current signal generated from the voltage signal according to the feedback voltage fed back from the secondary output of the transformer, and charging the capacitor. A triangular wave voltage synchronized with a clock signal having a predetermined oscillation frequency is received, and a slope compensation original current is generated by a current mirror circuit from a current obtained by converting the triangular wave voltage using a first resistor. The voltage subtraction circuit generates a slope compensation current by copying the slope compensation original current by another current mirror circuit, and the second resistance converts the slope compensation current into a voltage and the feedback voltage of the voltage is divided. A slope voltage is generated by subtracting from the divided voltage.

  The circuit scale can be reduced.

It is a figure which shows the structural example of a part of control circuit of the technique of this invention in a switching power supply device. It is a figure which shows the schematic whole structure example of the control circuit of this invention. It is a figure for demonstrating stabilization control of the output voltage in the control circuit of the technique of this invention. It is a figure which shows the structural example of the control circuit of the technique of this invention. It is a figure which shows the structural example of the control circuit of the technique of this invention. It is a figure which shows the operation | movement waveform of an oscillator circuit of the control circuit of the technique of this invention. It is a figure which shows the operation | movement waveform of a slope generation circuit. It is a figure which shows the structural example of the switching power supply device of current mode control. FIG. 9 is a diagram illustrating a schematic overall configuration example of a control circuit illustrated in FIG. 8. It is a figure for demonstrating stabilization control of the output voltage in a switching power supply device. It is a figure which shows the structural example of the conventional control circuit which uses an operational amplifier for a slope generation circuit. It is a figure which shows the structural example of the conventional control circuit which uses an operational amplifier for a slope generation circuit. It is a figure which shows the operation | movement waveform of the oscillator circuit of the conventional control circuit which uses an operational amplifier for a slope generation circuit. It is a figure which shows the operation | movement waveform of the slope generation circuit of the conventional control circuit which uses an operational amplifier for a slope generation circuit.

Hereinafter, embodiments will be described with reference to the drawings.
FIG. 1 is a diagram showing a configuration example of a part of a control circuit according to the present invention suitable for a switching power supply device. This control circuit is a circuit that controls the switching power supply device of current mode control that feeds back the inductor current of the transformer together with the output voltage to make the output voltage constant, and includes a feedback circuit 11, an oscillator circuit 12-1, and A slope generation circuit 13-1 is provided.

  The feedback circuit 11 outputs a voltage signal corresponding to the feedback voltage VFB fed back from the secondary side output of the transformer. The oscillator circuit 12-1 converts a voltage signal into a current signal, charges a capacitor with a charging current proportional to the current signal, generates a clock signal having a predetermined oscillation frequency, and outputs a triangular wave voltage Vosc0 synchronized with the clock signal. To do.

  The slope generation circuit 13-1 includes a slope compensation original current generation circuit 13a-1 and a voltage subtraction circuit 13b-1. The slope compensation original current generation circuit 13a-1 includes a resistor R41 (first resistor), transistors Tr11 and Tr12, PMOS (P-Channel Metal Oxide Semiconductor) transistors P11 and P12, and a current source I7.

  The voltage subtracting circuit 13b-1 includes a resistor R42 (second resistor) and NMOS (N-Channel Metal Oxide Semiconductor) transistors N11 and N12. Note that a PNP transistor is used for the transistor Tr11, and an NPN transistor is used for the transistor Tr12.

  The base of the transistor Tr11 is an input terminal of the slope generation circuit 13-1, and the triangular wave voltage Vosc0 is applied thereto. The input terminal of the current source I7 is connected to the power supply VDD and the sources of the PMOS transistors P11 and P12, and the output terminal of the current source I7 is connected to the emitter of the transistor Tr11 and the base of the transistor Tr12.

  The collector of the transistor Tr12 is connected to the drain of the PMOS transistor P11 and the gates of the PMOS transistors P11 and P12. The emitter of the transistor Tr12 is connected to one end of the resistor R41, and the drain of the PMOS transistor P12 is connected to the drain of the NMOS transistor N12 and the gates of the NMOS transistors N11 and N12.

  The divided voltage Vd is applied to one end of the resistor R42, and the drain of the NMOS transistor N11 is connected to the other end of the resistor R42. The collector of the transistor Tr11, the other end of the resistor R41, and the sources of the NMOS transistors N11 and N12 are connected to GND (ground).

  Here, the slope compensation original current generation circuit 13a-1 is a current obtained by converting the triangular wave voltage Vosc0 by the resistor R41 (the transistors Tr11 and Tr12 each constitute an emitter follower circuit and cancels Vbe each other. The applied voltage is equal to the triangular wave voltage Vosc0), and the slope compensation original current Is0 is generated by the current mirror circuit.

  The voltage subtracting circuit 13b-1 converts the slope compensation current Is into a voltage by the resistor R42 and subtracts the converted voltage from the divided voltage Vd obtained by dividing the feedback voltage VFB to obtain the slope voltage V_slope. Generate. With this configuration, the control circuit 10-1 can reduce the circuit scale.

  Next, the control circuit of the switching power supply device to which the technology of the present invention is applied will be described in detail. FIG. 2 is a diagram showing a schematic overall configuration example of the control circuit of the present invention. An example of the internal configuration around the feedback terminal FB, the current detection terminal CS, and the output terminal OUT is shown.

  The control circuit 10-1 includes a feedback circuit 11, an oscillator circuit 12-1, a slope generation circuit 13-1, a PWM comparator 21, an RS flip-flop 22, and a buffer 23. The feedback circuit 11 is the same as the circuit shown in FIG.

  Here, the positive input terminal of the PWM comparator 21 is connected to the current detection terminal CS, and the current detection signal voltage VCS is input. The negative input terminal of the PWM comparator 21 is input with the slope voltage V_slope.

  The reset terminal R of the RS flip-flop 22 is connected to the output terminal of the PWM comparator 21, and the clock signal ck1 from the oscillator circuit 12-1 is input to the set terminal S of the RS flip-flop 22.

  The positive output terminal Q of the RS flip-flop 22 is connected to the input terminal of the buffer 23, and the output terminal of the buffer 23 is connected to the output terminal OUT. A drive signal VOUT for switching the switching element PT1 is output from the output terminal OUT.

FIG. 3 is a diagram for explaining the stabilization control of the output voltage in the control circuit of the technique of the present invention. The horizontal axis is time, and the vertical axis is voltage.
[S11] The oscillator circuit 12-1 outputs a clock signal ck1 having a constant period.

[S11a] The drive signal VOUT from the RS flip-flop 22 set by the clock signal ck1 is output from the output terminal OUT via the buffer 23.
[S12] When the switching element PT1 is turned on by the drive signal VOUT (VOUT = H), a current flows through the primary winding Tn1 of the transformer T1, and the current detection signal voltage VCS applied to the current detection terminal CS increases.

  [S13] The slope generation circuit 13-1 generates a slope voltage V_slope from the feedback terminal voltage (feedback voltage) VFB applied to the feedback terminal FB in synchronization with the clock signal ck1. Note that the slope voltage V_slope is a voltage that gradually decreases from the divided voltage (VFB−Vbe) / 4 of the feedback terminal voltage VFB, as will be described later. Note that the voltage dividing ratio of the voltage dividing circuit including the resistors R31 to R34 is 1/4.

  [S14] The PWM comparator 21 compares the slope voltage V_slope with the current detection signal voltage VCS, and outputs an H level signal when the current detection signal voltage VCS reaches the slope voltage V_slope.

  [S15] When the RS flip-flop 22 is reset by the H level signal output from the PWM comparator 21, and the drive signal VOUT from the output terminal OUT becomes L level, the switching element PT1 is turned off (VOUT = L). At this time, the current detection signal voltage VCS becomes 0 V, and the output of the PWM comparator 21 also becomes L level.

  Thereafter, this operation is repeated with the clock signal ck1 having a fixed period, and the feedback terminal voltage VFB changes according to the load 2, whereby the duty (time ratio) of the drive signal VOUT is changed to control the switching of the switching element PT1. Thereby, it controls so that the output voltage of a switching power supply device may become a setting value.

  4 and 5 are diagrams showing examples of the configuration of the control circuit according to the technique of the present invention. The control circuit 10-1 includes a feedback circuit 11, an oscillator circuit 12-1, and a slope generation circuit 13-1. 4 shows the feedback circuit 11 and the oscillator circuit 12-1, and FIG. 5 shows the slope generation circuit 13-1.

The feedback circuit 11 is the same as the feedback circuit 11 shown in FIG.
The oscillator circuit 12-1 includes a resistor R3a, a capacitor C0, transistors Tr2 to Tr4, an NMOS transistor N2, PMOS transistors P3 and P4, a current source I2, and a comparator comp1.

  PNP transistors are used for the transistors Tr2 and Tr4, and NPN transistors are used for the transistor Tr3. The current source I2 is a constant current source of 1 μA, for example.

  Here, in the oscillator circuit 12-1, the transistor Tr2 (first transistor) receives the voltage signal output from the feedback circuit 11 as a base. The current source I2 (first current source) supplies a current flowing through the transistor Tr2.

  The transistor Tr3 (second transistor) receives the emitter voltage of the transistor Tr2 at the base. The transistor Tr4 (third transistor) determines the upper limit of the emitter voltage of the transistor Tr3. This is because the transistors Tr2 and Tr4 constitute an emitter follower circuit, so that the base voltage of the transistor Tr3 is (the smaller one of the bases of the transistors Tr2 and Tr4 + the base-emitter voltage Vbe). This is because the emitter voltage of the transistor Tr3 becomes (base voltage of the transistor Tr3 -Vbe) because the emitter follower circuit is configured (the transistors Tr2, Tr3, Tr4 are integrated in the same semiconductor). The base-emitter voltage Vbe is assumed to be equal).

  The emitter voltage of the transistor Tr3 is applied to the resistor R3a, and the current signal IR3a flows. The PMOS transistor P3 (first PMOS transistor) and the PMOS transistor P4 (second PMOS transistor) form a first current mirror circuit, and the first current mirror circuit has a resistor R3a according to the mirror ratio. Is copied (copied) to output a charging current Ich1 for the capacitor C0.

  The comparator comp1 generates and outputs the clock signal ck1 according to the comparison result between the charging voltage of the capacitor C0 that becomes the triangular wave voltage Vosc0 and the threshold voltage Vb. The NMOS transistor N2 (switch, first NMOS transistor) is turned on based on the clock signal ck1, and discharges the capacitor C0.

  On the other hand, the slope generation circuit 13-1 includes a slope compensation original current generation circuit 13a-1 and a voltage subtraction circuit 13b-1. The slope compensation original current generation circuit 13a-1 includes a resistor R41, transistors Tr11 and Tr12, PMOS transistors P11 and P12, and a current source I7. Voltage subtraction circuit 13b-1 includes a resistor R42 and NMOS transistors N11 and N12.

  A PNP transistor is used for the transistor Tr11, and an NPN transistor is used for the transistor Tr12. The current source I7 is a constant current source of 1 μA, for example.

  Here, the transistor Tr11 (fourth transistor) receives the triangular wave voltage Vosc0 as a base. The current source I7 (second current source) supplies a current flowing through the transistor Tr11. The transistor Tr12 (fifth transistor) receives the emitter voltage of the transistor Tr11 at the base.

  A current R41 flows through the resistor R41 (first resistor) when the emitter voltage of the transistor Tr12 is applied. The PMOS transistor P11 (third PMOS transistor) and the PMOS transistor P12 (fourth PMOS transistor) form a second current mirror circuit, and the second current mirror circuit generates a current IR41 flowing through the resistor R41. The replicated slope compensation original current Is0 is output according to the mirror ratio.

  The resistor R42 (second resistor) is applied with a divided voltage Vd at one end and a slope voltage V_slope from the other end. The NMOS transistor N11 (second NMOS transistor) and the NMOS transistor N12 (third NMOS transistor) form a third current mirror circuit, and the third current mirror circuit outputs from the second current mirror circuit. The slope compensation original current Is0 is duplicated (at a mirror ratio of 1: 1) to generate the slope compensation current Is, which is supplied from the other end of the resistor R42.

  Next, the connection relationship of the circuit elements of the control circuit 10-1 will be described. The collector of the transistor Tr10 is connected to the power supply terminal VCC, and the emitter of the transistor Tr10 is connected to one end of the resistor R10.

  The power supply line L1-1 connected to the internal power supply VDD (5V) of the control circuit 10-1 is connected to the base of the transistor Tr10, the input ends of the current sources I1, I2, and I7, and the sources of the PMOS transistors P1 to P4, P11, and P12. To do.

  The other end of the resistor R10 is connected to the feedback terminal FB, the base of the transistor Tr0, the collector of the transistor Tr0, and one end of the resistor R0, and the other end of the resistor R0 is connected to the drain of the NMOS transistor N1. The transistor Tr0 is the same as a diode because the base and collector are connected. In this case, the collector corresponds to the anode and the emitter corresponds to the cathode.

  The emitter of the transistor Tr0 is connected to one end of the resistor R31, and the other end of the resistor R31 is connected to one end of the resistor R32. The other end of the resistor R32 is connected to one end of the resistor R33, and the other end of the resistor R33 is connected to one end of the resistor R34 and one end of the resistor R42.

  The gate of the NMOS transistor N1 is connected to the output terminal of the current source I1, the drain of the PMOS transistor P1, the gates of the PMOS transistors P1 and P2, and the collector of the transistor Tr1. The back gate of the NMOS transistor N1 is connected to GND.

  The source of the NMOS transistor N1 is connected to the base of the transistor Tr1, and the emitter of the transistor Tr1 is connected to one end of the resistors R1 and R2. The drain of the PMOS transistor P2 is connected to the other end of the resistor R2 and the base of the transistor Tr2.

  The output terminal of the current source I2 is connected to the emitters of the transistors Tr2 and Tr4 and the base of the transistor Tr3. A voltage Va (for example, 2.5 V) is applied to the base of the transistor Tr4. The collector of the transistor Tr3 is connected to the drain of the PMOS transistor P3 and the gates of the PMOS transistors P3 and P4.

  The emitter of the transistor Tr3 is connected to one end of the resistor R3a, and the drain of the PMOS transistor P4 is connected to the base of the transistor Tr11, the positive input terminal of the comparator comp1, one end of the capacitor C0, and the drain of the NMOS transistor N2.

  A voltage Vb (for example, 2.5 V) is applied to the negative input terminal of the comparator comp1, and the output terminal of the comparator comp1 is connected to the gate of the NMOS transistor N2.

  The emitter of the transistor Tr11 is connected to the output terminal of the current source I7 and the base of the transistor Tr12. The collector of the transistor Tr12 is connected to the drain of the PMOS transistor P11 and the gates of the PMOS transistors P11 and P12, and the emitter of the transistor Tr12 is connected to one end of the resistor R41.

  The other end of the resistor R42 is connected to the drain of the NMOS transistor N11, and the drain of the PMOS transistor P12 is connected to the drain of the NMOS transistor N12 and the gates of the NMOS transistors N11 and N12.

  The ground line L2-1 connected to the GND of the control circuit 10-1 includes the other ends of the resistors R34, R1, R3a, and R41, the collectors of the transistors Tr2, Tr4, and Tr11, the other end of the capacitor C0, and the NMOS transistors N2, N11, and N12. Connect to the source.

Next, the operation of the control circuit 10-1 will be described. Note that the feedback circuit 11 is the same circuit as that in FIG.
First, the oscillator circuit 12-1 will be described. In the current mirror circuit of the PMOS transistors P3 and P4, since the mirror ratio of the PMOS transistors P3 and P4 is 4: 1, the capacitor C0 is charged with a current obtained by reducing the current IR3a flowing through the resistor R3a to ¼.

  That is, the charging current of the capacitor C0 is 1/4 of the drain current of the PMOS transistor P3, and is expressed by the following equation (11).

  If the charging time of the capacitor C0 is dt, the following equation (12) is established for the capacitor C0 in the same manner as the above equations (4a) and (4b).

  Since the clock signal ck1 that is the output of the oscillator circuit 12-1 is the output of the comparator comp1, the frequency fosc1 of the clock signal ck1 is calculated by the following equation (13) based on the equation (12). The

  FIG. 6 is a diagram showing operation waveforms of the oscillator circuit. The horizontal axis is time, and the vertical axis is voltage. The voltage Vb applied to the negative input terminal (−) of the comparator comp1 is 2.5V, and the VDD voltage is 5V.

  The triangular wave voltage Vosc0 is a voltage at the node n11 in the oscillator circuit 12-1 shown in FIG. 4, and becomes a charging voltage of the capacitor C0. The node n11 is a portion connected to the drain of the PMOS transistor P4, the base of the transistor Tr11, the positive input terminal (+) of the comparator comp1, one end of the capacitor C0, and the drain of the NMOS transistor N2.

  When the capacitor C0 is charged with a constant current, the time dt is set as one cycle charging time from when the capacitor C0 starts to be charged from 0V until the charging voltage Vosc0 becomes 2.5V.

  Further, since the triangular wave voltage Vosc0 is input to the positive side input terminal (+) of the comparator comp1 and 2.5 V is input to the negative side input terminal (−), the triangular wave voltage Vosc0 is input to the comparator comp1. Only when the voltage reaches 2.5 V, the H level signal is output.

  As described above, the voltage of the pulse waveform as shown in FIG. 6 is output from the output terminal of the comparator comp1, and the clock waveform is generated by the oscillator circuit 12-1. Signal ck1 is obtained.

  Next, the operation of the slope generation circuit 13-1 will be described. The emitter voltage of the transistor Tr12 is converted into a current by the resistor R41, and this current becomes the drain current of the PMOS transistor P11. As described above, since the emitter voltage of the transistor Tr12 is equal to Vosc0, the drain current of the PMOS transistor P11 is (Vosc0 / R41).

  In the current mirror circuit of the PMOS transistors P11 and P12, the mirror ratio of the PMOS transistors P11 and P12 is 5: 1. Further, in the current mirror circuit of the NMOS transistors N11 and N12, the mirror ratio of the NMOS transistors N11 and N12 is 1: 1.

  Therefore, the current Is obtained by reducing the drain current of the PMOS transistor P11 to 1/5 also flows through the NMOS transistor N11. That is, a current having the same value as the drain current of the PMOS transistor P12 also flows through the NMOS transistor N11. A current I_N11 flowing through the NMOS transistor N11 is a slope compensation current Is, and is Is = I_N11 = (Vosc0 / R41) × (1/5).

  The current I_N11 (slope compensation current Is) flowing through the NMOS transistor N11 is converted into a voltage by the resistor R42, and the divided voltage Vd (= ((VFB−Vbe) / 4)) at the node nC of the feedback circuit 11 is converted into the resistor R42. The slope voltage V_slope is generated by subtracting the voltage obtained by converting the slope compensation current Is via

  FIG. 7 is a diagram illustrating operation waveforms of the slope generation circuit. The horizontal axis of the graph of the clock signal ck1 and the slope voltage V_slope is time, the vertical axis is voltage, the horizontal axis of the current I_N11 graph is time, and the vertical axis is current. The description in the next section is for the case where the emitter voltage of the transistor Tr3 is the upper limit of 2.5V. However, in other cases, the following 2.5V is set to ((R1 + R2) / R1) · (VFB−Vbe). ) Can be considered similarly.

  The current I_N11 flowing through the NMOS transistor N11 increases from 0 μA to (2.5 V / R41) × (1/5) in one cycle of the clock signal ck1 (in the charging time dt of the capacitor C0). Here, the maximum value of the slope voltage V_slope is set to max2 (V_slope), and the minimum value of the slope voltage V_slope is set to min2 (V_slope).

  As the current I_N11 increases from 0 μA to (2.5 V / R41) × (1/5), the slope voltage V_slope gradually decreases from max2 (V_slope) to min2 (V_slope).

  The maximum value max2 (V_slope) of the slope voltage V_slope is represented by the following formula (14a), and the minimum value min2 (V_slope) of the slope voltage V_slope is represented by the following formula (14b).

  Therefore, the change amount Var1 of the slope voltage V_slope per time is calculated as in the following equation (15).

  From the equation (15), the change amount Var1 of the slope voltage V_slope per time is determined by the resistance ratio of the resistors R41 and R42. Note that a decrease in the divided voltage Vd due to the current I_N11 flowing with respect to 20 kΩ × 3 of the resistors R31 to R33 of the feedback circuit 11 is ignored because the current I_N11 is small.

Here, it calculates using a specific numerical value. R1 = 60 kΩ, R2 = 270 kΩ, R3a = 278 kΩ, R41 = 240 kΩ, R42 = 80 kΩ, and C0 = 15 pF.
When the output voltage ((R1 + R2) / R1) · (VFB−Vbe) from the feedback circuit 11 to the oscillator circuit 12-1 is 2.5 V or more, that is, ((R1 + R2) / R1) · (VFB−Vbe) ≧ 2. Substituting the above numerical value for .5V results in VFB ≧ 1.15V.

  Therefore, when VFB ≧ 1.15V, if the above numerical value is substituted into the equation (13), the frequency fosc1 of the clock signal ck1 is calculated as 60 kHz as in the equation (16).

  Further, the change amount Var1 of the slope voltage V_slope per time at this time is calculated as Var1 = −10 mV / μs as shown in Expression (17) when the above numerical value is substituted into Expression (15).

  On the other hand, when the output voltage ((R1 + R2) / R1) · (VFB−Vbe) of the feedback circuit 11 is 2.5V or less, that is, ((R1 + R2) / R1) · (VFB−Vbe) ≦ 2.5V Substituting a numerical value results in VFB ≦ 1.15V.

  Here, the rate of change between the frequency fosc1 of the clock signal ck1 and the feedback terminal voltage VFB is Δfosc1 / ΔVFB. Therefore, when VFB ≦ 1.15V, if the above numerical value is substituted into equation (13), the rate of change is calculated as in equation (18) and Δfosc1 / ΔVFB = 132 kHz / V. .

As described above, also in the control circuit 10-1 having the simplified circuit configuration of the invention, the same function as that of the control circuit 10 including the operational amplifier is realized.
As described above, according to the present invention, the slope compensation current is generated using the current mirror circuit, and the slope voltage is generated by subtracting the slope compensation current from the feedback terminal voltage VFB via the resistance value. did. As a result, the slope compensation function can be realized with a simple circuit having a small number of elements without using an operational amplifier.

  As mentioned above, although embodiment was illustrated, the structure of each part shown by embodiment can be substituted by the other thing which has the same function. Moreover, other arbitrary structures and processes may be added.

2 Load 10, 10-1 Control circuit 11 Feedback circuit 12, 12-1 Oscillator circuit 13, 13-1 Slope generation circuit 13a-1 Slope compensation original current generation circuit 13a, 13b-1 Voltage subtraction circuit 100 Switching power supply device R41 1st 1 resistor R42 2nd resistor T1 transformer Tr11 PNP transistor Tr12 NPN transistor P11, P12 PMOS transistor PC1 photocoupler PT1 switching element N11, N12 NMOS transistor I7 current source VDD internal power supply VFB feedback terminal voltage (feedback voltage)
Vosc0 Triangular wave voltage Vd Divided voltage Is Slope compensation current V_slope Slope voltage

Claims (6)

In the control circuit of the switching power supply device of current mode control that feeds back the inductor current of the transformer to achieve constant voltage,
A feedback circuit that outputs a voltage signal corresponding to a feedback voltage fed back from the secondary side output of the transformer;
An oscillator circuit that converts the voltage signal into a current signal, charges a capacitor with a charging current proportional to the current signal, and generates a clock signal of a predetermined oscillation frequency and a triangular wave voltage synchronized with the clock signal;
A slope compensation current is generated by a current mirror circuit from a current obtained by converting the triangular wave voltage with a first resistor, and a conversion from the slope compensation current to a voltage and the feedback voltage of the voltage are divided by a second resistor. A slope generation circuit that generates a slope voltage by subtracting from the divided voltage.
A control circuit for a switching power supply device, comprising: The oscillator circuit is:
A first transistor that receives the voltage signal at a base;
A first current source for supplying a current flowing through the first transistor;
A second transistor receiving the emitter voltage of the first transistor at a base;
A third transistor for determining an upper limit of the emitter voltage of the second transistor;
A third resistor through which the current signal flows when the emitter voltage of the second transistor is applied;
A first current mirror circuit that outputs the charging current copied from the current signal according to a mirror ratio;
A comparator that generates and outputs the clock signal according to a comparison result between a charging voltage of the capacitor that becomes the triangular wave voltage and a threshold voltage;
A switch that is turned on based on the clock signal to discharge the capacitor;
The control circuit of the switching power supply device according to claim 1, comprising: The first transistor is a first PNP transistor, the second transistor is a first NPN transistor, the third transistor is a second PNP transistor, and the first current is The mirror circuit is formed of a first PMOS transistor and a second PMOS transistor, and the switch is a first NMOS transistor,
The voltage signal is applied to a base of the first PNP transistor,
An input terminal of the first current source is connected to a power source, a source of the first PMOS transistor, and a source of the second PMOS transistor;
An output terminal of the first current source is connected to an emitter of the first PNP transistor, an emitter of the second PNP transistor, and a base of the first NPN transistor;
The collector of the first NPN transistor is connected to the drain of the first PMOS transistor, the gate of the first PMOS transistor, and the gate of the second PMOS transistor;
A voltage that determines the upper limit of the second emitter voltage of the first NPN transistor is applied to the base of the second PNP transistor, and the emitter of the first NPN transistor is one end of the third resistor. Connect with
The drain of the second PMOS transistor is connected to the positive side input terminal of the comparator, one end of the capacitor, the drain of the first NMOS transistor, and the input end of the slope generation circuit, and the negative side of the comparator. The threshold voltage is applied to the side input terminal,
The collectors of the first and second PNP transistors, the other end of the third resistor, the other end of the capacitor, and the source of the first NMOS transistor are connected to ground.
The control circuit for the switching power supply device according to claim 2. The slope generation circuit includes:
A fourth transistor receiving the triangular wave voltage at a base;
A second current source for supplying a current flowing through the fourth transistor;
A fifth transistor receiving the emitter voltage of the fourth transistor at a base;
The first resistor through which a current flows when an emitter voltage of the fifth transistor is applied;
A second current mirror circuit that outputs a current copied from the current according to a mirror ratio;
The second resistance to which the divided voltage is applied to one end and the slope voltage is output from the other end;
A third current mirror circuit that causes the slope compensation current obtained by further duplicating the duplicated current output from the second current mirror circuit to flow from the other end of the second resistor;
The control circuit for a switching power supply device according to claim 1, comprising: The fourth transistor is a third PNP transistor, the fifth transistor is a second NPN transistor, and the second current mirror circuit includes a third PMOS transistor and a fourth PMOS transistor. The third current mirror circuit is formed of a second NMOS transistor and a third NMOS transistor, and
The triangular wave voltage is applied to the base of the third PNP transistor,
The input terminal of the second current source is connected to the power source, the source of the third PMOS transistor, and the source of the fourth PMOS transistor,
The output terminal of the second current source is connected to the emitter of the third PNP transistor and the base of the second NPN transistor,
The collector of the second NPN transistor is connected to the drain of the third PMOS transistor, the gate of the third PMOS transistor, and the gate of the fourth PMOS transistor;
An emitter of the second NPN transistor is connected to one end of the first resistor;
The drain of the fourth PMOS transistor is connected to the drain of the third NMOS transistor, the gate of the second NMOS transistor, and the gate of the third NMOS transistor,
The divided voltage is applied to one end of the second resistor, the drain of the second NMOS transistor is connected to the other end of the second resistor,
The collector of the third PNP transistor, the other end of the first resistor, the source of the second NMOS transistor, and the source of the third NMOS transistor are connected to ground.
The control circuit for the switching power supply according to claim 4. In the slope generation circuit that compensates the slope of the switching power supply of the current mode control that feeds back the inductor current of the transformer to achieve a constant voltage,
A capacitor is charged with a charging current proportional to a current signal generated from a voltage signal corresponding to a feedback voltage fed back from the secondary side output of the transformer, and a predetermined oscillation frequency generated by charging the capacitor A slope compensation original current generation circuit that receives a triangular wave voltage synchronized with the clock signal of the current and generates a slope compensation original current by a current mirror circuit from a current obtained by converting the triangular wave voltage using a first resistor;
The slope compensation original current is copied by a current mirror circuit different from the current mirror circuit to generate a slope compensation current, and the second resistor converts the slope compensation current into a voltage and the feedback voltage of the voltage is A voltage subtracting circuit that generates a slope voltage by performing subtraction from the divided divided voltage;
A slope generation circuit comprising:

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