CN104101764A - Novel inductor current detection circuit applied to DC-DC converter - Google Patents
Novel inductor current detection circuit applied to DC-DC converter Download PDFInfo
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Abstract
The invention provides a novel inductor current detection circuit applied to a DC-DC converter. The detection circuit can be respectively used for detecting the current of a PMOS power tube and an NMOS power tube, and is suitable for different topological structures of the DC-DC converter. The detection circuit comprising a power tube current detection module which is used for sampling the current on a power tube, and carrying out proportional distribution to current detection output ends, a negative feedback loop with an improved common gate amplifier, and a bias current compensation branch. The negative feedback loop is used for increasing loop gain and can accurately carry out voltage clamping to improve the output current detection accuracy. The bias current compensation branch is used for eliminating an error introduced by bias current under the condition of low inductor current to further improve the output current detection accuracy under a light load. According to the invention, the circuit does not use an operational amplifier, so thus the structure is simpler compared with a traditional on-chip current detection circuit; the improved common gate amplifier is used, which can provide gain for the negative feedback loop, ensures the current detection accuracy, and can reduce the delay of the detected current; and the bias current compensation branch is used to improve the detection accuracy.
Description
Technical field
The present invention relates to the technical field of inductive current detection circuit, refer in particular to a kind of novel inductor current detection circuit of the DC-DC of being applied to converter.
Background technology
In current mode DC-DC convertor, inductive current detection circuit can be used for detecting the electric current of inductance or power MOS pipe, and feeds back in system loop and realized closed-loop control, indispensable core circuit from become current mode DC-DC convertor.
Traditional electric current detecting method has series connected resistance, filter network method and image method.Wherein, series connected resistance detects its pressure drop by the resistance of the little resistance of connecting in power stage current path, and then obtains the size of inductive current or power tube current.But to be power consumption large and efficiency is low for the drawback of this method, more obvious while being especially applied in the low portable set of output voltage.
Filter network method adopts the RC low-pass network that is parallel to inductance two ends to detect inductive drop, and calculates flow through electric current by the ESR of inductance; But this technology is owing to needing the time constant of exact matching inductance and RC low-pass network, therefore inapplicable in the situation that of the unknown of inductance specification, thereby there is limitation in its finished product circuit in application.
The detector tube that image method utilization and power tube match carrys out the electric current of equal proportion mirror image power tube, and the main advantage of this method is to be easy to Embedded and power consumption is little, and the traditional on-chip inductor current detection circuit based on image method as shown in Figure 5.Wherein, power tube is M1 and M3, and M2 is the detector tube mating with M1.In order to reduce power consumption, the length breadth ratio of M2 is at least the per mille of M1, and because two pipe gate source voltages equate, and the clamping action of amplifier makes V
aand V
bequate, so image current I
scan be comparatively accurately and inductive current I
lproportional.Ignoring bias current I
bin the situation of impact, can obtain and I at Ms place
ssubstantially equal detection electric current I
sen.
The shortcoming that above-mentioned traditional on-chip inductor electric current detecting method exists is: 1) need to design high performance amplifier for clamper V
aand V
bthereby, strengthened design difficulty; 2) the domain mismatch error of M2 and M1 is larger; 3) under underloading or discontinuous conduction mode, I
sento be down to lower value, its precision is easily subject to bias current I
bimpact.
Summary of the invention
The object of the invention is to reduce traditional electrical inducing current detection method in circuit design and the complexity realizing, improve the accuracy of detection of inductive current, reduce the latency issue of inductive current detection circuit simultaneously.The invention provides the novel inductor current detection circuit that is applied to DC-DC converter of a kind of high precision, low-power consumption, utilize the detector tube mating with MOS power tube to detect inductive current, and proposition adopts modified to be total to grid type amplifier and negative feedback loop forms good clamping circuit, for replacing the operational amplifier of traditional inductive current detection circuit, improve accuracy of detection and reduced and detect time delay; Meanwhile, adopt bias current compensation branch road, in the situation that inductive current is extremely low, further improved current detection accuracy.
For achieving the above object, technical scheme provided by the present invention is: a kind of novel inductor current detection circuit that is applied to DC-DC converter, can be respectively used to detect the electric current of PMOS power tube and NMOS power tube, be applicable to the different topology structure of DC-DC converter, comprise:
Power tube current detection module, for the electric current on sampled power pipe, and pro rata distributes to current detecting output terminal;
With the modified negative feedback loop of grid level amplifier altogether, for increasing loop gain, and can accurately carry out voltage clamping, thereby improve the detection current precision of output;
Bias current compensation branch road, for eliminating the error of introducing at low inductive current situation below-center offset electric current, further improves the detection current precision of exporting under underloading.
Described power tube current detection module is is mainly connected and composed by the first field effect transistor, the second field effect transistor, the 3rd field effect transistor, the 7th field effect transistor; Described negative feedback loop is is mainly connected and composed by the 4th field effect transistor, the 5th field effect transistor, the 6th field effect transistor, and described the 4th field effect transistor and the 5th field effect transistor connect and compose modified grid level amplifier altogether; Described bias current compensation branch road is is mainly connected and composed by the 8th field effect transistor and the 9th field effect transistor; Wherein, the corresponding field effect type of each field effect type while detecting PMOS power tube current during with detection NMOS power tube current is contrary.
The source electrode of described the first field effect transistor is connected with input voltage, the grounded-grid of the first field effect transistor, and the drain electrode of the first field effect transistor is connected with the source electrode of the 7th field effect transistor and the source electrode of the 3rd field effect transistor respectively; The drain electrode of the 7th field effect transistor is connected with the drain electrode of the tenth field effect transistor of peripheral circuit, and the grid of the 7th field effect transistor is connected with the grid of the tenth field effect transistor, and access power pipe drives signal; The source electrode of the second field effect transistor is connected with input voltage, the equal ground connection of grid of the grid of the second field effect transistor and the 3rd field effect transistor; The 4th field effect transistor is connected with the grid of the 5th field effect transistor, and is connected in the drain electrode of the 4th field effect transistor; The substrate of the 4th field effect transistor is connected with the source electrode of the 5th field effect transistor, and the source electrode of the 5th field effect transistor is connected with the drain electrode of the 3rd field effect transistor; The source electrode of the 4th field effect transistor is connected with the substrate of the 5th field effect transistor, drain electrode, the drain electrode of the 8th field effect transistor and the source electrode of the 6th field effect transistor of the second field effect transistor respectively, and the drain electrode of the 4th drain electrode of field effect transistor and the 11 field effect transistor of peripheral circuit is connected; The grid of the 6th field effect transistor is connected with the drain electrode of the 5th field effect transistor, and the drain electrode of the 6th drain electrode of field effect transistor and the 12 field effect transistor of peripheral circuit is connected; The grid of the 8th field effect transistor is connected with the grid of the 11 field effect transistor of bias voltage and peripheral circuit, the 13 field effect transistor, the 18 field effect transistor respectively, and the source electrode of the 8th field effect transistor is connected with the drain electrode of the 9th field effect transistor; The grid of the 9th field effect transistor is connected with the grid of the 14 field effect transistor of peripheral circuit, the 15 field effect transistor, the 16 field effect transistor respectively, the source ground of the 9th field effect transistor.
The drain electrode of described the 7th field effect transistor is connected with the drain electrode of the tenth field effect transistor of peripheral circuit, and the grid of the 7th field effect transistor is connected with the grid of the tenth field effect transistor, the grid control signal of access power pipe; The drain electrode of the first field effect transistor is connected with the source electrode of the 7th field effect transistor and the source electrode of the 3rd field effect transistor respectively, the source ground of the first field effect transistor; The drain electrode of the 3rd field effect transistor is connected with the source electrode of the 5th field effect transistor; The drain electrode of the second field effect transistor is connected with the source electrode of the 4th field effect transistor, the source ground of the second field effect transistor; The grid of the first field effect transistor, the second field effect transistor and the 3rd field effect transistor is all connected with supply voltage; The 4th field effect transistor is connected with the grid of the 5th field effect transistor, and is connected in the drain electrode of the 4th field effect transistor; The substrate of the 4th field effect transistor is connected with the source electrode of the 5th field effect transistor, and the source electrode of the 5th field effect transistor is connected with the drain electrode of the 3rd field effect transistor; The source electrode of the 4th field effect transistor is connected with the substrate of the 5th field effect transistor, drain electrode, the drain electrode of the 9th field effect transistor and the source electrode of the 6th field effect transistor of the second field effect transistor respectively, and the drain electrode of the 4th drain electrode of field effect transistor and the 16 field effect transistor of peripheral circuit is connected; The grid of the 6th field effect transistor is connected with the drain electrode of the 5th field effect transistor, and the drain electrode of the 6th drain electrode of field effect transistor and the 17 field effect transistor of peripheral circuit is connected; The grid of the 9th field effect transistor is connected with the 16 field effect transistor of bias voltage and peripheral circuit and the grid of the 15 field effect transistor respectively, and the drain electrode of the 8th field effect transistor is connected with the source electrode of the 9th field effect transistor; The grid of the 8th field effect transistor is connected with the grid of the 14 field effect transistor of peripheral circuit, the 11 field effect transistor, the 13 field effect transistor respectively, and the source electrode of the 8th field effect transistor is connected with supply voltage.
Compared with prior art, tool has the following advantages and beneficial effect in the present invention:
1, novel inductor current detection circuit of the present invention does not adopt amplifier, therefore compares current detection circuit on traditional sheet, and its structure is more simple;
2, novel inductor current detection circuit of the present invention adopts modified cathode-input amplifier, both can be negative feedback loop the accuracy of detection that gains and ensure electric current is provided, and can reduce again the time delay that detects electric current;
3, novel inductor current detection circuit of the present invention adopts bias current compensation branch road, has reduced underloading or the impact of discontinuous conduction mode below-center offset electric current on output detections electric current, further improves accuracy of detection.
Brief description of the drawings
Fig. 1 is the circuit theory diagrams of novel inductor current detection circuit described in embodiment 1.
Fig. 2 is that novel inductor current detection circuit described in embodiment 1 is applied to the inductive current that detects in Buck type DC-DC converter and the circuit theory diagrams of PMOS power tube current thereof.
Fig. 3 is the circuit theory diagrams of novel inductor current detection circuit described in embodiment 2.
Fig. 4 is that novel inductor current detection circuit described in embodiment 2 is applied to the inductive current that detects in Boost type DC-DC converter and the circuit theory diagrams of NMOS power tube current thereof.
Fig. 5 is traditional on-chip inductor current detection circuit schematic diagram.
Embodiment
Below in conjunction with specific embodiment, the invention will be further described.
Embodiment 1
As shown in Figure 1, the novel inductor current detection circuit that is applied to DC-DC converter described in the present embodiment, for detection of the electric current of PMOS power tube, comprising:
Power tube current detection module, for the electric current on sampled power pipe, and pro rata distributes to current detecting output terminal;
With the modified negative feedback loop of grid level amplifier altogether, for increasing loop gain, and can accurately carry out voltage clamping, thereby improve the detection current precision of output;
Bias current compensation branch road, for eliminating the error of introducing at low inductive current situation below-center offset electric current, further improves the detection current precision of exporting under underloading.
Described power tube current detection module is is mainly connected and composed by the first field effect transistor M1, the second field effect transistor M2, the 3rd field effect transistor M3, the 7th field effect transistor Ms; Described negative feedback loop is is mainly connected and composed by the 4th field effect transistor M4, the 5th field effect transistor M5, the 6th field effect transistor M6, and described the 4th field effect transistor M4 and the 5th field effect transistor M5 connect and compose modified grid level amplifier altogether; Described bias current compensation branch road is is mainly connected and composed by the 8th field effect transistor Mc1 and the 9th field effect transistor Mc2.
The source electrode of described the first field effect transistor M1 is connected with input voltage vin, the grounded-grid of the first field effect transistor M1, and the drain electrode of the first field effect transistor M1 is connected with the source electrode of the 7th field effect transistor Ms and the source electrode of the 3rd field effect transistor M3 respectively; The drain electrode of the 7th field effect transistor Ms is connected with the drain electrode of the tenth field effect transistor M17 of peripheral circuit, and the grid of the 7th field effect transistor Ms is connected with the grid of the tenth field effect transistor M17, and access power pipe drives signal; The source electrode of the second field effect transistor M2 is connected with input voltage vin, the equal ground connection of grid of the grid of the second field effect transistor M2 and the 3rd field effect transistor M3; The 4th field effect transistor M4 is connected with the grid of the 5th field effect transistor M5, and is connected in the drain electrode of the 4th field effect transistor M4; The substrate of the 4th field effect transistor M4 is connected with the source electrode of the 5th field effect transistor M5, and the source electrode of the 5th field effect transistor M5 is connected with the drain electrode of the 3rd field effect transistor M3; The source electrode of the 4th field effect transistor M4 is connected with the substrate of the 5th field effect transistor M5, drain electrode, the drain electrode of the 8th field effect transistor Mc1 and the source electrode of the 6th field effect transistor M6 of the second field effect transistor M2 respectively, and the drain electrode of the 4th drain electrode of field effect transistor M4 and the 11 field effect transistor M11 of peripheral circuit is connected; The grid of the 6th field effect transistor M6 is connected with the drain electrode of the 5th field effect transistor M5, and the drain electrode of the 6th drain electrode of field effect transistor M6 and the 12 field effect transistor M7 of peripheral circuit is connected; The grid of the 8th field effect transistor Mc1 is connected with the 11 field effect transistor M11 of bias voltage and peripheral circuit, the grid of the 13 field effect transistor M12, the 18 field effect transistor M16 respectively, and the source electrode of the 8th field effect transistor Mc1 is connected with the drain electrode of the 9th field effect transistor Mc2; The grid of the 9th field effect transistor Mc2 is connected with the 14 field effect transistor M15 of peripheral circuit, the grid of the 15 field effect transistor M14, the 16 field effect transistor M13 respectively, the source ground of the 9th field effect transistor Mc2.
In Fig. 1, the tenth field effect transistor M17 is the P type power switch pipe in DC-DC converter topologies, for transmitting inductive current I
l.Because the length breadth ratio of the first field effect transistor M1 is much larger than the 7th field effect transistor Ms, so the pressure drop on the first field effect transistor M1 is very little, the current potential that E is ordered extremely approaches input voltage vin, thereby has guaranteed the accurately electric current on mirror image the tenth field effect transistor M17 of the 7th field effect transistor Ms.The length breadth ratio of setting both is (W/L)
m17: (W/L)
ms=K
1: the electric current flowing through on 1, the seven field effect transistor Ms and the tenth field effect transistor M17 is respectively I
1and I
p, I
p: I
1=K
1: 1.
The substrate difference cross connection of the 5th field effect transistor M5 and the 4th field effect transistor M4 is in A, B 2 points, form modified cathode-input amplifier, its effect is to increase loop gain, makes the accurately current potential of clamper A, B of negative feedback loop that the 4th field effect transistor M4-Mp6 forms at 2.In the time that the output current Is of the current detection circuit on the 6th field effect transistor M6 reduces, A point potential rise, because the electric current on the 4th field effect transistor M4 equals bias current I
bso the grid voltage of the 4th field effect transistor M4 increases; Meanwhile, because the electric current on the 5th field effect transistor M5 also equals I
b, B point current potential also increases, and therefore the variation tendency of the current potential of 2 of A, B under negative feedback loop control is identical, and size also equates.The 11 field effect transistor M11, the 13 field effect transistor M12, the 16 field effect transistor M13, the 15 field effect transistor M14, the 14 field effect transistor M15, the 18 field effect transistor M16 form low voltage cascade current mirror, wherein, the 14 field effect transistor M15 and the 18 field effect transistor M16 produce bias current I
b, the 11 field effect transistor M11, the 13 field effect transistor M12, the 16 field effect transistor M13 and the 15 field effect transistor M14 are used for reducing channel modulation effect and accurate mirror image bias current I
b, and the output impedance that improves modified cathode-input amplifier, thus guarantee the current potential of 2 of clamper A accurately, B.In sum, can obtain:
I
2R
ds2＝I
bR
ds3+I
3R
ds1 (1)
Wherein, resistance R
ds1-R
ds3be respectively the conducting resistance of the first field effect transistor M1, the second field effect transistor M2, the 3rd field effect transistor M3, electric current I
2and electric current I
3be respectively the electric current that flows through the second field effect transistor M2 and the first field effect transistor M1.Because the first field effect transistor M1, the second field effect transistor M2, the 3rd field effect transistor M3 are all offset to dark linear zone, and work in the metal-oxide-semiconductor of dark linear zone, the expression formula of its resistance is:
The length breadth ratio that the first field effect transistor M1, the second field effect transistor M2, the 3rd field effect transistor M3 are set is (W/L)
1: (W/L)
2: (W/L)
3=K
2: 1:1, can obtain R
ds1: R
ds2: R
ds3=1:K
2: K
2.Therefore, by I
2=I
c+ I
b+ I
sand I
3=I
1+ I
bsubstitution formula (2), can obtain:
(I
c+I
s)K
2＝I
1+I
b (3)
When DC-DC converter is during in underloading duty, due to I
sless, I
bshunting to I
sthe error causing will increase.In order further to reduce this error, in the present invention, design bias current compensation branch road, its offset current I
csize be I
b/ K
2.Therefore, by I
c=I
b/ K
2substitution formula (3), can abbreviation be:
I
1＝K
2I
s (4)
Due to I
1+ I
p=I
lso the final relational expression of the output current of inductive current detection circuit and inductive current is:
From formula (5), I
lwith I
sbe good linear relationship, its ratio value is by K
1and K
2size determine.Finally, the 19 field effect transistor M8 and the 20 field effect transistor M10, the 12 field effect transistor M7 and the 17 field effect transistor M9 composition current-mirror structure, and by electric current I
smirror image output, the electric current I on the 19 field effect transistor M8
senfor the detection electric current of final output.In the time that the tenth field effect transistor M17 turn-offs, inductive current detection circuit of the present invention not exclusively turn-offs, still have the Weak current approaching with bias current to flow through, therefore, reduced the time delay of the tenth field effect transistor M17 in the time that next cycle is opened in inductive current detection circuit.
As shown in Figure 2, for the novel inductor current detection circuit described in the present embodiment is for detection of inductive current and PMOS power tube current thereof in Buck type DC-DC converter, wherein, the grid of the 7th field effect transistor Ms is connected with the grid of the tenth field effect transistor M17 in Buck type DC-DC converter, the drain electrode of the 7th field effect transistor Ms is connected with the drain electrode of the tenth field effect transistor M17 in Buck type DC-DC converter, and the source electrode of the first field effect transistor M1 is connected with the input voltage in Buck type DC-DC converter.
Embodiment 2
As shown in Figure 3, the novel inductor current detection circuit that is applied to DC-DC converter described in the present embodiment is for detection of the electric current of NMOS power tube as different from Example 1, wherein, the drain electrode of the 7th field effect transistor Ms is connected with the drain electrode of the tenth field effect transistor M17 of peripheral circuit, the grid of the 7th field effect transistor Ms is connected with the grid of the tenth field effect transistor M17, the grid control signal of access power pipe; The drain electrode of the first field effect transistor M1 is connected with the source electrode of the 7th field effect transistor Ms and the source electrode of the 3rd field effect transistor M3 respectively, the source ground of the first field effect transistor M1; The drain electrode of the 3rd field effect transistor M3 is connected with the source electrode of the 5th field effect transistor M5; The drain electrode of the second field effect transistor M2 is connected with the source electrode of the 4th field effect transistor M4, the source ground of the second field effect transistor M2; The grid of the first field effect transistor M1, the second field effect transistor M2 and the 3rd field effect transistor M3 is all connected with supply voltage; The 4th field effect transistor M4 is connected with the grid of the 5th field effect transistor M5, and is connected in the drain electrode of the 4th field effect transistor M4; The substrate of the 4th field effect transistor M4 is connected with the source electrode of the 5th field effect transistor M5, and the source electrode of the 5th field effect transistor M5 is connected with the drain electrode of the 3rd field effect transistor M3; The source electrode of the 4th field effect transistor M4 is connected with the substrate of the 5th field effect transistor M5, drain electrode, the drain electrode of the 9th field effect transistor Mc2 and the source electrode of the 6th field effect transistor M6 of the second field effect transistor M2 respectively, and the drain electrode of the 4th drain electrode of field effect transistor M4 and the 16 field effect transistor M13 of peripheral circuit is connected; The grid of the 6th field effect transistor M6 is connected with the drain electrode of the 5th field effect transistor M5, and the drain electrode of the 6th drain electrode of field effect transistor M6 and the 17 field effect transistor M9 of peripheral circuit is connected; The grid of the 9th field effect transistor Mc2 is connected with the 16 field effect transistor M13 of bias voltage and peripheral circuit and the grid of the 15 field effect transistor M14 respectively, and the drain electrode of the 8th field effect transistor Mc1 is connected with the source electrode of the 9th field effect transistor Mc2; The grid of the 8th field effect transistor Mc1 is connected with the 14 field effect transistor M15 of peripheral circuit, the grid of the 11 field effect transistor M11, the 13 field effect transistor M12 respectively, and the source electrode of the 8th field effect transistor Mc1 is connected with supply voltage.Its principle of work of novel inductor current detection circuit that Fig. 3 provides is identical with the circuit that calculation expression all provides with Fig. 1, therefore, the final relational expression of the output current of the inductive current detection circuit that Fig. 3 provides and inductive current is the formula (5) of embodiment 1 too; But in Fig. 3, the type of each metal-oxide-semiconductor is contrary with metal-oxide-semiconductor corresponding in Fig. 1, be for example total to grid level amplifier and power tube current detection module for modified wherein, in Fig. 1, formed by PMOS field effect transistor, in Fig. 3, formed by NMOS field effect transistor; And for bias current compensation branch road, in Fig. 1, formed by NMOS field effect transistor, in Fig. 3 by PMOS field effect transistor.
As shown in Figure 4, for the novel inductor current detection circuit described in the present embodiment is for detection of inductive current and NMOS power tube current thereof in Boost type DC-DC converter, wherein, the tenth field effect transistor M17 is the N-type power switch pipe in DC-DC converter topologies, the grid of the 7th field effect transistor Ms is connected with the grid of the tenth field effect transistor M17 in Boost type DC-DC converter, the drain electrode of the grid of the 7th field effect transistor Ms is connected with the drain electrode of the tenth field effect transistor M17 in Boost type DC-DC converter, the source ground of the first field effect transistor M1.
In addition, novel inductor current detection circuit of the present invention, can be applied in too Buck type DC-DC converter and the Boost type DC-DC converter of asynchronous rectification type, and Buck-boost type DC-DC converter, be applicable to the different topology structure of DC-DC converter.
The examples of implementation of the above are only the present invention's preferred embodiment, not limit practical range of the present invention with this, therefore the variation that all shapes according to the present invention, principle are done all should be encompassed in protection scope of the present invention.
Claims (4)
1. a novel inductor current detection circuit that is applied to DC-DC converter, is characterized in that, can be respectively used to detect the electric current of PMOS power tube and NMOS power tube, is applicable to the different topology structure of DC-DC converter, comprising:
Power tube current detection module, for the electric current on sampled power pipe, and pro rata distributes to current detecting output terminal;
With the modified negative feedback loop of grid level amplifier altogether, for increasing loop gain, and can accurately carry out voltage clamping, thereby improve the detection current precision of output;
Bias current compensation branch road, for eliminating the error of introducing at low inductive current situation below-center offset electric current, further improves the detection current precision of exporting under underloading.
2. a kind of novel inductor current detection circuit that is applied to DC-DC converter according to claim 1, is characterized in that: described power tube current detection module is is mainly connected and composed by the first field effect transistor (M1), the second field effect transistor (M2), the 3rd field effect transistor (M3), the 7th field effect transistor (Ms); Described negative feedback loop is is mainly connected and composed by the 4th field effect transistor (M4), the 5th field effect transistor (M5), the 6th field effect transistor (M6), and described the 4th field effect transistor (M4) and the 5th field effect transistor (M5) connect and compose modified grid level amplifier altogether; Described bias current compensation branch road is is mainly connected and composed by the 8th field effect transistor (Mc1) and the 9th field effect transistor (Mc2); Wherein, the corresponding field effect type of each field effect type while detecting PMOS power tube current during with detection NMOS power tube current is contrary.
3. a kind of novel inductor current detection circuit that is applied to DC-DC converter according to claim 2, it is characterized in that: the source electrode of described the first field effect transistor (M1) is connected with input voltage (Vin), the grounded-grid of the first field effect transistor (M1), the drain electrode of the first field effect transistor (M1) is connected with the source electrode of the 7th field effect transistor (Ms) and the source electrode of the 3rd field effect transistor (M3) respectively; The drain electrode of the 7th field effect transistor (Ms) is connected with the drain electrode of the tenth field effect transistor (M17) of peripheral circuit, the grid of the 7th field effect transistor (Ms) is connected with the grid of the tenth field effect transistor (M17), and access power pipe drives signal; The source electrode of the second field effect transistor (M2) is connected with input voltage (Vin), the equal ground connection of grid of the grid of the second field effect transistor (M2) and the 3rd field effect transistor (M3); The 4th field effect transistor (M4) is connected with the grid of the 5th field effect transistor (M5), and is connected in the drain electrode of the 4th field effect transistor (M4); The substrate of the 4th field effect transistor (M4) is connected with the source electrode of the 5th field effect transistor (M5), and the source electrode of the 5th field effect transistor (M5) is connected with the drain electrode of the 3rd field effect transistor (M3); The source electrode of the 4th field effect transistor (M4) is connected with the substrate of the 5th field effect transistor (M5), drain electrode, the drain electrode of the 8th field effect transistor (Mc1) and the source electrode of the 6th field effect transistor (M6) of the second field effect transistor (M2) respectively, and the drain electrode of the 4th drain electrode of field effect transistor (M4) and the 11 field effect transistor (M11) of peripheral circuit is connected; The grid of the 6th field effect transistor (M6) is connected with the drain electrode of the 5th field effect transistor (M5), and the drain electrode of the 6th drain electrode of field effect transistor (M6) and the 12 field effect transistor (M7) of peripheral circuit is connected; The grid of the 8th field effect transistor (Mc1) is connected with the grid of the 11 field effect transistor (M11) of bias voltage and peripheral circuit, the 13 field effect transistor (M12), the 18 field effect transistor (M16) respectively, and the source electrode of the 8th field effect transistor (Mc1) is connected with the drain electrode of the 9th field effect transistor (Mc2); The grid of the 9th field effect transistor (Mc2) is connected with the grid of the 14 field effect transistor (M15) of peripheral circuit, the 15 field effect transistor (M14), the 16 field effect transistor (M13) respectively, the source ground of the 9th field effect transistor (Mc2).
4. a kind of novel inductor current detection circuit that is applied to DC-DC converter according to claim 2, it is characterized in that: the drain electrode of described the 7th field effect transistor (Ms) is connected with the drain electrode of the tenth field effect transistor (M17) of peripheral circuit, the grid of the 7th field effect transistor (Ms) is connected with the grid of the tenth field effect transistor (M17), the grid control signal of access power pipe; The drain electrode of the first field effect transistor (M1) is connected with the source electrode of the 7th field effect transistor (Ms) and the source electrode of the 3rd field effect transistor (M3) respectively, the source ground of the first field effect transistor (M1); The drain electrode of the 3rd field effect transistor (M3) is connected with the source electrode of the 5th field effect transistor (M5); The drain electrode of the second field effect transistor (M2) is connected with the source electrode of the 4th field effect transistor (M4), the source ground of the second field effect transistor (M2); The first field effect transistor (M1), the second field effect transistor (M2) and the grid of the 3rd field effect transistor (M3) are all connected with supply voltage; The 4th field effect transistor (M4) is connected with the grid of the 5th field effect transistor (M5), and is connected in the drain electrode of the 4th field effect transistor (M4); The substrate of the 4th field effect transistor (M4) is connected with the source electrode of the 5th field effect transistor (M5), and the source electrode of the 5th field effect transistor (M5) is connected with the drain electrode of the 3rd field effect transistor (M3); The source electrode of the 4th field effect transistor (M4) is connected with the substrate of the 5th field effect transistor (M5), drain electrode, the drain electrode of the 9th field effect transistor (Mc2) and the source electrode of the 6th field effect transistor (M6) of the second field effect transistor (M2) respectively, and the drain electrode of the 4th drain electrode of field effect transistor (M4) and the 16 field effect transistor (M13) of peripheral circuit is connected; The grid of the 6th field effect transistor (M6) is connected with the drain electrode of the 5th field effect transistor (M5), and the drain electrode of the 6th drain electrode of field effect transistor (M6) and the 17 field effect transistor (M9) of peripheral circuit is connected; The grid of the 9th field effect transistor (Mc2) is connected with the 16 field effect transistor (M13) of bias voltage and peripheral circuit and the grid of the 15 field effect transistor (M14) respectively, and the drain electrode of the 8th field effect transistor (Mc1) is connected with the source electrode of the 9th field effect transistor (Mc2); The grid of the 8th field effect transistor (Mc1) is connected with the grid of the 14 field effect transistor (M15) of peripheral circuit, the 11 field effect transistor (M11), the 13 field effect transistor (M12) respectively, and the source electrode of the 8th field effect transistor (Mc1) is connected with supply voltage.
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|---|---|---|---|
| CN201410286406.0A CN104101764B (en) | 2014-06-24 | 2014-06-24 | Novel inductor current detection circuit applied to DC-DC converter |
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|---|---|---|---|
| CN201410286406.0A CN104101764B (en) | 2014-06-24 | 2014-06-24 | Novel inductor current detection circuit applied to DC-DC converter |
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| CN105092937A (en) * | 2015-09-02 | 2015-11-25 | 西安电子科技大学 | Full-cycle current detection circuit |
| CN105785101A (en) * | 2016-03-04 | 2016-07-20 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | Efficient inductor current detection circuit |
| CN106771486A (en) * | 2016-12-20 | 2017-05-31 | 电子科技大学 | A kind of current sampling circuit |
| CN108957102A (en) * | 2018-08-28 | 2018-12-07 | 长沙理工大学 | A kind of current detection circuit of no amplifier |
| CN109073687A (en) * | 2015-07-08 | 2018-12-21 | 高通股份有限公司 | For by derived from the drain-source voltage of power gating device voltage apply compensated gain the device and method that measure load current |
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| US6441597B1 (en) * | 2001-10-31 | 2002-08-27 | Semtech Corporation | Method and apparatus for sensing output inductor current in a DC-to-DC power converter |
| CN201159747Y (en) * | 2008-02-03 | 2008-12-03 | 深圳艾科创新微电子有限公司 | Inductor current sensing circuit for switch power source |
| CN201805600U (en) * | 2010-09-30 | 2011-04-20 | 杭州电子科技大学 | Primary-side constant-current control device of LED driver |
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| CN109073687A (en) * | 2015-07-08 | 2018-12-21 | 高通股份有限公司 | For by derived from the drain-source voltage of power gating device voltage apply compensated gain the device and method that measure load current |
| CN105092937A (en) * | 2015-09-02 | 2015-11-25 | 西安电子科技大学 | Full-cycle current detection circuit |
| CN105092937B (en) * | 2015-09-02 | 2018-03-06 | 西安电子科技大学 | A kind of complete period current detection circuit |
| CN105785101A (en) * | 2016-03-04 | 2016-07-20 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | Efficient inductor current detection circuit |
| CN105785101B (en) * | 2016-03-04 | 2018-09-07 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | A kind of efficient inductive current detection circuit |
| CN106771486A (en) * | 2016-12-20 | 2017-05-31 | 电子科技大学 | A kind of current sampling circuit |
| CN106771486B (en) * | 2016-12-20 | 2019-04-12 | 电子科技大学 | A kind of current sampling circuit |
| CN108957102A (en) * | 2018-08-28 | 2018-12-07 | 长沙理工大学 | A kind of current detection circuit of no amplifier |
| CN108957102B (en) * | 2018-08-28 | 2024-03-08 | 长沙理工大学 | Current detection circuit without operational amplifier |
| CN114167125A (en) * | 2021-07-29 | 2022-03-11 | 沈阳工业大学 | Current detection circuit |
| CN114167125B (en) * | 2021-07-29 | 2023-12-12 | 沈阳工业大学 | Current detection circuit |
| CN117310253A (en) * | 2023-09-20 | 2023-12-29 | 上海帝迪集成电路设计有限公司 | Wide-range high-precision current detection circuit and detection method thereof |
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