CN106787652A - A kind of dynamic suitable for buck converter output DC maladjustment eliminates circuit - Google Patents
A kind of dynamic suitable for buck converter output DC maladjustment eliminates circuit Download PDFInfo
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- CN106787652A CN106787652A CN201710070538.3A CN201710070538A CN106787652A CN 106787652 A CN106787652 A CN 106787652A CN 201710070538 A CN201710070538 A CN 201710070538A CN 106787652 A CN106787652 A CN 106787652A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/14—Arrangements for reducing ripples from dc input or output
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
A kind of dynamic suitable for buck converter output DC maladjustment eliminates circuit, belongs to electronic circuit technology field.Of the invention by adding duty cycle information in line wave generation circuit including line wave generation circuit and ripple supercircuit, directly sample upper power tube S1With lower power tube S2Voltage at connecting node SW is superimposed upon feedback voltage V to simulate to produce with the ripple of inductive current same-phaseFBAbove so that feedback voltage VFBWith preset reference voltage VREFIt is equal, to control the normal upset of pulse width modulated comparator PWM, strengthening system stability, avoid by the too small resonance problems for causing output voltage delayed phase and producing of equivalent series resistance of output capacitance, increase converter output voltage precision, contradiction of the valley detection pattern of traditional ripple control between the stability of a system and accuracy is overcome, be able to can accomplish dynamically to eliminate the DC maladjustment amount of output voltage in the case where different application condition is different input voltages and output voltage.
Description
Technical field
The invention belongs to electronic circuit technology field, and in particular to be applied to constant-on-time to one kind and be based on ripple
The dynamic of the buck DC-DC converter output DC maladjustment of control eliminates circuit.
Background technology
With the extensive use of portable electronic device, market constantly rises to the demand of power management integrated circuit, its
Middle voltage-dropping type (Buck) DC-DC converter is even more and is widely used in the fields such as communication, computer, industrial automation.Traditional
Buck DC-DC converter has three kinds of control models, respectively current-mode, voltage-mode and sluggish control.Based on the constant of ripple
Opening time control program (Ripple-based Constant On-time Control) belongs to one kind of sluggish mould control,
And be widely used the advantages of because its control is simple, without external compensation, excellent load regulation and efficiency.
For traditional buck converter, its systematic function exists certain compromise：Loop is superimposed upon PWM comparator forward ends
Too small loop stability reduction, the PWM comparator output jitters of being likely to result in of ripple quantity the problems such as cause false triggering.Ripple quantity mistake
It is big then can cause be located at 1/2nd switching frequencies at system q it is too low so that system response time is slack-off；And opened by constant
Open that the DC maladjustment amount that time intrinsic valley detection pattern introduces is excessive, this is on the premise of buck convertor output low pressure
Very big influence can be caused to system accuracy.
The content of the invention
Part, of the invention to be directed to constant-on-time and the decompression transformation based on ripple control in view of the shortcomings of the prior art
Device detects mould under the application conditions of different input voltage vins and output voltage Vout by the intrinsic valley of constant-on-time
The output imbalance that formula is introduced, there is provided a kind of dynamic eliminates circuit, it is ensured that output is dynamically eliminated in the case of different duty straight
It is lost in and adjusts.
The technical scheme is that：
A kind of dynamic suitable for buck converter output DC maladjustment eliminates circuit, including line wave generation circuit and ripple
Supercircuit,
The ripple supercircuit includes a trsanscondutance amplifier Gm, and the positive input of trsanscondutance amplifier Gm is used as the line
The first input end of ripple supercircuit, its negative input as the ripple supercircuit the second input, the ripple
Power tube opens lower power tube shut-off on the output end output pulse signal control buck converter of supercircuit；
Characterized in that, the line wave generation circuit includes first resistor R1, second resistance R2,3rd resistor R3, the 4th
Resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the 9th resistance R9, the first electric capacity C1, second
Electric capacity C2, the 3rd electric capacity C3, the 4th electric capacity C4, the 5th electric capacity C5, the 6th electric capacity C6, the first NMOS tube MN1, the second NMOS tube
MN2, the 3rd NMOS tube MN3, the first PMOS MP1, the second PMOS MP2 and the 3rd buffer BUF,
One end of first resistor R1 is input into buck converter lower power tube as the input of the line wave generation circuit
Voltage at node SW, its other end after the first electric capacity C1 by being grounded；
Second resistance R2 and 3rd resistor R3 connects, its series connection point output triangle wave voltage VF1And connect the ripple superposition
The first input end of circuit, the tie point of another termination first resistor R1 and the first electric capacity C1 of second resistance R2,3rd resistor
The other end ground connection of R3；
4th resistance R4 and the second electric capacity C2 connects, the other end connection second resistance R2 and the 3rd resistor of the 4th resistance R4
The series connection point of R3, the other end ground connection of the second electric capacity C2；
5th resistance R5 and the 3rd electric capacity C3 connects, and its series connection point connects the positive input of the 3rd buffer BUF, the 5th
The other end of resistance R5 connects the series connection point of the 4th resistance R4 and the second electric capacity C2, the other end ground connection of the 3rd electric capacity C3；
The negative input of the 3rd buffer BUF is connected the source electrode of the first NMOS tube MN1 and is followed by by the 6th resistance R6
Ground, the grid of the first NMOS tube MN1 of its output termination；
The source electrode of the first PMOS MP1 and the second PMOS MP2 is interconnected and connects supply voltage VCC, its gate interconnection simultaneously connects
Connect the drain electrode of the first PMOS MP1 and the first NMOS tube MN1；
The grid of the second NMOS tube MN2 connects to be believed with the control of signal inversion at buck converter lower power tube node SW
Number, its drain electrode connects the drain electrode of the second PMOS MP2 and the 3rd NMOS tube MN3, its source ground；
The grid of the 3rd NMOS tube MN3 connects to be believed with signal at buck converter lower power tube node SW with the control of phase
Number, its source electrode after the parallel-connection structure of the 5th electric capacity C5 and the 7th resistance R7 by being grounded；
8th resistance R8 and the 4th electric capacity C4 connects, the source electrode of the NMOS tube MN3 of another termination the 3rd of the 8th resistance R8, the
The other end ground connection of four electric capacity C4；
9th resistance R9 and the 6th electric capacity C6 connects, its series connection point output DC voltage VSW_DCAnd connect the ripple superposition
Second input of circuit, the series connection point of the resistance R8 of another termination the 8th and the 4th electric capacity C4 of the 9th resistance R9, the 6th electric capacity
The other end ground connection of C6.
Specifically, the ripple supercircuit also includes the first buffer BUF1, the second buffer BUF2, the tenth resistance
R10 and pulse width modulated comparator PWM,
The input input feedback voltage V of the first buffer BUF1FB, its output end by connected after the tenth resistance R10 across
Lead the output end of amplifier Gm and the positive input of pulse width modulated comparator PWM；
The input input reference voltage V of the second buffer BUF2REF, its output end connection pulse width modulated comparator PWM's
Negative input, the output end of pulse width modulated comparator PWM as the ripple supercircuit output end.
Beneficial effects of the present invention are：The present invention is different input voltage vins and output voltage in different application condition
Can accomplish dynamically to eliminate the DC maladjustment amount of output end voltage under Vout, dutycycle letter is added in line wave generation circuit
Breath so that the feedback voltage V proportional to output voltage VoutFBWith preset reference voltage VREFIt is equal, increase converter output electricity
Pressure Vout precision, overcomes contradiction of the valley detection pattern of traditional ripple control between the stability of a system and accuracy；This
Ripple supercircuit in the piece for using is invented, directly sample upper power tube S1With lower power tube S2Connecting node SW at voltage
To simulate to produce feedback voltage V is superimposed upon with the ripple of inductive current same-phaseFBAbove, controlling pulse width modulated comparator PWM
Normal upset, strengthening system stability, it is to avoid by the equivalent series resistance R of output capacitanceCoIt is too small to cause output voltage Vout
Delayed phase and the resonance problems that produce；5th electric capacity C5 filters the burr of square-wave signal on the 7th resistance R7 to cause that rear class is filtered
The average voltage that ripple is obtained is more accurate；Meanwhile, the present invention also retains traditional control of the constant on-time based on ripple
Control that mode has is simple, without external compensation, electromagnetic interference EMI it is functional, with preferable load regulation and
The advantages of light-load efficiency, optimize the systematic function of buck converter.
Brief description of the drawings
Fig. 1 is a kind of applicable voltage-dropping type variator loop control principle schematic diagram based on ripple control of the present invention.
Fig. 2 is the ripple that a kind of dynamic suitable for buck converter output DC maladjustment proposed by the present invention eliminates circuit
Produce circuit theory diagrams.
Fig. 3 is the ripple that a kind of dynamic suitable for buck converter output DC maladjustment proposed by the present invention eliminates circuit
Supercircuit and output DC maladjustment dynamically eliminate schematic diagram.
Fig. 4 dynamically eliminates schematic diagram for output DC maladjustment.
Specific embodiment
Below in conjunction with accompanying drawing, technical scheme is specifically described：
A kind of dynamic suitable for buck converter output DC maladjustment proposed by the present invention eliminates circuit, by tradition
DC filter (DC value extractor) in add duty cycle information, make it in different input voltage vins and output
Equal dynamic eliminates output DC offset voltage under the application conditions of voltage Vout, different dutycycles, so as to improve step-down become
The output accuracy of parallel operation；Ensure ripple quantity size simultaneously, do not influence the stability of a system.
It is as shown in Figure 1 a kind of voltage-dropping type variator principle schematic based on ripple control that the present invention is applicable, wherein
Circuit frame is by input voltage vin, inductance L, upper power tube S1, lower power tube S2, output capacitance Co and its equivalent series resistance
RCoConstituted with output loading Ro, wherein lower power tube S1And S2Node be SW, system output voltage is Vout.Output voltage
Vout produces feedback voltage V by feedback factor βFB, with reference voltage VREFInput pulse width modulator (PWM) together is compared
And eventually through logic module Logic control lower power tubes S1And S2Switch.Upper power tube S1Open lower power tube S2Shut-off
Time be Ton, be constant；Upper power tube S1The lower power tube S of shut-off2The time of unlatching is Toff, its marking signal for terminating
It is the output signal of pulse width modulated comparator PWM, the signal is in feedback voltage VFBLess than setting reference voltage value VREFWhen produce.
The ratio that Ton occupies whole switch periods (Ton+Toff) is dutycycle D.Due to feedback voltage VFBIn feeding pulsewidth modulation ratio
Compared with device PWM and reference voltage VREFNeed first to be superimposed the ripple voltage with the same frequency of inductive current with phase before comparing, therefore first resistor R1,
First electric capacity C1, second resistance R2 and 3rd resistor R3 are used to produce with inductive current with frequently with the triangle wave voltage V of phaseF1, with
DC quantity by DC filter and after adding duty cycle information is poor, that is, produce foregoing and feedback voltage VFBNeeded for superposition
Ripple voltage.
And ripple supercircuit in the piece that the present invention is used, directly sample upper power tube S1With lower power tube S2Connection section
Voltage at point SW is superimposed upon feedback voltage V to simulate to produce with the ripple of inductive current same-phaseFBAbove, controlling pulsewidth to adjust
The normal upset of comparator PWM processed, strengthening system stability, it is to avoid by the equivalent series resistance R of output capacitanceCoIt is too small cause it is defeated
Go out voltage VOUTDelayed phase and the resonance problems that produce；Duty cycle information is added simultaneously, to ensure the dynamic under different application
Output DC maladjustment is eliminated, increases converter output voltage precision.
Line wave generation circuit is as shown in Fig. 2 including first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance
R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the 9th resistance R9, the first electric capacity C1, the second electric capacity
C2, the 3rd electric capacity C3, the 4th electric capacity C4, the 5th electric capacity C5, the 6th electric capacity C6, the first NMOS tube MN1, the second NMOS tube MN2,
Three NMOS tube MN3, the first PMOS MP1, the second PMOS MP2 and the 3rd buffer BUF, one end of first resistor R1 is used as institute
The voltage at the input input buck converter lower power tube node SW of line wave generation circuit is stated, its other end passes through first
It is grounded after electric capacity C1；Second resistance R2 and 3rd resistor R3 connects, its series connection point output triangle wave voltage VF1And connect the line
The first input end of ripple supercircuit, the tie point of another termination first resistor R1 and the first electric capacity C1 of second resistance R2, the
The other end ground connection of three resistance R3；4th resistance R4 and the second electric capacity C2 connects, the electricity of other end connection second of the 4th resistance R4
Hinder the series connection point of R2 and 3rd resistor R3, the other end ground connection of the second electric capacity C2；5th resistance R5 and the 3rd electric capacity C3 connects, its
Series connection point connects the positive input of the 3rd buffer BUF, and the other end of the 5th resistance R5 connects the electricity of the 4th resistance R4 and second
Hold the series connection point of C2, the other end ground connection of the 3rd electric capacity C3；The negative input of the 3rd buffer BUF connects the first NMOS tube
The source electrode of MN1 and by after the 6th resistance R6 be grounded, its output termination the first NMOS tube MN1 grid；First PMOS MP1 and
The source electrode of the second PMOS MP2 is interconnected and connects supply voltage VCC, its gate interconnection simultaneously connect the first PMOS MP1 and first
The drain electrode of NMOS tube MN1；The grid of the second NMOS tube MN2 connects and signal inversion at buck converter lower power tube node SW
Control signal, its drain electrode connects the drain electrode of the second PMOS MP2 and the 3rd NMOS tube MN3, its source ground；3rd NMOS tube MN3
Grid connect control signal with signal at buck converter lower power tube node SW with phase, its source electrode passes through the 5th electric capacity C5
It is grounded with after the parallel-connection structure of the 7th resistance R7；8th resistance R8 and the 4th electric capacity C4 connects, another termination of the 8th resistance R8
The source electrode of the 3rd NMOS tube MN3, the other end ground connection of the 4th electric capacity C4；9th resistance R9 and the 6th electric capacity C6 connects, its series connection
Point output DC voltage VSW_DCAnd connect the second input of the ripple supercircuit, another termination the 8th of the 9th resistance R9
The series connection point of resistance R8 and the 4th electric capacity C4, the other end ground connection of the 6th electric capacity C6.
Ripple supercircuit as shown in figure 3, including trsanscondutance amplifier Gm, the first buffer BUF1, the second buffer BUF2,
The positive input of the tenth resistance R10 and pulse width modulated comparator PWM, trsanscondutance amplifier Gm is used as the ripple supercircuit
First input end, its negative input as the ripple supercircuit the second input, the ripple supercircuit it is defeated
Go out to hold output pulse signal to control power tube on buck converter to open lower power tube shut-off；The input of the first buffer BUF1
Input feedback voltage VFB, output end and pulsewidth modulation ratio of its output end by connection trsanscondutance amplifier Gm after the tenth resistance R10
Compared with the positive input of device PWM；The input input reference voltage V of the second buffer BUF2REF, its output end connection pulsewidth tune
The negative input of comparator PWM processed, the output end of pulse width modulated comparator PWM as the ripple supercircuit output
End.
Specific ripple fold be controlled by pulse width modulated comparator PWM output switching activities the course of work it is as follows：
As shown in Fig. 2 the input of line wave generation circuit is buck convertor lower power tube node SW voltages, first
Filtered as triangular wave by a RC network being made up of first resistor R1, the first electric capacity C1 and second resistance R2,3rd resistor R3
Signal, i.e. triangle wave voltage VF1, second resistance R2, the effect of 3rd resistor R3 are adjustment triangle wave voltage V hereinF1It is average
Value size is meeting the common-mode input range of rear class trsanscondutance amplifier Gm.For triangle wave voltage VF1, its ripple quantity size is：
Its average value size is：
Triangle wave voltage VF1Connection is made up of the 4th resistance R4, the second electric capacity C2 and the 5th resistance R5, the 3rd electric capacity C3
Its average value is obtained after two stage filter network, by a 3rd buffer BUF by the voltage clamping at the 6th resistance R6 two ends
In triangle wave voltage VF1Average.Therefore, it is by the electric current of the 6th resistance R6：
And the breadth length ratio of the current mirror of the first PMOS MP1 and the second PMOS MP2 compositions is 1:1, the 7th resistance R7's
Resistance is equal to the resistance of the 6th resistance R6, and the grid of the second NMOS tube MN2 and the 3rd NMOS tube MN3 connects and connect respectively and upper and lower power
With frequently with the control signal of phase at pipe node SW so that the 3rd NMOS tube MN3 conductings during Ton, the second NMOS tube MN2 shut-offs；
And the second NMOS tube MN2 conductings during Toff, the 3rd NMOS tube MN3 shut-offs.Thus, the pressure drop during Ton on the 7th resistance R7
It is triangle wave voltage VF1Average valueAnd the pressure drop during Toff on the 7th resistance R7 is 0.As shown in Fig. 2 dotted line frames,
The partial circuit is realized in triangle wave voltage VF1DC information in add duty cycle information, for rear class export DC maladjustment
Dynamic elimination.Therefore be a square-wave signal on the 7th resistance R7, its average value is：
Wherein D is dutycycle.Here the 5th electric capacity C5 act as filter the 7th resistance R7 on square-wave signal burr with
So that the average voltage that rear class filtering is obtained is more accurate, but it crosses conference and introduces big time constant, is unfavorable for square wave
Formed.Generally, the time constant of the 7th resistance R7 and the 5th electric capacity C5 should be less than 0.1 times of switch periods.
The square-wave signal at the 7th resistance R7 two ends is by the 8th resistance R8, the 4th electric capacity C4 and the 9th resistance R9, the 6th electricity
The current potential of its average value is obtained after the filter network of the large time constant for holding C6 compositions, i.e.,：
Above line wave generation circuit is obtained triangle wave voltage V againF1And DC voltage VSW_DCRear class mutual conductance is input to put
Big device produces ripple current I1, the DC voltage VSW_DCContaining duty cycle information, as shown in Figure 3.Make trsanscondutance amplifier etc.
Effect mutual conductance is Gm, VF1And VSW_DCIt is separately input to positive-negative input end, triangle wave voltage VF1Average value beSo that mutual conductance is put
The output current I of big device Gm1Can be obtained by the following formula：
Wherein,Here IrippleBe containing ripple information and
With inductive current with the electric current of phase, its DC component is zero frequently；Δ I is an information DC current containing dutycycle D, is used for
The dynamic elimination of output voltage imbalance.
As shown in figure 4, by the electric current I after trsanscondutance amplifier Gm1Required ripple electricity is produced after flowing through the tenth resistance R10
Press the feedback voltage V proportional with down-converter output voltage Vout sampled to the first buffer BUF1 inputsFBSuperposition,
As the positive input V of pulse width modulated comparator PWM1, i.e.,：
V1=VFB+R10·I1
=VFB+R10·(Iripple+ΔI)
And the negative input V of pulse width modulated comparator PWM2It is the reference voltage V by the second buffer BUF2REF。
I.e.：
V2=VREF
V1And V2Positive-negative input end respectively as pulse width modulated comparator PWM compares poor, and its difference is：
V1-V2=VFB+R10·(Iripple+ΔI)-VREF
=(VFB+R10·Iripple)-(VREF-R10·ΔI)
Another feedback voltage VFBThe ripple voltage of upper superposition is Vripple=R10·Iripple, its voltage peak-to-peak value is
Vripple(pp)；And reference voltage VREFTranslational movement be Δ V=R10Arrow mark in Δ I, such as Fig. 4.Due to constant-on-time
The intrinsic valley detection pattern of control mode, to cause that pulse width modulated comparator PWM overturns to produce and open upper power tube S1, close
The pulse signal of disconnected lower power tube S2 is, it is necessary to contain feedback voltage VFBThe V of information1Signal is down to and V in its valley2Voltage
Value is equal, as shown in Figure 4.Another ripple current I1Peak-to-peak value size be Iripple(pp), then V1V is touched in valley2When electric current I1's
Ripple quantity size isI.e.：
Eliminate the DC maladjustment on the output voltage Vout of output end output so that feedback voltage VFBWith reference voltage
VREFSize is identical, i.e. VFB=VREF.With reference to above-mentioned roll over condition formula, must have：
Due to
And
Calculated before substitution, above formula the right and left can be obtained and be respectively：
As can be seen that two formulas can be offset containing duty cycle information above, it is ensured that in different input voltage vins and output
Output voltage DC maladjustment can be dynamically eliminated under the application conditions of voltage Vout (i.e. different duty D) so that the present invention exists
It is applicable in wide scope.And to make above-mentioned two formula equal, i.e.,：
2R1·C1·fsw(R2+R3)=R1+R2+R3
For the Buck buck converters for determining frequency application (fsw is constant, such as 700kHz), second resistance R2 and the need to be only adjusted
The resistance size of three resistance R3, you can meet above-mentioned equation and set up.Meanwhile, by being above derived from VF1Ripple quantity size and the
The value of one resistance R1 and the first electric capacity C1 is inversely proportional, thus, can be by first resistor R1 and the first electric capacity C1 in design
Reasonable set be superimposed upon feedback voltage V to adjustFBThe size of ripple quantity, should make it be no less than 30mV under normal circumstances above,
So as to ensure the stability of a system.
The present invention can accomplish dynamically to disappear in the case where different application condition is different input voltage vins and output voltage Vout
Except the DC maladjustment amount of output end voltage so that the feedback voltage V proportional to output VoutFBWith preset reference voltage VREF
It is equal, overcome contradiction of the valley detection pattern of traditional ripple control between the stability of a system and accuracy.Meanwhile, this hair
It is bright to also retains traditional constant on-time control mode (Ripple-based Constant On-time based on ripple
Control the control that) has is simple, without external compensation, EMI it is functional, with preferable load regulation and underloading
The advantages of efficiency, the systematic function of Buck converters is optimized well.
One of ordinary skill in the art will be appreciated that embodiment described here is to aid in reader and understands this hair
Bright principle, it should be understood that protection scope of the present invention is not limited to such especially statement and embodiment.This area
Those of ordinary skill can according to these technical inspirations disclosed by the invention make it is various do not depart from essence of the invention other are each
Plant specific deformation and combine, these deformations and combination are still within the scope of the present invention.
Claims (2)
1. a kind of dynamic suitable for buck converter output DC maladjustment eliminates circuit, including line wave generation circuit and ripple are folded
Power-up road,
The ripple supercircuit includes a trsanscondutance amplifier (Gm), and the positive input of trsanscondutance amplifier (Gm) is used as the line
The first input end of ripple supercircuit, its negative input as the ripple supercircuit the second input, the ripple
Power tube opens lower power tube shut-off on the output end output pulse signal control buck converter of supercircuit；
Characterized in that, the line wave generation circuit includes first resistor (R1), second resistance (R2), 3rd resistor (R3), the
Four resistance (R4), the 5th resistance (R5), the 6th resistance (R6), the 7th resistance (R7), the 8th resistance (R8), the 9th resistance (R9),
First electric capacity (C1), the second electric capacity (C2), the 3rd electric capacity (C3), the 4th electric capacity (C4), the 5th electric capacity (C5), the 6th electric capacity
(C6), the first NMOS tube (MN1), the second NMOS tube (MN2), the 3rd NMOS tube (MN3), the first PMOS (MP1), the 2nd PMOS
Pipe (MP2) and the 3rd buffer (BUF),
One end of first resistor (R1) is input into buck converter lower power tube section as the input of the line wave generation circuit
The voltage at point (SW) place, its other end is grounded afterwards by the first electric capacity (C1)；
Second resistance (R2) and 3rd resistor (R3) are connected, its series connection point output triangle wave voltage (VF1) and connect the ripple fold
The first input end on road, another termination first resistor (R1) of second resistance (R2) and the tie point of the first electric capacity (C1) are powered up,
The other end ground connection of 3rd resistor (R3)；
4th resistance (R4) and the second electric capacity (C2) are connected, and the other end of the 4th resistance (R4) connects second resistance (R2) and the 3rd
The series connection point of resistance (R3), the other end ground connection of the second electric capacity (C2)；
5th resistance (R5) and the 3rd electric capacity (C3) are connected, and its series connection point connects the positive input of the 3rd buffer (BUF), the
The other end of five resistance (R5) connects the series connection point of the 4th resistance (R4) and the second electric capacity (C2), the other end of the 3rd electric capacity (C3)
Ground connection；
The negative input of the 3rd buffer (BUF) connects the source electrode of the first NMOS tube (MN1) and by after the 6th resistance (R6)
Ground connection, the grid of its output the first NMOS tube of termination (MN1)；
The source electrode of the first PMOS (MP1) and the second PMOS (MP2) is interconnected and connects supply voltage (VCC), its gate interconnection is simultaneously
Connect the drain electrode of the first PMOS (MP1) and the first NMOS tube (MN1)；
The grid of the second NMOS tube (MN2) connects to be believed with the control of buck converter lower power tube node (SW) place signal inversion
Number, its drain electrode connects the drain electrode of the second PMOS (MP2) and the 3rd NMOS tube (MN3), its source ground；
The grid of the 3rd NMOS tube (MN3) connects to be believed with buck converter lower power tube node (SW) place's signal with the control of phase
Number, its source electrode after the parallel-connection structure of the 5th electric capacity (C5) and the 7th resistance (R7) by being grounded；
8th resistance (R8) and the 4th electric capacity (C4) are connected, the source of the NMOS tube (MN3) of another termination the 3rd of the 8th resistance (R8)
Pole, the other end ground connection of the 4th electric capacity (C4)；
9th resistance (R9) and the 6th electric capacity (C6) are connected, its series connection point output DC voltage (VSW_DC) and connect the ripple fold
Second input on road, the resistance (R8) of another termination the 8th of the 9th resistance (R9) and the series connection point of the 4th electric capacity (C4) are powered up,
The other end ground connection of the 6th electric capacity (C6).
2. the dynamic suitable for buck converter output DC maladjustment according to claim 1 eliminates circuit, and its feature exists
In the ripple supercircuit also includes the first buffer (BUF1), the second buffer (BUF2), the tenth resistance (R10) and arteries and veins
Width modulation comparator (PWM),
The input input feedback voltage (V of the first buffer (BUF1)FB), its output end is connected afterwards by the tenth resistance (R10)
The output end of trsanscondutance amplifier (Gm) and the positive input of pulse width modulated comparator (PWM)；
The input input reference voltage (V of the second buffer (BUF2)REF), its output end connects pulse width modulated comparator (PWM)
Negative input, the output end of pulse width modulated comparator (PWM) as the ripple supercircuit output end.
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| CN113078817B (en) * | 2021-03-29 | 2022-03-25 | 浙江大学 | Interphase current balance control system suitable for hysteresis control high-frequency two-phase Buck converter |
| CN113607329A (en) * | 2021-07-13 | 2021-11-05 | 复旦大学 | Pressure sensor signal temperature compensation method and pressure sensor |
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| CN117175938B (en) * | 2023-11-02 | 2024-01-30 | 拓尔微电子股份有限公司 | DC-DC converter |
| CN117650701A (en) * | 2024-01-30 | 2024-03-05 | 芯昇科技有限公司 | Step-down circuit |
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