CN204408184U - A kind of Boost type dc-dc synchronizing power pipe current-limiting circuit - Google Patents

Abstract

The utility model for surge current when starting in existing Boost circuit to main switch Q ₂, synchronizing power pipe Q ₁and to the risk that the existence of apparatus of output terminal damages, propose a kind of Boost type dc-dc synchronizing power pipe current-limiting circuit, comprise electric current and voltage detection unit, flow-restriction and synchronizing power pipe Q ₁, electric current and voltage detection unit are for detecting synchronizing power pipe Q ₁output voltage V _oUTwith input voltage V _iNbetween pressure reduction, and by under-voltage for testing result control signal V _uVLObe delivered in flow-restriction and logic control circuit; This circuit can realize synchronizing power pipe Q ₁the function of the restriction of electric current, whole circuit structure of the present utility model is succinct, precision is high, response is quick, can improve the reliability of system.

Description

A kind of Boost type dc-dc synchronizing power pipe current-limiting circuit

Technical field

The utility model belongs to electronic circuit technology field, relates to analog integrated circuit, particularly a kind of Boost type dc-dc synchronizing power pipe current-limiting circuit.

Background technology

Along with the fast development of semiconductor technology and the continuous expansion of application, Boost circuit converts low dc voltage to High Level DC Voltage, realizes the boosting of direct voltage, and therefore Boost circuit is generally applied in daily life.Boost circuit is generally made up of control circuit, switching tube, energy-storage travelling wave tube inductance, electric capacity.Its boost process is by the energy transfer process of an inductance.During charging, inductance absorbs energy, and during electric discharge, inductance releases energy.

The system configuration of typical synchronized model Boost dc-dc as shown in Figure 1.This circuit adopts a negative voltage feedback loop, realizes controlling by pulse-width modulation method (PWM).Wherein Q ₂for main switch, Q ₁for synchronizing power pipe.Its operation principle is: output voltage V _oUTthrough sampling resistor R _sNS1and R _sNS2dividing potential drop obtains V _fBafterwards with reference voltage V _rcompare, its difference through error amplifier EA amplify after after overcompensation network, as the in-phase input end of pulse-width modulator PWM comparator, by comparing with the ramp signal of PWM comparator inverting input, carry out control synchronization power tube Q with relatively rear gained signal through logic control circuit ₁with main switch Q ₂open and shut off.As output voltage V _oUTduring decline, by sampling resistor R _sNS1and R _sNS2dividing potential drop gained feedback voltage signal can decline, then the voltage after being amplified by error amplifier can be increased, and makes main switch Q ₂oN time increase, output voltage rise; Vice versa.Voltage mode control maintains the constant of output by this degenerative mode.But, this Boost circuit due to startup stage input directly by synchronizing power pipe Q ₁give and export charging, synchronizing power pipe Q ₁face very large surge current, and if at synchronizing power pipe Q ₁main switch Q is opened when electric current is larger ₂, then there is the risk damaging power tube.

Utility model content

The purpose of this utility model is, for surge current when starting in above-mentioned Boost circuit to main switch Q ₂, synchronizing power pipe Q ₁and to the risk that the existence of apparatus of output terminal damages, propose a kind of Boost type dc-dc synchronizing power pipe current-limiting circuit, this circuit can realize synchronizing power pipe Q ₁the function of the restriction of electric current, whole circuit structure of the present utility model is succinct, precision is high, response is quick, can improve the reliability of system.

For achieving the above object, the utility model adopts following technical scheme to be solved:

A kind of Boost type dc-dc synchronizing power pipe current-limiting circuit, comprises as lower unit:

Electric current and voltage detection unit, for detecting synchronizing power pipe Q ₁output voltage V _oUTwith input voltage V _iNbetween pressure reduction, and by under-voltage for testing result control signal V _uVLObe delivered in flow-restriction and logic control circuit; And adopt negative feedback to hold synchronizing power pipe Q ₁output voltage V _oUT, by the synchronizing power pipe Q of sampling resistor extraction ₁the electric current I of mirror image pipe _sENSEbe converted to magnitude of voltage and current sampling signal V _iS, and by current sampling signal V _iSbe delivered to flow-restriction;

Flow-restriction, for control synchronization power tube Q ₁current value, and the current sampling signal V that will receive _iSwith external reference voltage V _rEFrelatively, finally by comparative result grid control signal V _gATEdirect connection synchronizing power pipe Q ₁grid, by Current Control in OK range.

Synchronizing power pipe Q ₁: for receiving the grid control signal V of flow-restriction _gATE, and provide output voltage V to electric current and voltage detection unit _oUT, node voltage V _sWwith underlayer voltage V _bODY;

The DC power supply first electric capacity C in parallel of input ₁after obtain input voltage V _iN, the first inductance L ₁be connected on the first electric capacity C ₁with synchronizing power pipe Q ₁between, under-voltage control signal V _uVLObe connected to the under-voltage control end of flow-restriction and logic control circuit; The output grid control signal V of flow-restriction _gATEbe connected to synchronizing power pipe Q ₁grid; Synchronizing power pipe Q ₁main switch Q in parallel between source electrode with ground ₂, drain the second electric capacity C in parallel ₂, and be connected to output voltage V _oUT; Output voltage V _oUTthrough sampling resistor R _sNS1and R _sNS2connect the end of oppisite phase of error amplifier EA after dividing potential drop, error amplifier EA in-phase end connects reference signal V _r, its output is connected to compensating network; The in-phase end of pulse-width modulator PWM connects compensating network, and its end of oppisite phase connects ramp signal, and output is connected to logic control circuit PWM control end; Logic control circuit clock signal terminal input clock signal, its drived control end connects the input of dead zone function, and the driver output end of dead zone function is connected to synchronizing power pipe Q ₁grid and main switch Q ₂grid.

Further, described electric current and voltage detection unit, comprise the first inverter, the second inverter, power mirror as PMOS M ₁₀₁, PMOS M ₁₀₂, PMOS M ₁₀₄, PMOS M ₁₀₇, PMOS M ₁₀₉, PMOS M ₁₁₁, PMOS M ₁₁₂, PMOS M ₁₁₃, NMOS tube M ₁₀₃, NMOS tube M ₁₀₅, NMOS tube M ₁₀₆, NMOS tube M ₁₀₈, NMOS tube M ₁₁₀, the first resistance R ₁, the second resistance R ₂, the first diode D ₁, the second diode D ₂, the first electric capacity C ₁with current source I _s1; Wherein:

Described current source I _s1input access internal electric source V _dD, its output connects NMOS tube M ₁₀₆drain and gate, NMOS tube M ₁₀₆source electrode be connected to the ground; NMOS tube M ₁₀₃, NMOS tube M ₁₀₅, NMOS tube M ₁₀₈, NMOS tube M ₁₁₀structure current mirror in a row, their grid and NMOS tube M ₁₀₆grid be connected, their source electrode is connected to the ground;

Described power mirror is as PMOS M ₁₀₁, itself and synchronizing power pipe Q ₁composition mirror image, its source electrode and node voltage V _sWbe connected, its grid and grid control signal V _gATEbe connected, its substrate and underlayer voltage V _bODYbe connected, its drain electrode respectively with PMOS M ₁₀₂with PMOS M ₁₁₁source electrode be connected, and power mirror is as PMOS M ₁₀₁source electrode connect the first diode D ₁positive pole, the first diode D ₁negative pole connects its substrate, and power mirror is as PMOS M ₁₀₁drain electrode connect the second diode D ₂positive pole, the second diode D ₂negative pole connect its substrate;

Described PMOS M ₁₀₂with PMOS M ₁₀₄form inverter, wherein PMOS M ₁₀₂grid, drain electrode all with PMOS M ₁₀₄grid, NMOS tube M ₁₀₃drain electrode is connected; PMOS M ₁₀₄source electrode and output voltage V _oUTbe connected and with PMOS M ₁₀₇source electrode be connected, its drain electrode with PMOS M ₁₁₁grid and NMOS tube M ₁₀₅drain electrode be connected; PMOS M ₁₁₁drain electrode and the second resistance R ₂with current sampling signal V _iSbe connected, the second resistance R ₂be connected to the ground;

Described PMOS M ₁₀₇with PMOS M ₁₀₉form inverter, wherein PMOS M ₁₀₉grid, drain electrode all with PMOS M ₁₀₇grid, NMOS tube M ₁₁₀drain electrode is connected, PMOS M ₁₀₉source electrode and the first resistance R ₁be connected, the other end of the first resistance R1 and input voltage V _iNbe connected; PMOS M ₁₀₇drain electrode respectively with NMOS tube M ₁₀₈drain electrode be connected with the input of the first inverter;

The output of described first inverter respectively with input, the PMOS M of the second inverter ₁₁₂grid and under-voltage control signal V _uVLObe connected; The output of the second inverter and PMOS M ₁₁₃grid be connected; PMOS M ₁₁₂, M ₁₁₃drain electrode respectively with output voltage V _oUTwith input voltage V _iNbe connected, PMOS M ₁₁₂, M ₁₁₃source electrode and substrate all with the first electric capacity C ₁with internal electric source V _dDbe connected, the first electric capacity C ₁ground connection.

Further, described flow-restriction, comprises the 3rd inverter, current source I _s2, PMOS M ₂₀₁, PMOS M ₂₀₃, PMOS M ₂₀₅, PMOS M ₂₀₇, PMOS M ₂₀₉, NMOS tube M ₂₀₂, NMOS tube M ₂₀₄, NMOS tube M ₂₀₆, NMOS tube M ₂₀₈with NMOS tube M ₂₁₀; Wherein:

Described current source I _s2, its input termination internal electric source V _dD, its output is connected on PMOS M ₂₀₃and M ₂₀₅source electrode on;

Described PMOS M ₂₀₁, M ₂₀₉source electrode meet internal electric source V _dD, PMOS M ₂₀₁grid, drain electrode all with PMOS M ₂₀₉grid and NMOS tube M ₂₀₂drain electrode be connected; PMOS M ₂₀₉drain electrode respectively with NMOS tube M ₂₁₀drain electrode, grid control signal V _gATEbe connected;

Described PMOS M ₂₀₃grid and external reference voltage V _rEFbe connected, its drain electrode respectively with NMOS tube M ₂₀₄leakage, grid and NMOS tube M ₂₀₂grid be connected; Described PMOS M ₂₀₅grid and current sampling signal V _iSbe connected, its drain electrode respectively with NMOS tube M ₂₀₆leakage, grid and NMOS tube M ₂₁₀grid be connected; NMOS tube M ₂₀₂, NMOS tube M ₂₀₄, NMOS tube M ₂₀₆with NMOS tube M ₂₁₀source electrode be all connected to the ground;

Described PMOS M ₂₀₇drain electrode and PMOS M ₂₀₉grid be connected, its grid and under-voltage control signal V _uVLObe connected, its source electrode and internal electric source V _dDbe connected; NMOS tube M ₂₀₈drain electrode and NMOS tube M ₂₁₀grid be connected, its grid is connected with the output of the 3rd inverter; The input of the 3rd inverter and under-voltage control signal V _uVLObe connected, NMOS tube M ₂₀₈source electrode be connected to the ground.

Further, described flow-restriction, comprises the 3rd inverter, current source I _s1, PMOS M ₂₀₁, PMOS M ₂₀₂, PMOS M ₂₀₃, PMOS M ₂₀₄, PMOS M ₂₀₇, PMOS M ₂₀₈, PMOS M ₂₁₁, NMOS tube M ₂₀₅, NMOS tube M ₂₀₆, NMOS tube M ₂₀₉, NMOS tube M ₂₁₀with NMOS tube M ₂₁₂; Wherein:

Described current source I _s1input termination internal electric source V _dD, its output is connected on PMOS M ₂₀₁and M ₂₀₂source electrode on;

Described PMOS M ₂₀₁grid and current sampling signal V _iSbe connected, its drain electrode respectively with NMOS tube M ₂₀₆drain electrode and NMOS tube M ₂₀₅source electrode be connected; PMOS M ₂₀₂grid and external reference voltage V _rEFbe connected, its drain electrode respectively with NMOS tube M ₂₁₀drain electrode and NMOS tube M ₂₀₉source electrode be connected;

Described PMOS M ₂₀₃, M ₂₀₇source electrode meet internal electric source V _dD, PMOS M ₂₀₃and M ₂₀₇grid all with PMOS M ₂₀₄drain electrode and NMOS tube M ₂₀₅drain electrode be connected, wherein PMOS M ₂₀₃drain electrode and PMOS M ₂₀₄source electrode be connected, PMOS M ₂₀₇drain electrode and PMOS M ₂₀₈source electrode connect;

Described PMOS M ₂₀₄and M ₂₀₈grid all with input voltage V _b1be connected, NMOS tube M ₂₀₄drain electrode and NMOS tube M ₂₀₅drain electrode be connected, PMOS M ₂₀₈drain electrode and NMOS tube M ₂₀₉drain and gate control signal V _gATEbe connected;

Described NMOS tube M ₂₀₅and M ₂₀₉grid all with input voltage V _b2be connected, NMOS tube M ₂₀₅source electrode and NMOS tube M ₂₀₆drain electrode be connected, NMOS tube M ₂₀₉source electrode and NMOS tube M ₂₁₀drain electrode be connected;

Described NMOS tube M ₂₀₆and M ₂₁₀grid all with input voltage V _b3be connected, their source electrode is all connected to the ground;

Described PMOS M ₂₁₁drain electrode respectively with PMOS M ₂₀₄with PMOS M ₂₀₈grid be connected, its source electrode and internal electric source V _dDbe connected, its grid and under-voltage control signal V _uVLObe connected;

Described NMOS tube M ₂₁₂drain electrode respectively with NMOS tube M ₂₀₅with NMOS tube M ₂₀₉grid be connected, its source electrode is connected to the ground, and its grid is connected with the output of the 3rd inverter; 3rd inverter input and under-voltage control signal V _uVLObe connected.

Further, described electric current and voltage detection unit, comprise the first inverter, the second inverter, current source I _s1, the first resistance R ₁, the second resistance R ₂, the 3rd resistance R ₃, the 4th resistance R ₄, the 5th resistance R ₅, the first diode D ₁, the second diode D ₂, the first electric capacity C ₁, power mirror is as PMOS M ₁₁₅, PMOS M ₁₀₁, PMOS M ₁₀₃, PMOS M ₁₀₅, PMOS M ₁₁₁, PMOS M ₁₁₃, PMOS M ₁₁₆, PMOS M ₁₁₇, PMOS M ₁₁₈, NMOS tube M ₁₀₂, NMOS tube M ₁₀₄, NMOS tube M ₁₀₆, NMOS tube M ₁₀₇, NMOS tube M ₁₀₈, NMOS tube M ₁₀₉, NMOS tube M ₁₁₀, NMOS tube M ₁₁₂with NMOS tube M ₁₁₄; Wherein:

Described current source I _s1input termination internal electric source V _dD, its output is connected on NMOS tube M ₁₀₇drain and gate on;

Described NMOS tube M ₁₀₂, M ₁₀₄, M ₁₀₆, M ₁₀₇and M ₁₁₀structure current mirror in a row, and their source electrode all ground connection, wherein NMOS tube M ₁₀₂, M ₁₀₄, M ₁₀₆and M ₁₁₀grid be all connected to NMOS tube M ₁₀₇grid on;

Described NMOS tube M ₁₁₀drain electrode be connected on composition differential pair NMOS tube M ₁₀₈and M ₁₀₉source electrode on; Wherein NMOS tube M ₁₀₈drain electrode be connected on PMOS M ₁₁₃source electrode on; NMOS tube M ₁₀₉drain electrode be connected on PMOS M ₁₁₁source electrode on; NMOS tube M ₁₁₂drain electrode be connected on NMOS tube M respectively ₁₁₂with NMOS tube M ₁₁₄grid on, simultaneously with PMOS M ₁₁₁drain electrode connects; NMOS tube M ₁₁₄drain electrode be connected on PMOS M ₁₁₃drain electrode and PMOS M ₁₁₆grid on; Wherein PMOS M ₁₁₁with PMOS M ₁₁₃grid and input voltage V _b1be connected; NMOS tube M ₁₁₂with NMOS tube M ₁₁₄source ground;

Described NMOS tube M ₁₀₉and M ₁₀₈form differential pair, their drain electrode is respectively by the 3rd resistance R ₃with the 4th resistance R ₄be connected on node voltage V _sWon, their grid then receives output voltage V respectively _oUTwith power mirror as PMOS M ₁₁₅drain electrode on;

Described PMOS M ₁₀₁source electrode and the first resistance R ₁be connected, the first resistance R ₁the other end and node voltage V _sWbe connected, PMOS M ₁₀₁grid and drain electrode all with NMOS tube M ₁₀₂drain electrode and input voltage V _b1be connected;

Described power mirror is as PMOS M ₁₁₅, itself and synchronizing power pipe Q ₁composition mirror image, its source electrode and node voltage V _sWbe connected, its grid and grid control signal V _gATEbe connected, its substrate and underlayer voltage V _bODYbe connected, its drain electrode and PMOS M ₁₁₆source electrode is connected, and power mirror is as PMOS M ₁₁₅source electrode connect the first diode D ₁positive pole, the first diode D ₁negative pole connects its substrate, its drain electrode connection second diode D ₂positive pole, the second diode D ₂negative pole connects its substrate; Wherein PMOS M ₁₁₆drain electrode respectively with the 5th resistance R ₅with current sampling signal V _iSbe connected; 5th resistance R ₅the other end be connected to the ground;

Described PMOS M ₁₀₃grid and drain electrode all with PMOS M ₁₀₅grid be connected; PMOS M ₁₀₃source electrode and the second resistance R ₂be connected, its drain electrode and NMOS tube M ₁₀₄drain electrode be connected; Second resistance R ₂the other end and input voltage V _iNbe connected; PMOS M ₁₀₅source electrode and output voltage V _oUTbe connected, its drain electrode respectively with NMOS tube M ₁₀₆drain electrode and under-voltage control signal V _uVLObe connected;

Described second inverter input and NMOS tube M ₁₀₆drain electrode be connected, its output respectively with PMOS M ₁₁₈grid, the first inverter input and under-voltage control signal V _uVLObe connected; The output of the first inverter and PMOS M ₁₁₇grid be connected; PMOS M ₁₁₈drain electrode and output voltage V _oUTbe connected, its substrate and source electrode all with PMOS M ₁₁₇substrate be connected with source electrode, and be connected to internal electric source V _dDon; First electric capacity C ₁one end connect internal electric source V _dD, other end ground connection; PMOS M ₁₁₇drain electrode and input voltage V _iNbe connected.

Traditional scheme when circuit start, now main switch Q ₂conducting, synchronizing power pipe Q ₁close, inductance L ₁start store electrical energy; As synchronizing power pipe Q ₁when source voltage arrives output valve, main switch Q ₂close, synchronizing power pipe Q ₁conducting, and now inductance L ₁on store very large electric current will by synchronizing power pipe Q ₁, synchronizing power pipe Q1 easily can be caused to damage; And as main switch Q ₂conducting, synchronizing power pipe Q ₁close, inductance L ₁electric current is by main switch Q ₂, main switch Q can be caused equally ₂damage.

Another problem of traditional circuit is that inductive current can by synchronizing power pipe Q ₁substrate and gang up, synchronizing power pipe Q ₁substrate be connected on its drain electrode on, now formed a diode, as synchronizing power pipe Q ₁when source voltage is higher than drain electrode, the diode that inductive current can be formed by this arrives output, has an impact to output.

The utility model when circuit start, main switch Q ₂close, synchronizing power pipe Q ₁conducting, increases electric current and voltage detection unit, by synchronizing power pipe Q ₁mirror image pipe and the second resistance by synchronizing power pipe Q ₁current conversion become magnitude of voltage and current sampling signal V _iS, and by current sampling signal V _iSpass to current limiting unit, make it compare, by comparative result control synchronization power tube Q with the threshold voltage of setting ₁grid voltage, thus limits synchronization power tube Q ₁charging current, make synchronizing power pipe Q ₁slowly charge, as synchronizing power pipe Q ₁drain voltage 200mV lower than input voltage time, open main switch Q ₂conducting, now current limiting unit is closed, and circuit starts normal work, prevents inductance L 1 from can store excessive electric current to main switch Q like this ₂with synchronizing power pipe Q ₁cause damage.

The utility model is at synchronizing power pipe Q ₁substrate add the diode of two reversal connections, the electric current preventing inductive current directly to be caused by substrate is ganged up.

The utility model compared with prior art has the following advantages:

1, the utility model is by sample-synchronous power tube Q ₁mirror image tube current is also changed into magnitude of voltage and current sampling signal V _iScompare with external reference voltage thus limits synchronization power tube Q ₁charging current, as synchronizing power pipe Q ₁drain electrode when soon reaching input voltage, circuit starts work of boosting normally, compared with traditional voltage mode control, can available protecting synchronizing power pipe Q ₁with main switch Q ₂.

2, the utility model is at synchronizing power pipe Q ₁source, increase diode between drain electrode and substrate, the electric current preventing inductive current directly to be caused by substrate is ganged up.

Accompanying drawing explanation

Fig. 1 is the system block diagram of traditional Boost circuit.

Fig. 2 is the structured flowchart of Boost type dc-dc synchronizing power pipe current-limiting circuit of the present utility model.

Fig. 3 is the schematic diagram of electric current in the utility model embodiment 1 and voltage detection unit.

Fig. 4 is the schematic diagram of the current-limiting circuit unit in the utility model embodiment 1.

Fig. 5 is the schematic diagram of the current-limiting circuit unit in the utility model embodiment 2.

Fig. 6 is the schematic diagram of electric current in the utility model embodiment 3 and voltage detection unit.

In accompanying drawing: 1-electric current and voltage detection unit, 2-current-limiting circuit unit, 101-first inverter, 102-second inverter, 201-the 3rd inverter.

Below in conjunction with accompanying drawing and embodiment, the utility model is further described.

Embodiment

Embodiment 1:

With reference to Fig. 2, Boost type dc-dc synchronizing power pipe current-limiting circuit of the present utility model, comprises electric current and voltage detection unit 1 and flow-restriction 1.

Described voltage and current detecting unit 1 are provided with four inputs b, c, e, f and three outputs a, d, g; Described flow-restriction 2 is provided with three inputs h, i, k and an output j; Wherein voltage is connected input voltage V with the first input end b of current detecting unit 1 _iN; Second input c, the 3rd input f are connected synchronizing power pipe Q respectively with four-input terminal e ₁source electrode, grid and drain electrode and node voltage V _sW, grid control signal V _gATEwith output voltage V _oUT; Wherein the first output a exports under-voltage control signal V _uVLOto the under-voltage control end of logic control circuit and flow-restriction 2 the 5th input h; Second output d connects synchronizing power pipe Q ₁substrate and substrate electric potential underlayer voltage V _bODY; 3rd output g connects the 6th input i and the current sampling signal V of flow-restriction 2 _iS; 7th input k of flow-restriction 2 connects external reference voltage V _rEF; Wherein the 4th output j connects synchronizing power pipe Q ₁grid;

The DC power supply first electric capacity C in parallel of input ₁after obtain input voltage V _iN, the first inductance L ₁be connected on the first electric capacity C ₁with synchronizing power pipe Q ₁between, under-voltage control signal V _uVLObe connected to flow-restriction 2 and logic control circuit; The output grid control signal V of flow-restriction 2 _gATEbe connected to synchronizing power pipe Q ₁grid; Synchronizing power pipe Q ₁main switch Q in parallel between source electrode with ground ₂, drain the second electric capacity C in parallel ₂, and be connected to output voltage V _oUTexport; Output voltage V _oUTthrough sampling resistor R _sNS1and R _sNS2dividing potential drop connects error amplifier EA end of oppisite phase, and error amplifier EA in-phase end connects reference signal V _r, its output is connected to compensating network; The in-phase end of pulse-width modulator PWM connects compensating network, and its end of oppisite phase connects ramp signal, exports and is connected to logic control circuit PWM control end; Logic control circuit clock signal terminal input clock signal, its drived control end connects the input of dead zone function, and the driver output end of dead zone function is connected to synchronizing power pipe Q ₁grid and main switch Q ₂grid.

As main switch Q ₂conducting, DC power supply flows to the first inductance L ₁, synchronizing power pipe Q ₁prevent the second electric capacity C ₂discharge over the ground, the first inductance L ₁on electric current linearly increase with certain ratio, along with the first inductance L ₁electric current increases, the first inductance L ₁in store some energy; As main switch Q ₂during shutoff, due to the first inductance L ₁electric current retention performance, flow through the first inductance L ₁electric current can not at once vanishing, but value vanishing time complete by charging slowly, and original circuit has disconnected, so the first inductance L ₁start to the second electric capacity C ₂charging, the second electric capacity C ₂both end voltage output voltage V _oUTraise, now voltage output voltage V _oUThigher than input voltage V _iN.

With reference to Fig. 3, the electric current of the present embodiment and voltage detection unit 1, comprise the first inverter 101, second inverter 102, power mirror as PMOS M ₁₀₁, PMOS M ₁₀₂, PMOS M ₁₀₄, PMOS M ₁₀₇, PMOS M ₁₀₉, PMOS M ₁₁₁, PMOS M ₁₁₂, PMOS M ₁₁₃, NMOS tube M ₁₀₃, NMOS tube M ₁₀₅, NMOS tube M ₁₀₆, NMOS tube M ₁₀₈, NMOS tube M ₁₁₀, the first resistance R ₁, the second resistance R ₂, the first diode D ₁, the second diode D ₂, the first electric capacity C ₁with current source I _s1; Wherein:

Described current source I _s1, its input access internal electric source V _dD, its output connects NMOS tube M ₁₀₆drain and gate, NMOS tube M ₁₀₆source electrode be connected to the ground; NMOS tube M ₁₀₃, NMOS tube M ₁₀₅, NMOS tube M ₁₀₈, NMOS tube M ₁₁₀structure current mirror in a row, their grid and NMOS tube M ₁₀₆grid be connected, their source electrode is connected to the ground;

Described power mirror is as PMOS M ₁₀₁, itself and synchronizing power pipe Q ₁composition mirror image, its source electrode and node voltage V _sWbe connected, its grid and grid control signal V _gATEbe connected, its substrate and underlayer voltage V _bODYbe connected, its drain electrode respectively with PMOS M ₁₀₂with PMOS M ₁₁₁source electrode be connected, and power mirror is as PMOS M ₁₀₁source electrode connect the first diode D ₁positive pole, the first diode D ₁negative pole connects its substrate, and power mirror is as PMOS M ₁₀₁drain electrode connect the second diode D ₂positive pole, the second diode D ₂negative pole connect its substrate;

First diode D ₁with the second diode D ₂effect be prevent electric current from directly being ganged up by source-drain electrode by substrate; Wherein power mirror is as PMOS M ₁₀₁electric current I _sENSEwith synchronizing power pipe Q ₁with power mirror as PMOS M ₁₀₁size relevant:

$I_{\mathrm{SENSE}}=\frac{{(W/L)}_{M_{101}}}{{(W/L)}_{Q_1}}---\left(1\right)$

Now, by electric current I _sENSEr is passed through in conversion ₂convert magnitude of voltage and current sampling signal V to _iS:

V _IS＝I _SENSE×R ₂(2)

Described PMOS M ₁₀₂with PMOS M ₁₀₄form inverter, wherein PMOS M ₁₀₂grid, drain electrode all with PMOS M ₁₀₄grid, NMOS tube M ₁₀₃drain electrode is connected; PMOS M ₁₀₄source electrode and output voltage V _oUTbe connected and with PMOS M ₁₀₇source electrode be connected, its drain electrode with PMOS M ₁₁₁grid, NMOS tube M ₁₀₅drain electrode is connected; PMOS M ₁₁₁drain electrode and the second resistance R ₂with current sampling signal V _iSbe connected, the second resistance R ₂be connected to the ground;

Described PMOS M ₁₀₇with PMOS M ₁₀₉form inverter, wherein PMOS M ₁₀₉grid, drain electrode all with PMOS M ₁₀₇grid, NMOS tube M ₁₁₀drain electrode is connected, PMOS M ₁₀₉source electrode and the first resistance R ₁be connected, the first resistance R ₁the other end and input voltage V _iNbe connected; PMOS M ₁₀₇drain electrode respectively with NMOS tube M ₁₀₈drain electrode be connected with the input of the first inverter 101;

The output of described first inverter 101 respectively with input, the PMOS M of the second inverter 102 ₁₁₂grid and under-voltage control signal V _uVLObe connected; The output of the second inverter 102 and PMOS M ₁₁₃grid be connected; PMOS M ₁₁₂, M ₁₁₃drain electrode respectively with output voltage V _oUTwith input voltage V _iNbe connected, PMOS M ₁₁₂, M ₁₁₃source electrode and substrate all with the first electric capacity C ₁with internal electric source V _dDbe connected, the first electric capacity C ₁ground connection.Wherein under-voltage control signal V _uVLOrelevant with reference current IS1:

V _UVLO＝I _S1×R ₁(3)

Voltage source V is selected in the effect of the first inverter 101,102 _dD, as output voltage V _oUThigher than input voltage V _iNtime, select output voltage V _oUTfor internal electric source V _dD, now under-voltage control signal V _uVLOfor low; Otherwise select input voltage V _iNfor voltage source V _dD, now under-voltage control signal V _uVLOfor height; PMOS M ₁₁₂, M ₁₁₃source electrode be connected with substrate, effect prevents V _dDselected after-current passes through substrate anti-channeling to another selecting side, thus guarantees input voltage V _iNwith output voltage V _oUTcan not gang up.

With reference to figure 4, the flow-restriction 2 of the present embodiment, comprises the 3rd inverter 201, current source I _s2, PMOS M ₂₀₁, PMOS M ₂₀₃, PMOS M ₂₀₅, PMOS M ₂₀₇, PMOS M ₂₀₉, NMOS tube M ₂₀₂, NMOS tube M ₂₀₄, NMOS tube M ₂₀₆, NMOS tube M ₂₀₈with NMOS tube M ₂₁₀; Wherein:

Described current source I _s2, its input termination internal electric source V _dD, its output is connected on PMOS M ₂₀₃and M ₂₀₅source electrode on;

Described PMOS M ₂₀₁, M ₂₀₉source electrode meet internal electric source V _dD, PMOS M ₂₀₁grid, drain electrode all with PMOS M ₂₀₉grid and NMOS tube M ₂₀₂drain electrode be connected; PMOS M ₂₀₉drain electrode and NMOS tube M ₂₁₀drain electrode, grid control signal V _gATEbe connected;

Described PMOS M ₂₀₃grid and external reference voltage V _rEFbe connected, its drain electrode respectively with NMOS tube M ₂₀₄leakage, grid and NMOS tube M ₂₀₂grid be connected; Described PMOS M ₂₀₅grid and current sampling signal V _iSbe connected, its drain electrode respectively with NMOS tube M ₂₀₆leakage, grid and NMOS tube M ₂₁₀grid be connected; NMOS tube M ₂₀₂, NMOS tube M ₂₀₄, NMOS tube M ₂₀₆, NMOS tube M ₂₁₀source electrode be all connected to the ground; Wherein external reference voltage V _rEFwith current sampling signal V _iSshould meet following relation:

V _REF＝V _IS(4)

Described PMOS M ₂₀₇drain electrode and PMOS M ₂₀₉grid be connected, its grid and under-voltage control signal V _uVLObe connected, its source electrode and internal electric source V _dDbe connected; NMOS tube M ₂₀₈drain electrode and NMOS tube M ₂₁₀grid be connected, its grid is connected with the output of the 3rd inverter 201; The input of the 3rd inverter 201 and under-voltage control signal V _uVLObe connected, NMOS tube M ₂₀₈source electrode be connected to the ground.

Embodiment 2:

The electric current of the present embodiment and identical in voltage detection unit 1 and embodiment 1.

With reference to Fig. 5, the flow-restriction 2 of the present embodiment, comprises the 3rd inverter 201, current source I _s1, PMOS M ₂₀₁, PMOS M ₂₀₂, PMOS M ₂₀₃, PMOS M ₂₀₄, PMOS M ₂₀₇, PMOS M ₂₀₈, PMOS M ₂₁₁, NMOS tube M ₂₀₅, NMOS tube M ₂₀₆, NMOS tube M ₂₀₉, NMOS tube M ₂₁₀with NMOS tube M ₂₁₂; Wherein:

Described current source I _s1, its input termination internal electric source V _dD, its output is connected on PMOS M ₂₀₁and M ₂₀₂source electrode on;

Described PMOS M ₂₀₁grid and current sampling signal V _iSbe connected, its drain electrode respectively with NMOS tube M ₂₀₆drain electrode and NMOS tube M ₂₀₅source electrode be connected; PMOS M ₂₀₂grid and external reference voltage V _rEFbe connected, its drain electrode respectively with NMOS tube M ₂₁₀drain electrode and NMOS tube M ₂₀₉source electrode be connected;

Described PMOS M ₂₀₃, M ₂₀₇source electrode meet internal electric source V _dD, PMOS M ₂₀₃, M ₂₀₇grid all with PMOS M ₂₀₄drain electrode and NMOS tube M ₂₀₅drain electrode be connected, wherein PMOS M ₂₀₃drain electrode and PMOS M ₂₀₄source electrode be connected, PMOS M ₂₀₇drain electrode and PMOS M ₂₀₈source electrode connect;

Described PMOS M ₂₀₄, M ₂₀₈grid all with input voltage V _b1be connected, NMOS tube M ₂₀₄drain electrode and NMOS tube M ₂₀₅drain electrode be connected, PMOS M ₂₀₈drain electrode and NMOS tube M ₂₀₉drain and gate control signal V _gATEbe connected;

Described NMOS tube M ₂₀₅, M ₂₀₉grid and input voltage V _b2be connected, NMOS tube M ₂₀₅source electrode and NMOS tube M ₂₀₆drain electrode be connected, NMOS tube M ₂₀₉source electrode and NMOS tube M ₂₁₀drain electrode be connected;

Described NMOS tube M ₂₀₆, M ₂₁₀grid and input voltage V _b3be connected, their source electrode is connected to the ground;

Described PMOS M ₂₁₁drain electrode respectively with PMOS M ₂₀₄with PMOS M ₂₀₈grid be connected, its source electrode and internal electric source V _dDbe connected, its grid and under-voltage control signal V _uVLObe connected;

Described NMOS tube M ₂₁₂drain electrode respectively with NMOS tube M ₂₀₅with NMOS tube M ₂₀₉grid be connected, its source electrode is connected to the ground, and its grid is connected with the output of the 3rd inverter 201; 3rd inverter 201 input and under-voltage control signal V _uVLObe connected.

Embodiment 3:

The flow-restriction 2 of the present embodiment and identical in embodiment 1.

With reference to figure 6, the electric current of the present embodiment and voltage detection unit 1, comprise the first inverter 101, second inverter 102, current source I _s1, the first resistance R ₁, the second resistance R ₂, the 3rd resistance R ₃, the 4th resistance R ₄, the 5th resistance R ₅, the first diode D ₁, the second diode D ₂, the first electric capacity C ₁, power mirror is as PMOS M ₁₁₅, PMOS M ₁₀₁, PMOS M ₁₀₃, PMOS M ₁₀₅, PMOS M ₁₁₁, PMOS M ₁₁₃, PMOS M ₁₁₆, PMOS M ₁₁₇, PMOS M ₁₁₈, NMOS tube M ₁₀₂, NMOS tube M ₁₀₄, NMOS tube M ₁₀₆, NMOS tube M ₁₀₇, NMOS tube M ₁₀₈, NMOS tube M ₁₀₉, NMOS tube M ₁₁₀, NMOS tube M ₁₁₂with NMOS tube M ₁₁₄.Wherein:

Described current source I _s1, its input termination internal electric source V _dD, its output is connected on NMOS tube M ₁₀₇drain and gate on;

Described NMOS tube M ₁₀₂, M ₁₀₄, M ₁₀₆, M ₁₀₇and M ₁₁₀structure current mirror in a row, and their source electrode all ground connection, wherein NMOS tube M ₁₀₂, M ₁₀₄, M ₁₀₆and M ₁₁₀grid be all connected to NMOS tube M ₁₀₇grid on;

Described NMOS tube M ₁₁₀drain electrode be connected on composition differential pair NMOS tube M ₁₀₈, M ₁₀₉source electrode on; Wherein NMOS tube M ₁₀₈drain electrode be connected on PMOS M ₁₁₃source electrode on; NMOS tube M ₁₀₉drain electrode be connected on PMOS M ₁₁₁source electrode on; NMOS tube M ₁₁₂drain electrode be connected on NMOS tube M ₁₁₂with NMOS tube M ₁₁₄grid on, simultaneously with PMOS M ₁₁₁drain electrode connects; NMOS tube M ₁₁₄drain electrode be connected on PMOS M ₁₁₃drain electrode and PMOS M ₁₁₆grid on; Wherein PMOS M ₁₁₁with PMOS M ₁₁₃grid and input voltage V _b1be connected; NMOS tube M ₁₁₂with NMOS tube M ₁₁₄source ground;

Described NMOS tube M ₁₀₉and M ₁₀₈form differential pair, their drain electrode is respectively by the 3rd resistance R ₃with the 4th resistance R ₄be connected on node voltage V _sWon, their grid then receives output voltage V respectively _oUTwith power mirror as PMOS M ₁₁₅drain electrode on;

Described PMOS M ₁₀₁source electrode and the first resistance R ₁be connected, the first resistance R ₁the other end and node voltage V _sWbe connected, PMOS M ₁₀₁grid and drain electrode all with NMOS tube M ₁₀₂drain electrode and input voltage V _b1be connected; Its effect improves NMOS tube M ₁₀₆and M ₁₀₈matching.Wherein NMOS tube M ₁₀₂upper reaches overcurrent I _d2with current source I _s1and NMOS tube size relationship:

$I_{D1}=I_{S1}\×\frac{{(W/L)}_{M_{102}}}{{(W/L)}_{M_{107}}}=\frac{I_{S1}}{2}---\left(5\right)$

Described first resistance R ₁, the 3rd resistance R ₃, the 4th resistance R ₄between relation:

R ₁＝2R ₃＝2R ₄(6)

Described power mirror is as PMOS M ₁₁₅, itself and synchronizing power pipe Q ₁composition mirror image, its source electrode and node voltage V _sWbe connected, its grid and grid control signal V _gATEbe connected, its substrate and underlayer voltage V _bODYbe connected, its drain electrode and PMOS M ₁₁₆source electrode is connected, and power mirror is as PMOS M ₁₁₅source electrode connect the first diode D ₁positive pole, the first diode D ₁negative pole connects its substrate, its drain electrode connection second diode D ₂positive pole, the second diode D ₂negative pole connects its substrate; Wherein PMOS M ₁₁₆drain electrode and the 5th resistance R ₅with current sampling signal V _iSbe connected; 5th resistance R ₅the other end be connected to the ground;

Described PMOS M ₁₀₃grid and drain electrode all with PMOS M ₁₀₅grid be connected; PMOS M ₁₀₃source electrode and the second resistance R ₂be connected, its drain electrode and NMOS tube M ₁₀₄drain electrode be connected; Second resistance R ₂the other end and input voltage V _iNbe connected; PMOS M ₁₀₅source electrode and output voltage V _oUTbe connected, its drain electrode respectively with NMOS tube M ₁₀₆drain electrode and under-voltage control signal V _uVLObe connected;

Described second inverter 102 input and NMOS tube M ₁₀₆drain electrode be connected, its output and PMOS M ₁₁₈grid, the first inverter 101 input and under-voltage control signal V _uVLObe connected; The output of the first inverter 101 and PMOS M ₁₁₇grid be connected; PMOS M ₁₁₈drain electrode and output voltage V _oUTbe connected, its substrate and source electrode and PMOS M ₁₁₇substrate be connected with source electrode, and be connected to internal electric source V _dDon; First electric capacity C ₁one end connect internal electric source V _dD, other end ground connection; PMOS M ₁₁₇drain electrode and input voltage V _iNbe connected.

The utility model when circuit start, main switch Q ₂close, synchronizing power pipe Q ₁conducting, increases electric current and voltage detection unit 1, by synchronizing power pipe Q ₁mirror image pipe and the second resistance by synchronizing power pipe Q ₁current conversion become magnitude of voltage and current sampling signal V _iS, and by current sampling signal V _iSpass to current limiting unit 2, itself and external reference voltage are compared, by comparative result control synchronization power tube Q ₁grid voltage, thus limits synchronization power tube Q ₁charging current, make synchronizing power pipe Q ₁slowly charge, as synchronizing power pipe Q ₁drain voltage 200mV lower than input voltage time, open main switch Q ₂conducting, now current limiting unit 2 is closed, and circuit starts normal work, prevents inductance L like this ₁excessive electric current can be stored to main switch Q ₂with synchronizing power pipe Q ₁cause damage.

Below be only three preferred example of the present utility model, do not form any restriction of the present utility model, obviously under design of the present utility model, different changes and improvement can be carried out to its circuit, but these are all at the row of protection of the present utility model.

Claims (6)

1. a Boost type dc-dc synchronizing power pipe current-limiting circuit, is characterized in that: also comprise as lower unit except negative voltage feedback loop:

Electric current and voltage detection unit (1), for detecting synchronizing power pipe Q ₁output voltage V _oUTwith input voltage V _iNbetween pressure reduction, and by under-voltage for testing result control signal V _uVLObe delivered in flow-restriction (2) and logic control circuit; And adopt negative feedback to hold synchronizing power pipe Q ₁output voltage V _oUT, by the synchronizing power pipe Q of sampling resistor extraction ₁the electric current I of mirror image pipe _sENSEbe converted to magnitude of voltage and current sampling signal V _iS, and by current sampling signal V _iSbe delivered to flow-restriction (2);

Flow-restriction (2), for control synchronization power tube Q ₁current value, and the current sampling signal V that will receive _iSwith external reference voltage V _rEFrelatively, finally by comparative result grid control signal V _gATEdirect connection synchronizing power pipe Q ₁grid, by Current Control in OK range;

Synchronizing power pipe Q ₁: for receiving the grid control signal V of flow-restriction (2) _gATE, and provide output voltage V to electric current and voltage detection unit (1) _oUT, node voltage V _sWwith underlayer voltage V _bODY.

2. a kind of Boost type dc-dc synchronizing power pipe current-limiting circuit according to claim 1, is characterized in that: the DC power supply first electric capacity C in parallel of input ₁after obtain input voltage V _iN, the first inductance L ₁be connected on the first electric capacity C ₁with synchronizing power pipe Q ₁between, under-voltage control signal V _uVLObe connected to the under-voltage control end of flow-restriction (2) and logic control circuit; The output grid control signal V of flow-restriction (2) _gATEbe connected to synchronizing power pipe Q ₁grid; Synchronizing power pipe Q ₁main switch Q in parallel between source electrode with ground ₂, drain the second electric capacity C in parallel ₂, and be connected to output voltage V _oUT; Output voltage V _oUTthrough sampling resistor R _sNS1and R _sNS2connect the end of oppisite phase of error amplifier EA after dividing potential drop, error amplifier EA in-phase end connects reference signal V _r, its output is connected to compensating network; The in-phase end of pulse-width modulator PWM connects compensating network, and its end of oppisite phase connects ramp signal, and output is connected to logic control circuit PWM control end; Logic control circuit clock signal terminal input clock signal, its drived control end connects the input of dead zone function, and the driver output end of dead zone function is connected to synchronizing power pipe Q ₁grid and main switch Q ₂grid.

3. a kind of Boost type dc-dc synchronizing power pipe current-limiting circuit according to claim 1, it is characterized in that: described electric current and voltage detection unit (1), comprise the first inverter (101), the second inverter (102), power mirror as PMOS M ₁₀₁, PMOS M ₁₀₂, PMOS M ₁₀₄, PMOS M ₁₀₇, PMOS M ₁₀₉, PMOS M ₁₁₁, PMOS M ₁₁₂, PMOS M ₁₁₃, NMOS tube M ₁₀₃, NMOS tube M ₁₀₅, NMOS tube M ₁₀₆, NMOS tube M ₁₀₈, NMOS tube M ₁₁₀, the first resistance R ₁, the second resistance R ₂, the first diode D ₁, the second diode D ₂, the first electric capacity C ₁with current source I _s1; Wherein:

Described current source I _s1input access internal electric source V _dD, its output connects NMOS tube M ₁₀₆drain and gate, NMOS tube M ₁₀₆source electrode be connected to the ground; NMOS tube M ₁₀₃, NMOS tube M ₁₀₅, NMOS tube M ₁₀₈, NMOS tube M ₁₁₀structure current mirror in a row, their grid and NMOS tube M ₁₀₆grid be connected, their source electrode is connected to the ground;

Described power mirror is as PMOS M ₁₀₁, itself and synchronizing power pipe Q ₁composition mirror image, its source electrode and node voltage V _sWbe connected, its grid and grid control signal V _gATEbe connected, its substrate and underlayer voltage V _bODYbe connected, its drain electrode respectively with PMOS M ₁₀₂with PMOS M ₁₁₁source electrode be connected, and power mirror is as PMOS M ₁₀₁source electrode connect the first diode D ₁positive pole, the first diode D ₁negative pole connects its substrate, and power mirror is as PMOS M ₁₀₁drain electrode connect the second diode D ₂positive pole, the second diode D ₂negative pole connect its substrate;

Described PMOS M ₁₀₂with PMOS M ₁₀₄form inverter, wherein PMOS M ₁₀₂grid, drain electrode all with PMOS M ₁₀₄grid, NMOS tube M ₁₀₃drain electrode is connected; PMOS M ₁₀₄source electrode and output voltage V _oUTbe connected and with PMOS M ₁₀₇source electrode be connected, its drain electrode with PMOS M ₁₁₁grid and NMOS tube M ₁₀₅drain electrode be connected; PMOS M ₁₁₁drain electrode and the second resistance R ₂with current sampling signal V _iSbe connected, the second resistance R ₂be connected to the ground;

Described PMOS M ₁₀₇with PMOS M ₁₀₉form inverter, wherein PMOS M ₁₀₉grid, drain electrode all with PMOS M ₁₀₇grid, NMOS tube M ₁₁₀drain electrode is connected, PMOS M ₁₀₉source electrode and the first resistance R ₁be connected, the other end of the first resistance R1 and input voltage V _iNbe connected; PMOS M ₁₀₇drain electrode respectively with NMOS tube M ₁₀₈drain electrode be connected with the input of the first inverter (101);

The output of described first inverter (101) respectively with input, the PMOS M of the second inverter (102) ₁₁₂grid and under-voltage control signal V _uVLObe connected; The output of the second inverter (102) and PMOS M ₁₁₃grid be connected; PMOS M ₁₁₂, M ₁₁₃drain electrode respectively with output voltage V _oUTwith input voltage V _iNbe connected, PMOS M ₁₁₂, M ₁₁₃source electrode and substrate all with the first electric capacity C ₁with internal electric source V _dDbe connected, the first electric capacity C ₁ground connection.

4. a kind of Boost type dc-dc synchronizing power pipe current-limiting circuit according to claim 1, is characterized in that: described flow-restriction, comprises the 3rd inverter (201), current source I _s2, PMOS M ₂₀₁, PMOS M ₂₀₃, PMOS M ₂₀₅, PMOS M ₂₀₇, PMOS M ₂₀₉, NMOS tube M ₂₀₂, NMOS tube M ₂₀₄, NMOS tube M ₂₀₆, NMOS tube M ₂₀₈with NMOS tube M ₂₁₀; Wherein:

Described current source I _s2, its input termination internal electric source V _dD, its output is connected on PMOS M ₂₀₃and M ₂₀₅source electrode on;

Described PMOS M ₂₀₁, M ₂₀₉source electrode meet internal electric source V _dD, PMOS M ₂₀₁grid, drain electrode all with PMOS M ₂₀₉grid and NMOS tube M ₂₀₂drain electrode be connected; PMOS M ₂₀₉drain electrode respectively with NMOS tube M ₂₁₀drain electrode, grid control signal V _gATEbe connected;

Described PMOS M ₂₀₃grid and external reference voltage V _rEFbe connected, its drain electrode respectively with NMOS tube M ₂₀₄leakage, grid and NMOS tube M ₂₀₂grid be connected; Described PMOS M ₂₀₅grid and current sampling signal V _iSbe connected, its drain electrode respectively with NMOS tube M ₂₀₆leakage, grid and NMOS tube M ₂₁₀grid be connected; NMOS tube M ₂₀₂, NMOS tube M ₂₀₄, NMOS tube M ₂₀₆with NMOS tube M ₂₁₀source electrode be all connected to the ground;

Described PMOS M ₂₀₇drain electrode and PMOS M ₂₀₉grid be connected, its grid and under-voltage control signal V _uVLObe connected, its source electrode and internal electric source V _dDbe connected; NMOS tube M ₂₀₈drain electrode and NMOS tube M ₂₁₀grid be connected, its grid is connected with the output of the 3rd inverter (201); The input of the 3rd inverter (201) and under-voltage control signal V _uVLObe connected, NMOS tube M ₂₀₈source electrode be connected to the ground.

5. a kind of Boost type dc-dc synchronizing power pipe current-limiting circuit according to claim 1, is characterized in that: described flow-restriction, comprises the 3rd inverter (201), current source I _s1, PMOS M ₂₀₁, PMOS M ₂₀₂, PMOS M ₂₀₃, PMOS M ₂₀₄, PMOS M ₂₀₇, PMOS M ₂₀₈, PMOS M ₂₁₁, NMOS tube M ₂₀₅, NMOS tube M ₂₀₆, NMOS tube M ₂₀₉, NMOS tube M ₂₁₀with NMOS tube M ₂₁₂; Wherein:

Described current source I _s1input termination internal electric source V _dD, its output is connected on PMOS M ₂₀₁and M ₂₀₂source electrode on;

Described PMOS M ₂₀₁grid and current sampling signal V _iSbe connected, its drain electrode respectively with NMOS tube M ₂₀₆drain electrode and NMOS tube M ₂₀₅source electrode be connected; PMOS M ₂₀₂grid and external reference voltage V _rEFbe connected, its drain electrode respectively with NMOS tube M ₂₁₀drain electrode and NMOS tube M ₂₀₉source electrode be connected;

Described PMOS M ₂₀₃, M ₂₀₇source electrode meet internal electric source V _dD, PMOS M ₂₀₃and M ₂₀₇grid all with PMOS M ₂₀₄drain electrode and NMOS tube M ₂₀₅drain electrode be connected, wherein PMOS M ₂₀₃drain electrode and PMOS M ₂₀₄source electrode be connected, PMOS M ₂₀₇drain electrode and PMOS M ₂₀₈source electrode connect;

Described PMOS M ₂₀₄and M ₂₀₈grid all with input voltage V _b1be connected, NMOS tube M ₂₀₄drain electrode and NMOS tube M ₂₀₅drain electrode be connected, PMOS M ₂₀₈drain electrode and NMOS tube M ₂₀₉drain and gate control signal V _gATEbe connected;

Described NMOS tube M ₂₀₅and M ₂₀₉grid all with input voltage V _b2be connected, NMOS tube M ₂₀₅source electrode and NMOS tube M ₂₀₆drain electrode be connected, NMOS tube M ₂₀₉source electrode and NMOS tube M ₂₁₀drain electrode be connected;

Described NMOS tube M ₂₀₆and M ₂₁₀grid all with input voltage V _b3be connected, their source electrode is all connected to the ground;

Described PMOS M ₂₁₁drain electrode respectively with PMOS M ₂₀₄with PMOS M ₂₀₈grid be connected, its source electrode and internal electric source V _dDbe connected, its grid and under-voltage control signal V _uVLObe connected;

Described NMOS tube M ₂₁₂drain electrode respectively with NMOS tube M ₂₀₅with NMOS tube M ₂₀₉grid be connected, its source electrode is connected to the ground, and its grid is connected with the output of the 3rd inverter (201); 3rd inverter (201) input and under-voltage control signal V _uVLObe connected.

6. a kind of Boost type dc-dc synchronizing power pipe current-limiting circuit according to claim 1, it is characterized in that: described electric current and voltage detection unit, comprise the first inverter (101), the second inverter (102), current source I _s1, the first resistance R ₁, the second resistance R ₂, the 3rd resistance R ₃, the 4th resistance R ₄, the 5th resistance R ₅, the first diode D ₁, the second diode D ₂, the first electric capacity C ₁, power mirror is as PMOS M ₁₁₅, PMOS M ₁₀₁, PMOS M ₁₀₃, PMOS M ₁₀₅, PMOS M ₁₁₁, PMOS M ₁₁₃, PMOS M ₁₁₆, PMOS M ₁₁₇, PMOS M ₁₁₈, NMOS tube M ₁₀₂, NMOS tube M ₁₀₄, NMOS tube M ₁₀₆, NMOS tube M ₁₀₇, NMOS tube M ₁₀₈, NMOS tube M ₁₀₉, NMOS tube M ₁₁₀, NMOS tube M ₁₁₂with NMOS tube M ₁₁₄; Wherein:

Described current source I _s1input termination internal electric source V _dD, its output is connected on NMOS tube M ₁₀₇drain and gate on;

Described NMOS tube M ₁₀₂, M ₁₀₄, M ₁₀₆, M ₁₀₇and M ₁₁₀structure current mirror in a row, and their source electrode all ground connection, wherein NMOS tube M ₁₀₂, M ₁₀₄, M ₁₀₆and M ₁₁₀grid be all connected to NMOS tube M ₁₀₇grid on;

Described NMOS tube M ₁₁₀drain electrode be connected on composition differential pair NMOS tube M ₁₀₈and M ₁₀₉source electrode on; Wherein NMOS tube M ₁₀₈drain electrode be connected on PMOS M ₁₁₃source electrode on; NMOS tube M ₁₀₉drain electrode be connected on PMOS M ₁₁₁source electrode on; NMOS tube M ₁₁₂drain electrode be connected on NMOS tube M respectively ₁₁₂with NMOS tube M ₁₁₄grid on, simultaneously with PMOS M ₁₁₁drain electrode connects; NMOS tube M ₁₁₄drain electrode be connected on PMOS M ₁₁₃drain electrode and PMOS M ₁₁₆grid on; Wherein PMOS M ₁₁₁with PMOS M ₁₁₃grid and input voltage V _b1be connected; NMOS tube M ₁₁₂with NMOS tube M ₁₁₄source ground;

Described NMOS tube M ₁₀₉and M ₁₀₈form differential pair, their drain electrode is respectively by the 3rd resistance R ₃with the 4th resistance R ₄be connected on node voltage V _sWon, their grid then receives output voltage V respectively _oUTwith power mirror as PMOS M ₁₁₅drain electrode on;

Described PMOS M ₁₀₁source electrode and the first resistance R ₁be connected, the first resistance R ₁the other end and node voltage V _sWbe connected, PMOS M ₁₀₁grid and drain electrode all with NMOS tube M ₁₀₂drain electrode and input voltage V _b1be connected;

Described power mirror is as PMOS M ₁₁₅, itself and synchronizing power pipe Q ₁composition mirror image, its source electrode and node voltage V _sWbe connected, its grid and grid control signal V _gATEbe connected, its substrate and underlayer voltage V _bODYbe connected, its drain electrode and PMOS M ₁₁₆source electrode is connected, and power mirror is as PMOS M ₁₁₅source electrode connect the first diode D ₁positive pole, the first diode D ₁negative pole connects its substrate, its drain electrode connection second diode D ₂positive pole, the second diode D ₂negative pole connects its substrate; Wherein PMOS M ₁₁₆drain electrode respectively with the 5th resistance R ₅with current sampling signal V _iSbe connected; 5th resistance R ₅the other end be connected to the ground;

Described PMOS M ₁₀₃grid and drain electrode all with PMOS M ₁₀₅grid be connected; PMOS M ₁₀₃source electrode and the second resistance R ₂be connected, its drain electrode and NMOS tube M ₁₀₄drain electrode be connected; Second resistance R ₂the other end and input voltage V _iNbe connected; PMOS M ₁₀₅source electrode and output voltage V _oUTbe connected, its drain electrode respectively with NMOS tube M ₁₀₆drain electrode and under-voltage control signal V _uVLObe connected;

Described second inverter (102) input and NMOS tube M ₁₀₆drain electrode be connected, its output respectively with PMOS M ₁₁₈grid, the first inverter (101) input and under-voltage control signal V _uVLObe connected; The output of the first inverter (101) and PMOS M ₁₁₇grid be connected; PMOS M ₁₁₈drain electrode and output voltage V _oUTbe connected, its substrate and source electrode all with PMOS M ₁₁₇substrate be connected with source electrode, and be connected to internal electric source V _dDon; First electric capacity C ₁one end connect internal electric source V _dD, other end ground connection; PMOS M ₁₁₇drain electrode and input voltage V _iNbe connected.