CN201805600U - A LED driver primary side constant current control device - Google Patents
A LED driver primary side constant current control device Download PDFInfo
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Abstract
本实用新型公开了一种LED驱动器原边恒流控制装置。现有的恒流控制装置易出现光耦老化问题且电路较为复杂。本实用新型中的峰值采样保持模块的输出端接副边电流模拟模块的输入端,副边电流模拟模块的输出端接平均电流环的输入端,平均电流环的输出端接比较模块的一个输入端,比较模块的另一个输入端接锯齿波产生模块的输出端,比较模块的输出端接驱动脉冲产生模块的一个输入端,驱动脉冲产生模块的另一个输入端接电感电流过零检测模块的输出端,驱动脉冲产生模块的输出端接驱动模块。本实用新型可实现高功率因数和输出恒流控制。
The utility model discloses a constant current control device for the primary side of an LED driver. The existing constant current control device is prone to the problem of optocoupler aging and the circuit is relatively complicated. The output terminal of the peak sampling and holding module in the utility model is connected to the input terminal of the secondary current simulation module, the output terminal of the secondary current simulation module is connected to the input terminal of the average current loop, and the output terminal of the average current loop is connected to an input of the comparison module terminal, the other input terminal of the comparison module is connected to the output terminal of the sawtooth wave generation module, the output terminal of the comparison module is connected to one input terminal of the drive pulse generation module, and the other input terminal of the drive pulse generation module is connected to the inductor current zero-crossing detection module The output terminal, the output terminal of the driving pulse generating module is connected to the driving module. The utility model can realize high power factor and output constant current control.
Description
技术领域technical field
本实用新型属于开关电源技术领域,涉及一种LED驱动器原边恒流控制装置。The utility model belongs to the technical field of switching power supplies and relates to a primary side constant current control device of an LED driver.
背景技术Background technique
目前大功率的LED驱动器通常需满足以下几项要求:输出恒流、高功率因数和电气隔离。其中输出恒流是LED自身特点所决定,高功率因数是为了降低驱动器对公用电网的污染,而电气隔离是出于安全考虑。电气隔离通常采用高频变压器实现,为了实现输出恒流控制,通常的做法是要采集输出电流信号,然后通过光耦元件传到原边控制电路。副边电流采样电路和光耦的存在,增加了电路的复杂性,进一步,由于光耦存在老化问题,使电路的稳定性和使用寿命都受到一定影响。Current high-power LED drivers usually need to meet the following requirements: output constant current, high power factor and electrical isolation. Among them, the output constant current is determined by the characteristics of the LED itself, the high power factor is to reduce the pollution of the driver to the public grid, and the electrical isolation is for safety considerations. Electrical isolation is usually achieved by using a high-frequency transformer. In order to achieve output constant current control, the usual practice is to collect the output current signal, and then transmit it to the primary side control circuit through the optocoupler. The existence of the secondary current sampling circuit and the optocoupler increases the complexity of the circuit. Furthermore, due to the aging problem of the optocoupler, the stability and service life of the circuit are affected to a certain extent.
一种解决方案是采用原边恒流控制,即无需副边电流采样和光耦元件,直接通过在隔离变压器的原边得到输出电流的信息或者采用恒功率控制,以实现输出恒流。此外为了满足高功率因数的要求,控制电路还需能实现功率因数校正功能。目前已有能实现原边恒流控制和高功率因数要求的控制芯片主要有PI的LNK-PH系列和Infineon的ICL8001G,这两种芯片基本上能满足原边恒流控制和高功率因数要求,但是性能未必最优。One solution is to use primary side constant current control, that is, without secondary side current sampling and optocoupler components, directly obtain output current information on the primary side of the isolation transformer or use constant power control to achieve output constant current. In addition, in order to meet the requirements of high power factor, the control circuit also needs to be able to realize the power factor correction function. At present, there are control chips that can realize primary-side constant current control and high power factor requirements, mainly including PI's LNK-PH series and Infineon's ICL8001G. These two chips can basically meet the primary-side constant current control and high power factor requirements. But performance may not be optimal.
因此,研究结构简单、高性能的隔离型高功率因数反激式LED驱动器的原边恒流控制装置是一项非常具有实际应用价值的工作。Therefore, it is a very practical work to study the primary side constant current control device of the isolated high power factor flyback LED driver with simple structure and high performance.
发明内容Contents of the invention
本实用新型的目的是针对现有技术的不足,提供了一种LED驱动器原边恒流控制装置,该装置无需乘法器,结构非常简单。The purpose of the utility model is to provide a constant current control device for the primary side of an LED driver, which does not need a multiplier and has a very simple structure, aiming at the shortcomings of the prior art.
本实用新型解决技术问题所采取的技术方案为:The technical scheme that the utility model solves the technical problem that takes is:
本实用新型包括峰值采样保持模块、副边电流模拟模块、平均电流环、锯齿波产生模块、比较模块、电感电流过零检测模块、驱动脉冲产生模块、驱动模块。The utility model comprises a peak sampling and holding module, a secondary side current simulation module, an average current loop, a sawtooth wave generation module, a comparison module, an inductor current zero-crossing detection module, a driving pulse generation module and a driving module.
峰值采样保持模块的输出端接副边电流模拟模块的输入端,副边电流模拟模块的输出端接平均电流环的输入端,平均电流环的输出端接比较模块的一个输入端,比较模块的另一个输入端接锯齿波产生模块的输出端,比较模块的输出端接驱动脉冲产生模块的一个输入端,驱动脉冲产生模块的另一个输入端接电感电流过零检测模块的输出端,驱动脉冲产生模块的输出端接驱动模块。The output terminal of the peak sample and hold module is connected to the input terminal of the secondary current analog module, the output terminal of the secondary current analog module is connected to the input terminal of the average current loop, the output terminal of the average current loop is connected to an input terminal of the comparison module, and the output terminal of the comparison module is The other input terminal is connected to the output terminal of the sawtooth wave generating module, the output terminal of the comparison module is connected to one input terminal of the driving pulse generating module, the other input terminal of the driving pulse generating module is connected to the output terminal of the inductor current zero-crossing detection module, and the driving pulse The output terminal of the generating module is connected to the driving module.
所述的副边电流模拟模块可以采用以下六种技术方案实现The secondary side current analog module can be implemented using the following six technical solutions
方案一:副边电流模拟模块包括电阻R11和开关S11;电阻R11的一端接峰值采样保持模块的输出端,电阻R11的另一端接开关S11的一端并作为副边电流模拟模块的输出端,开关S11的另一端接地,开关S11的控制端接驱动产生模块的正相输出端Q。Option 1: The secondary current simulation module includes a resistor R 11 and a switch S 11 ; one end of the resistor R 11 is connected to the output terminal of the peak sampling and holding module, and the other end of the resistor R 11 is connected to one end of the switch S 11 as a secondary current simulation module The output terminal of the switch S 11 is grounded, and the control terminal of the switch S 11 is connected to the positive phase output terminal Q of the drive generation module.
方案二:副边电流模拟模块包括电阻R11、开关S11和反相器U11,电阻R11的一端接峰值采样保持模块的输出端,电阻R11的另一端接开关S11的一端并作为副边电流模拟模块的输出端,开关S11的另一端接地,开关S11的控制端接反相器U11的输出端,反相器U11的输入端接驱动脉冲产生模块的反相输出端 Scheme 2: The secondary current simulation module includes a resistor R 11 , a switch S 11 and an inverter U 11 , one end of the resistor R 11 is connected to the output end of the peak sampling and holding module, the other end of the resistor R 11 is connected to one end of the switch S 11 and As the output terminal of the secondary current simulation module, the other end of the switch S11 is grounded, the control terminal of the switch S11 is connected to the output terminal of the inverter U11, and the input terminal of the inverter U11 is connected to the inverting phase of the driving pulse generation module output
方案三:副边电流模拟模块包括开关S44、开关S55和反相器U22,开关S55的一端接峰值采样保持电路的输出端,开关S55的另一端与开关S44的一端相连后作为副边电流模拟模块电路的输出端,开关S44的另一端接地,开关S44控制端接驱动脉冲产生模块的正相输出端Q,S55的控制信号由驱动脉冲产生模块的正相输出端Q经反相器U22反相之后得到。Scheme 3: The secondary side current simulation module includes a switch S 44 , a switch S 55 and an inverter U 22 , one end of the switch S 55 is connected to the output end of the peak sampling and holding circuit, and the other end of the switch S 55 is connected to one end of the switch S 44 Finally, as the output terminal of the secondary current analog module circuit, the other end of the switch S44 is grounded, the control terminal of the switch S44 is connected to the positive phase output terminal Q of the drive pulse generation module, and the control signal of S55 is determined by the positive phase output terminal Q of the drive pulse generation module. The output terminal Q is obtained after being inverted by the inverter U22 .
方案四:副边电流模拟模块包括开关S44和开关S55,开关S55的一端接峰值采样保持电路的输出端,开关S55的另一端与开关S44的一端相连后作为副边电流模拟模块电路的输出端,开关S44的另一端接地,开关S44控制端接驱动脉冲产生模块的正相输出端Q,开关S55的控制端接驱动脉冲产生模块的反相输出端 Solution 4: The secondary current simulation module includes a switch S44 and a switch S55 , one end of the switch S55 is connected to the output end of the peak sampling and holding circuit, and the other end of the switch S55 is connected to one end of the switch S44 as a secondary current simulation The output terminal of the module circuit, the other end of the switch S44 is grounded, the control terminal of the switch S44 is connected to the positive phase output terminal Q of the drive pulse generation module, and the control terminal of the switch S55 is connected to the inverting output terminal of the drive pulse generation module
方案五:副边电流模拟模块包括开关S66和电阻R66,开关S66的一端接峰值采样保持电路的输出端,开关S66的另一端与接电阻R66的一端后作为副边电流模拟模块电路的输出端,电阻R66的另一端接地,开关S66的控制端直接接驱动脉冲产生模块的反相输出端 Scheme 5: The secondary current simulation module includes a switch S 66 and a resistor R 66 , one end of the switch S 66 is connected to the output terminal of the peak sampling and holding circuit, and the other end of the switch S 66 is connected to one end of the resistor R 66 as a secondary current simulation The output end of the module circuit, the other end of the resistor R 66 is grounded, and the control end of the switch S 66 is directly connected to the inverting output end of the drive pulse generation module
方案六:副边电流模拟模块包括开关S66、电阻R66和反相器U33,开关S66的一端接峰值采样保持电路的输出端,开关S66的另一端与接电阻R66的一端后作为副边电流模拟模块电路的输出端,电阻R66的另一端接地,开关S66的控制信号由驱动脉冲产生模块的正相输出端Q经反相器U33反相之后得到。Scheme 6: The secondary side current simulation module includes a switch S 66 , a resistor R 66 and an inverter U 33 , one end of the switch S 66 is connected to the output end of the peak sampling and holding circuit, the other end of the switch S 66 is connected to one end of the resistor R 66 Finally, as the output terminal of the secondary current analog module circuit, the other end of the resistor R 66 is grounded, and the control signal of the switch S 66 is obtained by inverting the positive phase output terminal Q of the driving pulse generation module through the inverter U 33 .
所述的平均电流环包括输入电阻R22、补偿网络、电压基准Vref和运算放大器,副边电流模拟模块的输出经电阻R22接到平均电流环中的运算放大器的负端输入,运算放大器正端输入接电压基准Vref,补偿网络的一端与运算放大器负端输入连接,补偿网络的另一端与运算放大器输出端连接。The average current loop includes an input resistor R22 , a compensation network, a voltage reference Vref and an operational amplifier, the output of the secondary current analog module is connected to the negative terminal input of the operational amplifier in the average current loop through the resistor R22 , and the positive input of the operational amplifier is The terminal input is connected to the voltage reference Vref, one end of the compensation network is connected to the negative input of the operational amplifier, and the other end of the compensation network is connected to the output terminal of the operational amplifier.
所述的电压基准Vref可以采取以下三种技术方案:The voltage reference Vref can adopt the following three technical solutions:
方案一:电压基准Vref采用直流电压源。Solution 1: The voltage reference Vref adopts a DC voltage source.
方案二:电压基准Vref包括除法器、电阻Ra1、电阻Ra2、电阻Ra3、电阻Ra4和电容Ca1;Ra1一端接反激式LED驱动器输入整流器B1的高电平输出端,另一端与电阻Ra3和电容Ca1并联支路的一端相连后接到除法器的除数端B,电阻Ra3和电容Ca1并联的另一端接地,电阻Ra2的一端、电阻Ra4的一端与除法器的被除数端A连接,电阻Ra2的另一端接反激式LED驱动器输入整流器B1的高电平输出端,电阻Ra4的另一端接地,除法器的输出作为电压基准Vref的输出,为幅值恒定、与输入整流器B1的输出同频同相的正弦半波信号。Scheme 2: The voltage reference Vref includes a divider, a resistor R a1 , a resistor R a2 , a resistor R a3 , a resistor R a4 and a capacitor C a1 ; one end of R a1 is connected to the high-level output end of the flyback LED driver input rectifier B 1 , The other end is connected to one end of the parallel branch of the resistor R a3 and the capacitor C a1 , and then connected to the divisor terminal B of the divider, the other end of the parallel connection of the resistor R a3 and the capacitor C a1 is grounded, one end of the resistor R a2 , one end of the resistor R a4 Connect with the dividend end A of the divider, the other end of the resistor R a2 is connected to the high level output end of the flyback LED driver input rectifier B1 , the other end of the resistor R a4 is grounded, and the output of the divider is used as the output of the voltage reference Vref , which is a sine half-wave signal with constant amplitude and the same frequency and phase as the output of the input rectifier B1 .
方案三:电压基准Vref包括除法器、三极管Qb1、电阻Rb1、电阻Rb2、电阻Rb3、电容Cb1、第一镜像电流源和第二镜像电流源;电阻Rb1一端接反激式LED驱动器输入整流器B1的高电平输出端,电阻Rb1另一端接三极管Qb1的集电极和基极,三极管Qb1的发射极接地;三极管Qb1的集电极和基极分别接第一镜像电流源和第二镜像电流源的输入端,第一镜像电流源的输出端与电阻Rb2的一端、电容Cb1的一端、除法器的除数端B连接,电阻Rb2的另一端与电容Cb1的另一端接地;第二镜像电流源的输出端与电阻Rb3的一端、除法器的被除数端A连接;电阻Rb3的另一端接地,除法器的输出作为电压基准Vref的输出,为幅值恒定、与输入整流器B1的输出同频同相的正弦半波信号。Scheme 3: The voltage reference Vref includes a divider, a transistor Q b1 , a resistor R b1 , a resistor R b2 , a resistor R b3 , a capacitor C b1 , a first mirror current source and a second mirror current source; one end of the resistor R b1 is connected to a flyback type The LED driver is input to the high-level output terminal of the rectifier B1 , the other end of the resistor R b1 is connected to the collector and base of the transistor Q b1 , and the emitter of the transistor Q b1 is grounded; the collector and base of the transistor Q b1 are respectively connected to the first The input terminals of the mirror current source and the second mirror current source, the output terminal of the first mirror current source are connected with one end of the resistor R b2 , one end of the capacitor C b1 , and the divisor terminal B of the divider, and the other end of the resistor R b2 is connected with the capacitor The other end of C b1 is grounded; the output end of the second mirror current source is connected to one end of the resistor R b3 and the dividend end A of the divider; the other end of the resistor R b3 is grounded, and the output of the divider is used as the output of the voltage reference Vref, which is A sine half-wave signal with constant amplitude and the same frequency and phase as the output of the input rectifier B1 .
所述的锯齿波产生模块包括直流电压源VDD、直流电流源IDC、电容C33和开关S33;直流电流源IDC的输入端与直流电压源VDD连接,输出端接电容C33的一端和开关S33的一端,并作为锯齿波产生模块的输出端;电容C33的另一端和开关S33的另一端相连之后接地,开关S33的控制端接驱动产生模块的反相输出端 The sawtooth wave generation module includes a DC voltage source V DD , a DC current source I DC , a capacitor C 33 and a switch S 33 ; the input terminal of the DC current source I DC is connected to the DC voltage source V DD , and the output terminal is connected to the capacitor C 33 One end of the capacitor C33 and one end of the switch S33 are used as the output end of the sawtooth wave generation module; the other end of the capacitor C33 is connected to the other end of the switch S33 and then grounded, and the control end of the switch S33 is connected to the inverting output of the drive generation module end
所述的比较模块包括第一比较器U1,第一比较器U1的负端输入接平均电流环的输出端,第一比较器U1的正端输入接锯齿波产生模块的输出。The comparison module includes a first comparator U 1 , the negative terminal input of the first comparator U 1 is connected to the output terminal of the average current loop, and the positive terminal input of the first comparator U 1 is connected to the output of the sawtooth wave generating module.
所述的电感电流过零检测模块包括第二比较器U2和延时模块,第二比较器U2的负端输入接反激式LED驱动器变压器的辅助绕组异名端,U2的正端输入接地;延时模块的一端与第二比较器U2的输出端连接,延时模块的另一端作为电感电流过零检测模块的输出端。The inductance current zero-crossing detection module includes a second comparator U2 and a delay module, the negative terminal input of the second comparator U2 is connected to the opposite end of the auxiliary winding of the flyback LED driver transformer, and the positive terminal of U2 The input is grounded; one end of the delay module is connected to the output end of the second comparator U 2 , and the other end of the delay module is used as the output end of the inductor current zero-crossing detection module.
所述的驱动脉冲产生模块采用RS触发器,RS触发器的R脚接比较模块的输出端,RS触发器的S脚接电感电流过零检测模块的输出端。驱动脉冲产生模块的输出经驱动模块送到反激式LED驱动器原边开关管Q1的门极,驱动脉冲产生模块的输出同时作为副边电流模拟模块中的开关的控制信号。The drive pulse generation module uses an RS flip-flop, the R pin of the RS flip-flop is connected to the output end of the comparison module, and the S pin of the RS flip-flop is connected to the output end of the inductor current zero-crossing detection module. The output of the driving pulse generating module is sent to the gate of the flyback LED driver primary switch Q1 through the driving module, and the output of the driving pulse generating module is also used as the control signal of the switch in the secondary current analog module.
本实用新型作为隔离型反激式LED驱动器的控制装置,与反激式LED驱动器的主电路共同构成开关电源。传统的单管反激式LED驱动器的主电路包括输入整流器、输入电容、吸收网络、变压器、原边开关管、原边电流采样网络、输出整流器和输出电容。其中输入电容为一容量非常小的电容,主要起到滤波作用,对输入整流器输出的正弦半波波形基本没有影响。本实用新型的反激式LED驱动器的主电路也可以为传统单管反激式拓扑其它的变结构拓扑,如双管反激式变换器等。The utility model is used as a control device of an isolated flyback LED driver, and together with a main circuit of the flyback LED driver, the utility model constitutes a switching power supply. The main circuit of a traditional single-tube flyback LED driver includes an input rectifier, an input capacitor, a snubber network, a transformer, a primary switching tube, a primary current sampling network, an output rectifier, and an output capacitor. The input capacitor is a capacitor with a very small capacity, which mainly plays a filtering role and basically has no effect on the half-sine wave waveform output by the input rectifier. The main circuit of the flyback LED driver of the present utility model can also be a traditional single-tube flyback topology and other variable structure topologies, such as a double-tube flyback converter.
所述的峰值采样保持模块与反激式LED驱动器主电路的原边电流采样网络相连,在每个开关周期对原边电流采样信号进行峰值采样保持,提取原边电流采样信号峰值。The peak sampling and holding module is connected with the primary current sampling network of the main circuit of the flyback LED driver, performs peak sampling and holding on the primary current sampling signal in each switching cycle, and extracts the peak value of the primary current sampling signal.
所述的副边电流模拟模块接到峰值采样保持模块之后,用来模拟副边输出整流器电流。输出整流器电流波形的包络线为正弦半波,具体到单个开关周期,副边输出整流器电流波形为斜率线性下降的直角三角形。副边电流模拟模块的单个开关周期的输出波形是一矩形波,宽度等于原边开关管关断时间(约等于副边输出整流器导通时间),幅值等于原边电流采样信号单个开关周期的峰值电压,因此面积与副边输出整流器电流波形面积的两倍成比例。After the secondary current simulation module is connected to the peak sample and hold module, it is used to simulate the secondary output rectifier current. The envelope of the current waveform of the output rectifier is a half-sine wave, specific to a single switching cycle, and the current waveform of the output rectifier on the secondary side is a right-angled triangle with a linearly decreasing slope. The output waveform of a single switching period of the secondary side current analog module is a rectangular wave, the width is equal to the turn-off time of the primary side switch tube (approximately equal to the conduction time of the secondary side output rectifier), and the amplitude is equal to the single switching period of the primary side current sampling signal peak voltage, so the area is proportional to twice the area of the secondary output rectifier current waveform.
所述的平均电流环对副边电流模拟模块的输出信号平均值与所述的电压基准进行比较并对二者之间误差加以放大。The average current loop compares the average value of the output signal of the secondary current analog module with the voltage reference and amplifies the error between the two.
所述锯齿波产生模块在反激式LED驱动器原边开关管导通期间产生锯齿波;在原边开关管关断期间,锯齿波产生模块输出低电平。The sawtooth wave generation module generates a sawtooth wave when the primary switch of the flyback LED driver is turned on; and the sawtooth wave generation module outputs a low level when the primary switch is turned off.
所述的比较模块的输入分别为锯齿波产生模块的输出信号和平均电流环的输出信号。比较模块对锯齿波产生模块的输出信号和平均电流环的输出信号进行比较,当锯齿波产生模块的输出信号上升到与平均电流环的输出信号相等时,比较模块输出从低电平翻转为高电平。The input of the comparison module is the output signal of the sawtooth wave generation module and the output signal of the average current loop respectively. The comparison module compares the output signal of the sawtooth wave generation module with the output signal of the average current loop. When the output signal of the sawtooth wave generation module rises to be equal to the output signal of the average current loop, the output of the comparison module turns from low to high. level.
所述的电感电流过零检测模块检测反激式LED驱动器的变压器辅助绕组电压信号,间接检测出变压器激磁电感电流过零点。当变压器辅助绕组电压信号降到零时,电感电流过零检测模块输出高电平。The inductance current zero-crossing detection module detects the transformer auxiliary winding voltage signal of the flyback LED driver, and indirectly detects the zero-crossing point of the excitation inductance current of the transformer. When the transformer auxiliary winding voltage signal drops to zero, the inductor current zero-crossing detection module outputs a high level.
所述的驱动脉冲产生模块根据比较模块和电感电流过零检测模块的输出电平信号产生脉冲信号:当比较模块产生一个低电平到高电平的翻转时,驱动脉冲产生模块的脉冲信号由高电平复位到低电平;当电感电流过零检测模块产生一个低电平到高电平的翻转时,驱动脉冲产生模块的脉冲信号由低电平置位到高电平;周而复始,产生脉冲序列。The drive pulse generation module generates a pulse signal according to the output level signals of the comparison module and the inductance current zero-crossing detection module: when the comparison module generates a low-level to high-level reversal, the pulse signal of the drive pulse generation module is generated by Reset from high level to low level; when the inductance current zero-crossing detection module generates a low level to high level inversion, the pulse signal of the driving pulse generation module is set from low level to high level; pulse train.
所述的驱动模块用来增强所述驱动脉冲产生模块的驱动能力。The driving module is used to enhance the driving capability of the driving pulse generating module.
其中,所述的反激式LED驱动器工作在临界断续模式(BCM)。Wherein, the flyback LED driver works in Boundary Discontinuous Mode (BCM).
其中,所述的副边电流模拟模块可以采用所述的六种技术方案中的其中任意一种。Wherein, the secondary current simulation module may adopt any one of the six technical solutions.
其中,平均电流环的电压基准,可以是方案一所述的直流电压基准,也可以是由所述的方案二或方案三产生的与反激式LED驱动器输入整流桥的输出电压同频同相、幅值固定的正弦半波电压基准。Wherein, the voltage reference of the average current loop can be the DC voltage reference described in
其中,所述的平均电流环的运算放大器可以是电压型或电流型(跨导型)。Wherein, the operational amplifier of the average current loop can be a voltage type or a current type (transconductance type).
进一步,所述平均电流环的补偿网络可以为纯积分环节,也可以为比例积分环节,或者比例积分微分环节,属于公知技术。Further, the compensation network of the average current loop may be a pure integral link, or a proportional integral link, or a proportional integral differential link, which belongs to the known technology.
其中,所述驱动模块可以是两个双极晶体管或金属氧化物半导体场效应管构成的推挽结构(图腾柱结构),属于公知技术。Wherein, the driving module may be a push-pull structure (totem pole structure) composed of two bipolar transistors or metal oxide semiconductor field effect transistors, which belongs to the known technology.
其中,所述的开关可以是单个双极晶体管、金属氧化物半导体场效应管或由多个双极晶体管或金属氧化物半导体场效应管实现的组合开关。Wherein, the switch may be a single bipolar transistor, metal oxide semiconductor field effect transistor or a combined switch realized by multiple bipolar transistors or metal oxide semiconductor field effect transistors.
基于以上阐述,本实用新型的核心思想在于:通过电感电流过零检测模块检测反激式LED驱动器变压器电感电流过零点,并在变压器电感电流过零时开通原边开关管,从而使反激式LED驱动器工作在电流临界断续模式(BCM);通过所述的峰值采样保持模块对原边电流采样信号进行峰值采样和保持,获取原边电流采样信号的峰值包络线;获取原边电流采样信号的峰值包络线之后,通过所述的副边电流模拟模块,模拟出面积与副边二极管电流两倍面积成比例的信号;将副边电流模拟模块的输出信号送到平均电流环中,利用平均电流环自身具有平均值滤波功能,在平均电流环的输入端得到与输出电流平均值成比例的正弦半波信号,通过与电压基准进行比较,将二者的误差信号经过平均电流环的补偿网络进行放大,得到一误差放大的直流信号;通过锯齿波产生模块产生的锯齿波与平均电流环输出的直流信号进行比较,获得原边开关管的关断触发信号,由于锯齿波斜率固定,从而使整个工频周期内原边开关管导通时间为恒定值;当输入整流器输出的正弦半波电压作用在原边变压器两端的时间恒定时,原边电流采样信号峰值包络线为正弦半波,从而实现反激式LED驱动器的高功率因数;当输出电流发生波动,使得平均电流环的输出直流信号幅值变化,从而改变原边开关管导通时间,使得输出电流平均值趋于稳定,实现输出恒流。输出电流的恒流值可以通过改变原边电流采样系数或者改变平均电流环中的电压基准实现。Based on the above description, the core idea of the present invention is to detect the zero-crossing point of the inductance current of the flyback LED driver transformer through the inductance current zero-crossing detection module, and turn on the primary switch tube when the transformer inductance current crosses zero, so that the flyback The LED driver works in current critical discontinuous mode (BCM); the peak value sampling and holding of the primary current sampling signal is carried out by the peak sampling and holding module to obtain the peak envelope of the primary current sampling signal; obtain the primary current sampling After the peak envelope of the signal, through the secondary current simulation module, a signal whose area is proportional to twice the area of the secondary diode current is simulated; the output signal of the secondary current simulation module is sent to the average current loop, Utilizing the average value filter function of the average current loop itself, a sine half-wave signal proportional to the average value of the output current is obtained at the input end of the average current loop, and compared with the voltage reference, the error signal of the two is passed through the average current loop The compensation network is amplified to obtain an error-amplified DC signal; the sawtooth wave generated by the sawtooth wave generation module is compared with the DC signal output by the average current loop to obtain the turn-off trigger signal of the primary switch tube. Since the slope of the sawtooth wave is fixed, In this way, the conduction time of the primary side switch tube is a constant value in the entire power frequency cycle; when the sinusoidal half-wave voltage output by the input rectifier acts on both ends of the primary side transformer for a constant time, the peak envelope of the primary side current sampling signal is a sine half wave, In this way, the high power factor of the flyback LED driver is realized; when the output current fluctuates, the amplitude of the output DC signal of the average current loop changes, thereby changing the conduction time of the primary switch tube, making the average value of the output current tend to be stable, and realizing output constant current. The constant current value of the output current can be realized by changing the sampling coefficient of the primary current or changing the voltage reference in the average current loop.
本实用新型的有益效果在于:本实用新型提出的恒导通时间的隔离型高功率因数反激式LED驱动器的原边恒流控制装置,无需光耦和副边反馈电路,即可实现高功率因数和输出恒流控制。与同类型高功率因数原边恒流控制电路相比,省去了乘法器,结构更加简单;进一步,原边核心控制电路可以集成为单芯片。The beneficial effect of the utility model is that: the primary side constant current control device of the isolated high power factor flyback LED driver with constant conduction time proposed by the utility model can realize high power without optocoupler and secondary side feedback circuit. factor and output constant current control. Compared with the same type of high power factor primary side constant current control circuit, the multiplier is omitted, and the structure is simpler; further, the primary side core control circuit can be integrated into a single chip.
附图说明Description of drawings
图1为本实用新型与反激式LED驱动器的主电路连接示意图;Fig. 1 is the schematic diagram of the main circuit connection of the utility model and the flyback LED driver;
图2为本实用新型的第一具体实施例示意图;Fig. 2 is the schematic diagram of the first specific embodiment of the utility model;
图3为本实用新型工作原理波形分析图;Fig. 3 is the waveform analysis diagram of the working principle of the present utility model;
图4为本实用新型中副边电流模拟模块的六种具体实现方案;Fig. 4 is six kinds of specific implementation schemes of the secondary side current simulation module in the utility model;
图5为本实用新型的第二具体实施例示意图;Fig. 5 is the schematic diagram of the second specific embodiment of the present utility model;
图6为本实用新型的第三具体实施例示意图;Fig. 6 is the schematic diagram of the third specific embodiment of the present utility model;
图7为本实用新型与非隔离的升降压电路的主电路连接示意图。FIG. 7 is a schematic diagram of the connection between the utility model and the main circuit of the non-isolated buck-boost circuit.
具体实施方式Detailed ways
以下结合本实用新型框图以及具体实施例示意图本实用新型内容进行详细说明。The content of the utility model will be described in detail below in conjunction with the block diagram of the utility model and the schematic diagram of specific embodiments.
参照图1,一种LED驱动器原边恒流控制装置包括:峰值采样保持模块100、副边电流模拟模块200、平均电流环300、锯齿波产生模块400、比较模块500、电感电流过零检测模块600、驱动脉冲产生模块700和驱动模块800。Referring to Fig. 1, a constant current control device for the primary side of an LED driver includes: a peak sampling and holding
峰值采样保持模块100的输出端接副边电流模拟模块200的输入端,副边电流模拟模块200的输出端接平均电流环300的输入端,平均电流环400的输出端接比较模块的一个输入端,比较模块500的另一个输入端接锯齿波产生模块400的输出端,比较模块500的输出端接驱动脉冲产生模块700的一个输入端,驱动脉冲产生模块700的另一个输入端接电感电流过零检测模块600的输出端,驱动脉冲产生模块700的输出端接驱动模块800。The output terminal of the peak sampling and holding
本实用新型的应用对象为反激式LED驱动器的主电路,包括输入整流桥B1、输入电容Cin、变压器T、吸收网络、原边开关管Q1、原边电流采样网络、输出整流器(选用二极管D1)和输出电容C0。The application object of the utility model is the main circuit of the flyback LED driver, including the input rectifier bridge B 1 , the input capacitor C in , the transformer T, the absorption network, the primary switch tube Q 1 , the primary current sampling network, and the output rectifier ( Choose diode D 1 ) and output capacitor C 0 .
参照图2的第一具体实施例示意图:With reference to the schematic diagram of the first specific embodiment of Fig. 2:
峰值采样保持模块100与反激式LED驱动器主电路的原边电流采样网络相连,在每个开关周期对原边电流采样信号进行峰值采样保持,提取原边电流采样信号峰值;其中,峰值采样保持模块具体可选用中国专利(公开号:CN101615432)公开的峰值采样保持电路。The peak sampling and holding
副边电流模拟模块200包括:电阻R11和开关S11;电阻R11的一端接峰值采样保持模块100的输出,电阻R11的另一端接开关S11的一端,二者的连接点作为副边电流模拟模块200的输出,开关S11的另一端接地,开关S11的控制端接驱动产生模块700的正相输出端Q,当控制端电平为高电平,开关S11导通,当当控制端电平为低电平,开关S11关断;副边电流模拟模块200的输出为一方波信号。The secondary side
平均电流环300包括输入电阻R22、补偿网络、电压基准Vref和运算放大器。副边电流模拟模块200的输出经电阻R22接到平均电流环300中的运算放大器的负端输入,运算放大器正端输入接电压基准Vref。由于平均电流环具有开关周期平均值滤波效果,因此平均电流环300的运算放大器负端输入信号为副边电流模拟模块200的输出信号滤除了开关周期纹波之后的平均值。该信号与电压基准Vref进行比较,二者之间误差经补偿网络和运算放大器加以放大之后输出一叠加了两倍交流电网频率的低频纹波和高频开关纹波的直流电平信号。The average
锯齿波产生模块400包括直流电压源VDD、直流电流源IDC、电容C33和开关S33;其中直流电压源VDD和直流电流源IDC可通过公知技术得到;直流电流源IDC的输入端与直流电压源VDD连接,输出端接电容C33的一端和开关S33的一端相连作为锯齿波产生模块400的输出端,电容C33的另一端和开关S33的另一端相连之后接地,开关S33的控制端接驱动产生模块700的反相输出端当控制端电平为高电平,开关S33导通,将电容C33两端电压保持为零;当控制端电平为低电平,开关S33关断,直流电流源IDC给电容C33充电,产生锯齿波信号。The sawtooth
比较模块500包括第一比较器U1,U1的负端输入接平均电流环300的输出,U1的正端输入接锯齿波产生模块400的输出。当锯齿波产生模块400产生的锯齿波信号触及到平均电流环300的输出电平,比较模块500的输出电平从低电平翻转为高电平。由于平均电流环300的输出电平在整个工频周期内基本幅值基本不变,锯齿波产生模块400产生的锯齿波信号斜率也固定,而锯齿波信号的宽度对应着原边开关管Q1的导通时间,因此对于特定的平均电流环300的输出电平幅值,原边开关管Q1的导通时间恒定。当原边开关管Q1的导通时间恒定,原边开关管电流波形包络线跟随反激式LED驱动器输入整流器B1的输出,为与反激式LED驱动器输入整流器B1的输出同频同相的正弦半波。The
电感电流过零检测模块600包括第二比较器U2和延时模块,U2的负端输入接反激式LED驱动器变压器的辅助绕组异名端,U2的正端输入接地;通过检测变压器辅助绕组电压信号过零点,可间接检测出变压器电感电流过零点。当检测到变压器辅助绕组的电压信号过零,第二比较器U2输出高电平。由于反激式LED驱动器变压器辅助绕组电压信号过零点与原边开关管漏源极(或集电极与发射极)之间的谐振电压谷底存在一定时间差,即反激式LED驱动器变压器辅助绕组电压信号过零点要稍微超前原边开关管漏源极之间的谐振电压谷底。通过延时模块,对该时间差进行补偿,可获得原边开关管在漏源极之间的谐振电压谷底开通。The inductor current zero-crossing
进一步,电感电流过零检测模块600中的第二比较器U2的正端输入也可改接一低幅值的直流电压源,减少因地线干扰而造成的误差。Furthermore, the positive terminal input of the second comparator U 2 in the inductor current zero-crossing
驱动脉冲产生模块700采用RS触发器实现,其中R脚接比较模块500的输出,S脚接电感电流过零检测模块600的输出:当比较模块500产生一个低电平到高电平的翻转时,驱动脉冲产生模块800的输出信号由高电平复位到低电平;当电感电流过零检测模块600产生一个低电平到高电平的翻转时,驱动脉冲产生模块700的输出信号由低电平置位到高电平,如此周而复始,产生输出脉冲序列。The driving
驱动脉冲产生模块700的输出经驱动模块800送到反激式LED驱动器原边开关管Q1的门极,驱动脉冲产生模块700的输出同时直接作为副边电流模拟模块200中的开关S11的控制信号。The output of the driving
图3是反激式LED驱动器工作在电流临界断续模式下原副边的关键波形,参考图3对本实用新型工作原理进行详细说明:Fig. 3 is the key waveform of the primary and secondary sides of the flyback LED driver working in the current critical discontinuous mode. Referring to Fig. 3, the working principle of the utility model is described in detail:
图3中,Vcomp是平均电流环300的输出波形,Vsaw是锯齿波产生模块400的输出波形,VGS_Q1和VGS_s11分别是反激式LED驱动器原边开关管Q1的驱动波形和开关S11的控制端波形;ipri是反激式LED驱动器原边开关管电流波形;isec是反激式LED驱动器副边输出整流器电流波形;Vsamp1e是峰值采样保持模块100的输出波形;VDS_S11是开关S11两端的电压波形,即副边电流模拟模块200的输出波形。根据图3可以看到,由于平均电流环300的输出波形Vcomp为直流电平,剧齿波Vsaw斜率一定,因此反激式LED驱动器原边开关管Q1的导通时间恒定,原边开关管电流ipri波形包络线为正弦半波;由于电感电流过零检测模块600使反激式LED驱动器工作在电流临界断续模式,因此副边输出整流器的电流波形isec包络线同样也为正弦半波;峰值采样保持模块100的输出波形Vsamp1e为阶梯波,每个阶梯的幅值对应不同的原边采样电流峰值;副边电流模拟模块200的输出波形VDS_s11为幅值变化的矩形波,幅值对应不同原边电流采样信号的峰值;由图3可知:In Fig. 3, V comp is the output waveform of the average
其中,K1为原边电流采样系数,Ns为变压器副边匝数,Np为变压器原边匝数,为副边电流模拟模块200的输出波形VDS_s11的平均值,为副边输出整流器的电流平均值。从上式可以看出副边电流模拟模块200的输出波形VDS_s11的平均值正比于输出电流平均值Io;因此只要将送入平均电流环300,与设定的基准Vref进行比较,即可间接调节输出平均电流,从而实现输出电流恒流。由于平均电流环自身具有滤波功能,只要将VDS_s11送入平均电流环300,即可在平均电流环300的运算放大器输入端获得VDS_s11的平均值进一步,也可以在副边电流模拟模块200的输出和平均电流环300增加一级滤波电路,但对电路功能基本没有影响。Among them, K 1 is the primary current sampling coefficient, N s is the number of turns of the secondary side of the transformer, N p is the number of turns of the primary side of the transformer, is the average value of the output waveform V DS_s11 of the secondary
平均电流环300基准通常设置为直流电压基准;此外,反激式LED驱动器副边输出整流器电流波形isec进行开关周期滤波之后的波形平均值近似为正弦半波,因此平均电流环300基准也可以设置为与反激式LED驱动器输入整流桥的输出波形同频同相、幅值恒定的正弦半波基准。The average
图4给出了副边电流模拟模块200的若干种具体实现电路,其中图4(a)所示电路结构与图2中副边电流模拟模块200相同;图4(b)所示电路结构与图4(a)所示电路结构相似,也是由电阻R11和开关S11组成,不同之处在于S11的控制信号是由驱动脉冲产生模块的反相输出端经反相器U11反相之后得到;图4(c)中副边电流模拟模块200由开关S44、S55和反相器U22组成,S55的一端接峰值采样保持电路100的输出,S55的另一端与开关S44的一端相连后作为副边电流模拟模块200电路的输出端,开关S44的另一端接地,开关S44控制端接驱动脉冲产生模块的正相输出端Q,S55的控制信号由驱动脉冲产生模块的正相输出端Q经反相器U22反相之后得到;图4(d)中副边电流模拟模块200电路结构与图4(c)中相同,区别在于S55的控制端接驱动脉冲产生模块的反相输出端图4(e)中副边电流模拟模块200由开关S66和电阻R66组成,开关S66的一端接峰值采样保持电路100的输出,开关S66的另一端与接电阻R66的一端后作为副边电流模拟模块200电路的输出端,电阻R66的另一端接地,开关S66的控制端直接接驱动脉冲产生模块的反相输出端图4(f)中副边电流模拟模块200电路结构与图4(e)中相同,区别在于开关S66的控制信号由驱动脉冲产生模块的正相输出端Q经反相器U33反相之后得到。Figure 4 shows several specific implementation circuits of the secondary current simulation module 200, wherein the circuit structure shown in Figure 4(a) is the same as that of the secondary current simulation module 200 in Figure 2; the circuit structure shown in Figure 4(b) is the same as The circuit shown in Figure 4(a) has a similar structure and is also composed of a resistor R 11 and a switch S 11. The difference is that the control signal of S 11 is the inverting output terminal of the drive pulse generation module Obtained after being inverted by the inverter U11 ; the secondary current analog module 200 in Figure 4(c) is composed of switches S44 , S55 and inverter U22 , and one end of S55 is connected to the output of the peak sample-and-hold circuit 100 , the other end of S55 is connected to one end of switch S44 as the output end of the secondary current analog module 200 circuit, the other end of switch S44 is grounded, and the control end of switch S44 is connected to the positive phase output end Q of the drive pulse generation module , the control signal of S55 is obtained by the positive-phase output terminal Q of the driving pulse generating module after being inverted by the inverter U22 ; the circuit structure of the secondary current analog module 200 in Fig. 4(d) is the same as that in Fig. , the difference is that the control terminal of S55 is connected to the inverting output terminal of the driving pulse generation module In Fig. 4 (e), the secondary side
图5是本实用新型的第二具体实施例,主电路以及主要控制部分都与图2所示的实施例相同,与图2的区别是图5中平均电流环300的电压基准Vref采用了幅值恒定的正弦半波基准模块,并给出了一种具体实施方式。参考图5,正弦半波基准模块Vref包括除法器、电阻Ra1、电阻Ra2、电阻Ra3、电阻Ra4和电容Ca1;其中,电阻Ra1一端接反激式LED驱动器输入整流器B1的高电平输出端,另一端与电阻Ra3和电容Ca1并联支路的一端相连后接到除法器的除数端B,电阻Ra3和电容Ca1并联的另一端接地,电阻Ra1、电阻Ra3和电容Ca1构成的电网络对输入整流器B1的正端输出电压分压和滤波,电阻Ra1、电阻Ra3和电容Ca1连接点电压为一叠加了较小低频纹波的直流电压,其平均值与反激式LED驱动器输入交流电压峰值成正比,电阻Ra2一端接输入整流器B1的高电平输出端,另一端与电阻Ra4相连,电阻Ra4另一端接地,除法器的被除数端A接Ra2和Ra4的连接点,在除法器中进行相除(A/B),使得除法器的输出为幅值恒定、与反激式LED驱动器输入整流器的输出同频同相的正弦半波信号。Fig. 5 is the second specific embodiment of the present utility model, and main circuit and main control part are all identical with the embodiment shown in Fig. 2, and the difference with Fig. 2 is that the voltage reference Vref of the average
图6是本实用新型的第三具体实施例主电路,主电路以及主要控制部分都与图5所示的实施例相同,与图5的区别在于图6中平均电流环300的基准Vref采用了另一种方式来产生幅值恒定的正弦半波基准模块;参考图6,正弦半波基准模块Vref包括除法器、三极管Qb1、电阻Rb1、电阻Rb2、电阻Rb3、电容Cb1、镜像电流源I和镜像电流源II;其中电阻Rb1一端接反激式LED驱动器输入整流器B1的高电平输出端,电阻Rb1另一端接三极管Qb1的集电极和基极,三极管Qb1的发射极接地,三极管Qb1的集电极和基极还分别接镜像电流源I和镜像电流源II的输入端,镜像电流源I的输出与电阻Rb2的一端、电容Cb1的一端以及除法器的除数端B相连,电阻Rb2的另一端与电容Cb1的另一端接地,镜像电流源II的输出与电阻Rb3的一端以及除法器的被除数端A相连;三极管Qb1和电阻Rb1用来将反激式LED驱动器输入整流器B1输出的正弦半波电压信号转换为电流信号;镜像电流模块I获取与流经Rb1支路电流成比例的正弦半波电流信号,并经阻容网络Rb2和Cb1获得与反激式LED驱动器输入交流电压幅值成比例的直流电压信号,接到除法器的被除数端B;镜像电流模块II获取与流经Rb1支路电流成比例的正弦半波电流信号,经电阻Rb3转换成电压信号,送入到除法器的除数端A;二者信号在除法器中进行相除(A/B),在除法器输出端产生幅值恒定、与输入整流器输出电压波形同频同相的正弦半波电压基准信号。镜像电流模块可由金属氧化物半导体场效应管或双极晶体管构成,属于公知技术。Fig. 6 is the main circuit of the third specific embodiment of the present utility model, and the main circuit and the main control part are all the same as the embodiment shown in Fig. 5, and the difference with Fig. 5 is that the reference Vref of the average current loop 300 in Fig. 6 adopts Another way to generate a sine half-wave reference module with a constant amplitude; referring to Figure 6, the sine half-wave reference module Vref includes a divider, a transistor Q b1 , a resistor R b1 , a resistor R b2 , a resistor R b3 , a capacitor C b1 , Mirror current source I and mirror current source II; one end of the resistor R b1 is connected to the high-level output end of the flyback LED driver input rectifier B1 , the other end of the resistor R b1 is connected to the collector and base of the transistor Q b1 , and the transistor Q The emitter of b1 is grounded, the collector and base of transistor Q b1 are connected to the input terminals of mirror current source I and mirror current source II respectively, the output of mirror current source I is connected to one end of resistor R b2 , one end of capacitor C b1 and The divisor end B of the divider is connected, the other end of the resistor R b2 is grounded to the other end of the capacitor C b1 , the output of the mirror current source II is connected to one end of the resistor R b3 and the dividend end A of the divider; the transistor Q b1 and the resistor R b1 is used to convert the sinusoidal half-wave voltage signal output by the flyback LED driver input rectifier B1 into a current signal; the mirror current module I obtains a sinusoidal half-wave current signal proportional to the current flowing through the R b1 branch, and passes through the resistor Capacitance network R b2 and C b1 obtain a DC voltage signal proportional to the amplitude of the input AC voltage of the flyback LED driver, which is connected to the dividend terminal B of the divider; mirror current module II obtains a current proportional to the current flowing through the R b1 branch The sinusoidal half-wave current signal is converted into a voltage signal by the resistor R b3 , and sent to the divisor terminal A of the divider; the two signals are divided (A/B) in the divider, and the amplitude is generated at the output terminal of the divider A sinusoidal half-wave voltage reference signal that is constant and has the same frequency and phase as the output voltage waveform of the input rectifier. The current mirror module can be composed of metal oxide semiconductor field effect transistors or bipolar transistors, which belongs to the known technology.
本实用新型可以应用到隔离型输出,也可以应用到非隔离型输出。图7为本实用新型与一种非隔离的升降压(buck-boost)电路的主电路连接示意图;其中,各模块的具体实现可参考图2,图4~图6中所示的具体实施例。The utility model can be applied to isolated output, and can also be applied to non-isolated output. Fig. 7 is a schematic diagram of the main circuit connection between the utility model and a non-isolated buck-boost circuit; wherein, the specific implementation of each module can refer to Fig. 2, and the specific implementation shown in Fig. 4 to Fig. 6 example.
本实用新型包括的具体模块如峰值电流采样保持电路100、副边电流模拟模块200和正弦半波信号基准产生电路等,本领域技术人员可以在不违背其精神的前提下,可以有多种实施方式,或通过各种不同的组合方式,形成不同的具体实施例,这里不再详细描述。The specific modules included in the utility model, such as the peak current sampling and holding
无论上文说明如何详细,还有可以有许多方式实施本实用新型,说明书中所述的只是本实用新型的一个具体实施例子。凡根据本实用新型精神实质所做的等效变换或修饰,都应涵盖在本实用新型的保护范围之内。No matter how detailed the above description is, there are many ways to implement the utility model, and what is described in the description is only a specific implementation example of the utility model. All equivalent transformations or modifications made according to the spirit of the utility model shall fall within the protection scope of the utility model.
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CN103354416A (en) * | 2013-07-14 | 2013-10-16 | 郑儒富 | Average-mode constant current control circuit and control method thereof |
CN103347350A (en) * | 2013-07-29 | 2013-10-09 | 常熟银海集成电路有限公司 | Isolated constant-current LED (light-emitting diode) drive chip of peripheral circuit free of auxiliary winding of transformer |
CN104734477A (en) * | 2013-12-19 | 2015-06-24 | 李永红 | Output current limiting circuit and method |
CN104101764B (en) * | 2014-06-24 | 2017-04-12 | 暨南大学 | Novel inductor current detection circuit applied to DC-DC converter |
CN104242650A (en) * | 2014-09-09 | 2014-12-24 | 滁州市圣宏制造有限公司 | Power supply circuit and power supply |
CN104242650B (en) * | 2014-09-09 | 2017-01-11 | 深圳市昌豪微电子有限公司 | Power supply circuit and power supply |
CN105244848A (en) * | 2015-10-30 | 2016-01-13 | 杰华特微电子(杭州)有限公司 | Overvoltage protection method and circuit |
CN105244848B (en) * | 2015-10-30 | 2019-02-15 | 杰华特微电子(杭州)有限公司 | Over-voltage protection method and circuit |
CN112019002A (en) * | 2020-08-06 | 2020-12-01 | 杭州电子科技大学 | A primary side constant current control device for LLC resonant converter |
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