CN103280963B - A kind of PFC control circuit reducing power tube conducting power consumption - Google Patents

Abstract

The present invention provides a PFC control circuit for reducing the conduction power consumption of the power tube, which is based on the topology of the Boost circuit, including a voltage loop circuit, a power tube drain-source voltage V _DS valley bottom conduction control circuit, and a logic control and drive circuit The voltage loop circuit is used to stabilize the output and generate the shutdown signal of the power tube. The power tube drain-source voltage V _DS valley conduction control circuit is used to detect the drain-source V _DS of the power tube and compare it with the valley-bottom voltage to generate the conduction of the power tube. Through the control signal, the logic control and drive circuit is used to drive and control the turn-on and turn-off of the power tube. By detecting the voltage of V _DS , it is ensured that under different input voltage conditions, the power tube can be turned on when its drain-source voltage V _DS is at the bottom voltage or zero voltage, thereby reducing the loss of the power tube when it is turned on.

Description

A PFC control circuit for reducing conduction power consumption of power transistor

technical field

The invention relates to a single-phase power factor correction circuit in the field of switching power supplies, in particular to a PFC control circuit for reducing the conduction power consumption of a power tube.

Background technique

At present, in the Boost PFC of the critical conduction mode (CRM, Critical Conduction Mode) shown in Figure 1, the traditional zero-current detection conduction scheme, when the power transistor is turned on, the source-drain voltage of the power transistor is relatively large, and the conduction work The consumption is also relatively large, because the frequency of the input AC voltage V _in is relatively small compared to the switching frequency of the power transistor M, so it can be assumed that the magnitude of the input voltage remains unchanged within one switching cycle of the power transistor M. Assuming that the input AC voltage V _in is V _cin through the full-bridge rectifier, when the power transistor M is in the conduction state, the voltage V _{L across the inductor L} is V _cin , and the voltage V _L across the inductor L is equal to the inductor current i The relation of _L is:

$L\frac{{\mathrm{di}}_L}{\mathrm{dt}}=V_L=V_{\mathrm{cin}}$ Formula 1

It can be seen from formula 1 that the inductor current will increase linearly at this time. If the on-time of the power transistor M is T _on , then the increase of the inductor current i _L during the on-time of the power transistor M is △i _l (+) as follows:

${\mathrm{\Δi}}_L(+)=i_{L\left(\mathrm{peak}\right)}=\frac{V_{\mathrm{cin}}}{L}{T}_{\mathrm{on}}$ Formula 2

When the power tube M is in the off state, assuming the off time is T _off and the output voltage of the Boost circuit is V _o , the relationship between the voltage V _L at both ends of the inductor L and the inductor current i _L is:

$L\frac{{\mathrm{di}}_L}{\mathrm{dt}}=V_L=V_{\mathrm{cin}}-V_o$ Formula 3

For the Boost circuit, V _cin -V _o <0, so when the power tube M is turned off, the inductor current i _L will decrease linearly, and the drain-source voltage V _DS of the power tube M is equal to the output voltage V _o . For the traditional PFC control circuit using zero-current detection, when it detects that the inductor current i _L drops to 0, the power tube is turned on, but at the moment of turning on, the drain-source voltage V _DS of the power tube M is equal to the output voltage V _o , so serious conduction power consumption.

In the prior art, in order to reduce conduction power consumption, a method called valley conduction (VS, ValleySwitching) or zero voltage switching (ZVS, ZeroVoltageSwitching) is widely used in the PFC control circuit of the CRM. The main principle is: when it is detected that the inductor current i _L in the Boost circuit structure drops to zero, the power tube M is turned on after a certain time delay, and the inductance L in the Boost circuit structure and the drain-source parasitic capacitance C _d of the power tube will be connected in series Resonance, the drain-source parasitic capacitance C _d of the power tube starts to discharge through the inductor, assuming that after the resonance occurs for a period of time T _d , the voltage V _DS on the drain-source parasitic capacitance C _d of the power tube drops to the bottom value or 0, if it happens to make The delayed turn-on time of the power tube is also equal to T _d , so the valley-bottom conduction or zero-voltage switching is realized, which reduces the conduction power consumption of the power tube.

In the prior art, a typical PFC control circuit for reducing the conduction power consumption of the power transistor is shown in Figure 2. Its working principle is: by adding an RC delay module to the PFC inductor current detection part of the traditional CRM, the power The time for delaying the turn-on of the tube is equal to half of the resonance period, so that the power tube is turned on just when the drain-source voltage V _DS of the power tube drops to the bottom value, and the purpose of reducing the power consumption of the power tube is achieved. The circuit shown in Figure 2 has the following problems: the delayed turn-on time of the power tube is related to the input voltage, and for different input voltages, the inductance in the Boost circuit structure and the parasitic capacitance of the power tube will produce different series resonance situations. Therefore, by adding an RC delay module to achieve valley voltage or zero voltage conduction, it cannot satisfy different input voltages.

In the prior art, another typical PFC control circuit for reducing the on-state power consumption of the power transistor is shown in Figure 3. It uses the detection circuit to determine several important moments during resonance, and then according to the voltage at both ends of the mutual inductance voltage during resonance and The input voltage is center-symmetric, and the moment when the drain-source voltage V _DS of the power tube reaches the valley voltage can be known through circuit calculation. The circuit also adds a delay of the gate drive signal, so that the power tube can be turned on at the bottom of the valley, and the power consumption of the power tube can be reduced. This circuit also cannot meet the conditions of input voltages of different sizes, and the circuit is relatively complicated and difficult to implement.

Contents of the invention

In order to overcome the fact that the prior art realizes V _DS valley voltage or zero voltage conduction (reducing power tube conduction power consumption), it cannot meet the input voltages of different sizes and the circuit structure is complicated and difficult to realize, the present invention provides a method to reduce The PFC control circuit of the power tube conduction power consumption, through the introduction of the power tube drain-source voltage valley bottom conduction control circuit, can reduce the power tube conduction power consumption while meeting different input voltages. The circuit structure is simple and easy to implement. By detecting the voltage of V _DS , it is ensured that the power tube can be turned on when its drain-source voltage V _DS is at the bottom voltage or zero voltage under different input voltage conditions, thereby reducing the power tube conduction. time loss.

The technical scheme that the present invention solves the problems of the technologies described above is as follows:

A PFC control circuit for reducing the conduction power consumption of the power tube, based on the topology of the Boost circuit, including an inductor L, a power tube M, and a diode D, one end of the inductor L is connected to the positive output end of the full-bridge rectifier, and the inductor The other end of L is connected to the drain of power tube M and the anode of diode D, the source of power tube M is connected to the negative output terminal of the full-bridge rectifier, the cathode of diode D is connected to one end of the load, and the other end of the load is connected to the power tube source of M;

It is characterized in that it is provided with a voltage loop circuit for stabilizing the output and generating the turn-off signal of the power tube M, and is used to detect the drain-source voltage V _DS of the power tube M and compare it with the valley voltage to generate the power of the power tube M turn-on control signal The tube drain-source voltage V _DS valley conduction control circuit and the logic control and drive circuit for driving and controlling the power tube M to be turned on and off, wherein:

The voltage loop circuit includes resistors R5, R6, compensation capacitor C _COM , error amplifier, reference voltage source V _REF , sawtooth wave generator and pulse frequency modulation (PFM) comparator, and one end of resistor R5 is connected to Boost type boost circuit topology The cathode of the diode D is connected, the other end of the resistor R5 is connected to the inverting input end of the error amplifier and one end of the resistor R6, the other end of the resistor R6 is grounded, the non-inverting input end of the error amplifier is connected to the reference voltage source, and one end of the compensation capacitor C _COM It is connected with the output terminal of the error amplifier and the inverting input terminal of the pulse frequency modulation comparator, the other end of the compensation capacitor C _COM is grounded, and the non-inverting input terminal of the pulse frequency modulation comparator is connected with the output terminal of the sawtooth wave generator;

The power tube drain-source voltage V _DS valley conduction control circuit includes a subtractor, a comparator, a power tube drain-source voltage V _DS sampling circuit, a boost circuit topology input voltage V _cin sampling circuit rectified by a full-bridge rectifier, and The output voltage V _o sampling circuit of the Boost-type boost circuit topology, the power tube drain-source voltage V _DS The input terminal of the sampling circuit is connected to the drain of the power tube M in the Boost-type boost circuit topology, and the power tube drain-source voltage V The output terminal of the _DS sampling circuit is connected to the inverting input terminal of the comparator, the positive input terminal of the comparator is connected to the output terminal of the subtractor, the positive input terminal of the subtractor is connected to the output terminal of the V _cin sampling circuit, and V _cin The input terminal of the sampling circuit is connected to the positive output terminal of the full-bridge rectifier, the inverting input terminal of the subtractor is connected to the output terminal of the V _o sampling circuit, and the input terminal of the V _o sampling circuit is connected to the diode in the topology of the Boost type booster circuit D's cathode connection;

The logic control and drive circuit includes a pulse generator, an RS flip-flop and a gate drive circuit. The input end of the pulse generator is connected to the output end of the comparator in the power tube drain-source voltage V _DS valley conduction control circuit. The output terminal is connected to the set input terminal (S) of the RS flip-flop, the reset input terminal (R) of the RS flip-flop is connected to the output terminal of the pulse frequency modulation comparator in the voltage loop circuit, and the output terminal of the RS flip-flop is connected to the gate drive The input end of the circuit is connected, and the output end of the gate drive circuit is connected to the gate of the power transistor M in the Boost circuit topology.

The power tube drain-source voltage V _DS sampling circuit includes resistors R3 and R4, and one end of the resistor R3 is used as the input end of the power tube drain-source voltage V _DS sampling circuit to be connected to the drain end of the power tube M in the Boost boost circuit topology , the other end of the resistor R3 is connected to one end of the resistor R4 and connected to the inverting input of the comparator as the output of the drain-source voltage V _DS sampling circuit of the power tube, and the other end of the resistor R4 is grounded;

The input voltage V _cin sampling circuit of the Boost boost circuit topology includes resistors R1 and R2, one end of the resistor R1 is connected to the positive output end of the full-bridge rectifier, and the other end of the resistor R1 is connected to one end of the resistor R2 as V _cin The output end of the sampling circuit is connected to the positive input end of the subtractor, and the other end of the resistor R2 is grounded;

The output voltage V _o sampling circuit of described Boost step-up circuit topological structure comprises resistance R7 and R8, and one end of resistance R7 is connected with the cathode of diode D in the Boost step-up circuit topological structure as the input terminal of V _o sampling circuit, and resistance R7 The other end of is connected with one end of resistor R8 and connected as the output end of the V _o sampling circuit with the inverting input end of the subtractor.

The comparator in the drain-source voltage V _DS valley bottom conduction control circuit of the power transistor is a hysteresis comparator.

The ratio of the resistor R1 to the resistor R2 is 99/1; the ratio of the resistor R3 to the resistor R4 is 99/1, and the ratio of the resistor R7 to the resistor R8 is 102/1.

Compared with prior art, the beneficial effect of the present invention is:

In the PFC control circuit of the present invention, a drain-source voltage V _DS valley-bottom conduction control circuit is added, and by detecting the drain-source voltage V _DS of the power tube, the valley-bottom conduction of the power tube is realized under a wider input voltage range, reducing Reduce conduction loss and EMI interference; when the parasitic capacitance of the power tube resonates in series with the boost inductor, the power tube is always turned on at the first valley or zero voltage of V _DS , effectively limiting the input current caused by the series resonance Total Harmonic Distortion (THD, TotalHarmonicDistribution); resistor R1 is equal to resistor R3, resistor R2 is equal to resistor R4, the ratio of resistor R1 to resistor R2 is greater than the ratio of resistor R7 to resistor R8, so that when V _DS drops to slightly greater than the valley voltage, the conduction The power tube is passed to partially offset the influence caused by the delay of the gate capacitance of the power tube M.

Description of drawings

Figure 1 is a traditional critical conduction mode (CRM) Boost PFC control circuit;

Fig. 2 is a kind of typical PFC control circuit of reducing power tube conduction power consumption in the prior art;

Fig. 3 is another kind of typical structure block diagram of the PFC control circuit of reducing power tube conduction power consumption in the prior art;

Fig. 4 is the schematic diagram of the PFC control circuit capable of reducing the conduction power consumption of the power transistor under different input voltage situations of the present invention;

Fig. 5 is the concrete circuit diagram of Fig. 4;

Fig. 6 is when 2V _cin >V _o , the correlative waveform figure of circuit of the present invention;

Fig. 7 is when 2V _cin ＜V _o , the correlative waveform figure of circuit of the present invention;

Fig. 8 is a simulation waveform diagram of the circuit of the present invention.

detailed description

The principles and features of the present invention will be described below in conjunction with the accompanying drawings, and the examples given are only used to explain the present invention, and are not intended to limit the scope of the present invention.

Example:

As shown in Figure 4, the circuit of the present invention is based on the topology 1 of the Boost type booster circuit, and also includes a voltage loop circuit 2 for stabilizing the output and generating a power tube shutdown signal, for detecting V _DS and comparing it with the valley voltage to generate Power tube conduction control signal power tube drain-source voltage V _DS valley bottom conduction control circuit 3 and logic control and drive circuit 4 for driving and controlling power tube on and off. The topology 1 of the boost circuit is the same as that of the prior art, including an inductor L, a power tube M, and a diode D. One end of the inductor L is connected to the positive output terminal of the full-bridge rectifier, and the other end of the inductor L is connected to the power tube M. The drain of the power tube M is connected to the negative output terminal of the full-bridge rectifier, the gate of the power tube M is connected to the output terminal of the gate driver (Driver) in the logic control and drive circuit, and the other end of the inductor L It is connected to the anode of diode D, and the cathode of diode D is connected to the load.

As shown in Figure 5, the voltage loop circuit 2 includes resistor R5, resistor R6, compensation capacitor C _COM , error amplifier OTA, reference voltage source V _REF , sawtooth wave generator STG, pulse frequency modulation (PFM) comparator PCOM, and one end of resistor R5 Connect with the cathode of the diode D in the topology of the Boost circuit, connect the other end of the resistor R5 to the inverting input of the error amplifier, connect one end of the resistor R6 to the inverting input of the error amplifier, and connect the other end of the resistor R6 to ground. The non-inverting input of the error amplifier is connected to the reference voltage source V _REF , one end of the compensation capacitor C _COM is connected to the output of the error amplifier, the other end of the compensation capacitor C _COM is grounded, and the output of the error amplifier is connected to the inverting input of the pulse frequency modulator The non-inverting input terminal of the pulse frequency modulation comparator is connected with the output of the sawtooth wave generator, and the output terminal of the pulse frequency modulation comparator is connected with the R input terminal of the RS flip-flop in the logic control and drive circuit.

Power tube drain-source voltage V _DS valley conduction control circuit 3 includes subtractor SUB, comparator COM, V _DS sampling circuit, V _cin sampling circuit, V _o sampling circuit, the input terminal of V _DS sampling circuit and Boost boost circuit topology In the structure, the drain end of the power transistor M is connected, the other end of the V _DS sampling circuit is connected with the inverting input end of the comparator, the output end of the comparator is connected with the input end of the pulse generator in the logic control and drive circuit 4, and the comparator The positive input terminal of the subtractor is connected to the output terminal of the subtractor, the positive input terminal of the subtractor is connected to the output terminal of the V _cin sampling circuit, the input terminal of the V _cin sampling circuit is connected to the positive output terminal of the full-bridge rectifier, and the subtractor The inverting input terminal of the V _o sampling circuit is connected to the output terminal of the V _o sampling circuit, and the input terminal of the V o sampling circuit is connected to the cathode of the diode D in the topology of the Boost boosting circuit.

The logic control and drive circuit 4 includes a pulse generator PUL, an RS flip-flop TR, and a gate driver (Driver). The output of the pulse generator is connected to the S input of the RS flip-flop, and the output of the RS flip-flop is connected to the gate driver. (Driver) input connection.

The V _DS sampling circuit includes a resistor R3 and a resistor R4. One end of the resistor R3 is connected to the drain end of the power transistor M in the Boost circuit topology, the other end of the resistor R3 is connected to one end of the resistor R4, and the other end of the resistor R4 is grounded. The junction of the resistor R3 and the resistor R4 is the first sampling point a, which is connected to the inverting input terminal of the comparator.

The V _cin sampling circuit includes a resistor R1 and a resistor R2. One end of the resistor R1 is connected to the positive output of the full-bridge rectifier, the other end of the resistor R1 is connected to one end of the resistor R2, the other end of the resistor R2 is grounded, and the resistor R1 is connected to the second resistor The connection of R2 is the second sampling point b, which is connected to the non-inverting input terminal of the subtractor.

The V _o sampling circuit includes a resistor R7 and a resistor R8. One end of the resistor R7 is connected to the cathode of the diode D in the Boost circuit topology, the other end of the resistor R7 is connected to one end of the resistor R8, the other end of the resistor R8 is grounded, and the resistor R7 and The connection of the resistor R8 is the third sampling point c, which is connected to the inverting input terminal of the subtractor.

In this embodiment, the comparator is a hysteresis comparator, the ratio of the resistor R1 to the resistor R2 is equal to the ratio of the resistor R3 to the resistor R4, both equal to 99/1, and the ratio of the resistor R7 to the resistor R8 is 102/1.

The working principle of the PFC control circuit capable of reducing the conduction power consumption of the power transistor under different input voltage conditions of the present invention is:

When the power tube M is in the off state, the current i _L on the inductor decreases linearly. If the power tube is not turned on in time when i _L decreases to 0, series resonance will occur between the inductor L and the parasitic capacitance C _d of the power tube . For input voltages of different Boost circuit topologies, the series resonance conditions are also different. According to the difference of the input voltage V _cin , there are mainly the following two situations:

(1) 2V _Cin > V _o

FIG. 6 is a related waveform diagram of a PFC control circuit provided by the present invention that can reduce the on-power consumption of the power transistor under different input voltage conditions in this case. During the period from t ₀ to t ₁ , the power tube M is turned on, the current of the inductor L increases linearly, and the energy increases. After the t _on time, the power tube M is turned off, and the inductor L starts to contribute to the parasitic capacitance C _d of the power tube and other devices. Charging, the voltage on C _d reaches V _O at time t ₁ , and the boost diode D is turned on at this moment. During the period from t ₀ to t ₁ , the power tube M is turned off, the inductor L and V _Cin begin to release energy to the load, the current of the inductor L decreases linearly, but the output remains unchanged at V _O , and at the time t ₂ , the inductor current drops to zero . During the period from t ₂ to t ₃ , the power tube M is still turned off, the inductance L and the parasitic capacitance C _d resonate, and the period of the series resonance is:

$T_R=2\mathrm{\&pi;}\sqrt{{\mathrm{LC}}_d}$ Formula 4

The parasitic capacitance C _d begins to discharge to the inductance L, the voltage on the parasitic capacitance C _d begins to drop, and the inductance current increases in reverse. After 1/4 of the resonance cycle, the current i _L of the inductance L reaches the reverse maximum value, according to the formula 1 can be obtained: the voltage at both ends of the inductor L is 0, so the drain-source voltage V _DS of the power tube M is equal to V _cin at this time; after 1/4 of the resonance cycle reaches _t3 , the drain-source voltage V _DS of the power tube M will reach The valley value V _DS(valley) is:

V _DS(valley) =V _o - ² (V _o -V _cin )= ² V _cin -V _oFormula 5

The expressions of the inductor current i _L and the power tube source-drain voltage V _DS during the period from t ₀ to t ₃ are:

${\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; ~</span>{\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; :</span>\left\{\begin{array}{c}{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; Cin</span>}}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span>\\ {\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DS</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}\end{array}\right.$

$t_1~t_2:\left\{\begin{array}{c}{i}_L=\frac{V_{\mathrm{Cin}}}{L}(t_1-t_0)+(-\frac{V_{\mathrm{Cin}}}{L})(t-t_1)\\ V_{\mathrm{DS}}=V_o\end{array}\right.$ Formula 6

${\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; ~</span>{\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; :</span>\left\{\begin{array}{c}{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}\frac{{\mathrm{<span\; class="notranslate">\; dV</span>}}_{\mathrm{<span\; class="notranslate">\; ds</span>}}}{\mathrm{<span\; class="notranslate">\; dt</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; Cin</span>}}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; sin</span>}<span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; w</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span>\\ {\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DS</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; Cin</span>}}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; cos</span>}<span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; w</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; Cin</span>}}\end{array}\right.<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; w</span>}<span\; class="notranslate">\; =</span>\sqrt{{\mathrm{<span\; class="notranslate">\; LC</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}}$

The ratio of resistor R1 to resistor R2 is equal to 99/1, so the input voltage sampled by the V _cin sampling circuit to the Boost circuit topology is:

$V_b=\frac{V_{\mathrm{cin}}}{100}$ Formula 7

The ratio of the resistor R7 to the resistor R8 is equal to 102/1, and the output voltage sampled by the V _o sampling circuit to the Boost circuit topology is:

$V_c=\frac{V_o}{103}$ Formula 8

The output of the subtractor SUB is:

$V_{\mathrm{sub}}={2V}_b-V_c=\frac{{2V}_{\mathrm{cin}}}{100}-\frac{V_o}{103}$ Formula 9

The ratio of resistor R3 to resistor R4 is 99/1, so the drain-source voltage of the power tube M sampled by the V _DS sampling circuit is:

$V_a=\frac{V_{\mathrm{DS}}}{100}$ Formula 10

At time _t3 , the drain-source voltage of the power tube reaches the valley value V _DS(valley) , and V _a <V _sub , so at this time, the output of the hysteresis comparator in the valley-bottom conduction control circuit of the power tube drain-source voltage V _DS is low level, the power transistor M is turned on through the logic control and the drive circuit, and the V _DS valley conduction is realized. Since the voltage V _DS at both ends of the drain and source drops to the minimum at this time, the conduction power consumption is also significantly reduced.

(2) 2V _Cin < V _o

FIG. 7 is a related waveform diagram of a PFC control circuit provided by the present invention that can reduce the on-power consumption of the power transistor under different input voltage conditions. During t ₀ ~ t ₁ , t ₁ ~ t ₂ , its voltage and current analysis is the same as the first case. But during the period from t ₂ to t ₃ , since 2V _Cin <V _o , the V _ds valley voltage becomes negative at last, but the parasitic diode of the power transistor M may be turned on, thus limiting it to -0.7V. In this case, 2V _cin -V _o <0, the output V _sub of the subtractor SUB =0, so when it is detected that the drain-source voltage V _DS of the power tube drops to 0, the hysteresis comparator outputs a low level, and the logic The control and drive circuit turns on the power tube to realize V _DS zero-voltage conduction. Thus, the turn-on power consumption of the power transistor M is reduced.

Fig. 8 is a simulation waveform diagram of a PFC control circuit with an input voltage of 220V and an output voltage of 400V simulating by the PFC control circuit of the present invention capable of reducing the on-state power consumption of the power transistor under different input voltage conditions. In its ordinate, PFC is the gate drive signal of the power transistor M, V _DS is the drain-source voltage of the power transistor M, i _L is the current on the inductor L, and V _cin is the input voltage transient of the Boost circuit topology Value, V _o is the output voltage of the Boost boost circuit topology. At time t=36.56μs, V _cin =300V, the power tube drain-source voltage V _DS drops to the valley value V _DS(valley) , which is 200V. And at this time 2V _cin -V _o =200V, at the same time the grid drive signal of the power tube becomes high level, the power tube is turned on, thereby realizing the conduction at the bottom of the valley, reducing the power consumption of the power tube, and verifying the present invention feasibility.

The above descriptions are only preferred examples of the present invention, and are not limited to the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (3)

1. A PFC control circuit for reducing the conduction power consumption of the power tube, based on the topology of the Boost type booster circuit, including an inductor L, a power tube M, and a diode D, and one end of the inductor L is connected to the positive output end of the full-bridge rectifier , the other end of the inductor L is connected to the drain of the power tube M and the anode of the diode D, the source of the power tube M is connected to the negative output terminal of the full-bridge rectifier, the cathode of the diode D is connected to one end of the load, and the other end of the load is connected to The source of the power tube M; It is characterized in that it is provided with a voltage loop circuit for stabilizing the output and generating the turn-off signal of the power tube M, and is used to detect the drain-source voltage V _DS of the power tube M and compare it with the valley voltage to generate the power of the power tube M turn-on control signal The tube drain-source voltage V _DS valley conduction control circuit and the logic control and drive circuit for driving and controlling the power tube M to be turned on and off, wherein: The voltage loop circuit includes resistors R5, R6, compensation capacitor C _COM , error amplifier, reference voltage source, sawtooth wave generator and pulse frequency modulation comparator, and one end of resistor R5 is connected to the cathode of diode D in the boost circuit topology , the other end of the resistor R5 is connected to the inverting input end of the error amplifier and one end of the resistor R6, the other end of the resistor R6 is grounded, the non-inverting input end of the error amplifier is connected to the reference voltage source, and one end of the compensation capacitor C _COM is connected to the output of the error amplifier Terminal and the inverting input end of the pulse frequency modulation comparator are connected, the other end of the compensation capacitor C _COM is grounded, and the non-inverting input end of the pulse frequency modulation comparator is connected with the output end of the sawtooth wave generator; Power tube drain-source voltage V _DS valley conduction control circuit includes subtractor, comparator, power tube drain-source voltage V _DS sampling circuit, input voltage V _cin sampling circuit of Boost type boost circuit topology and Boost type boost circuit topology The output voltage V _o sampling circuit of the structure, the input terminal of the power tube drain-source voltage V _DS sampling circuit is connected with the drain of the power tube M in the topology of the Boost type boost circuit, and the output terminal of the power tube drain-source voltage V _DS sampling circuit Connect with the inverting input terminal of the comparator, connect the positive input terminal of the comparator with the output terminal of the subtractor, connect the positive input terminal of the subtractor with the output terminal of the boost circuit topology input voltage V _cin sampling circuit , the input terminal of the boost circuit topology input voltage V _cin sampling circuit is connected to the positive output terminal of the full-bridge rectifier, the inverting input terminal of the subtractor is connected to the output voltage V _o sampling circuit of the boost circuit topology The output terminal is connected, and the input terminal of the Boost type boost circuit topology output voltage V _o sampling circuit is connected with the cathode of the diode D in the Boost type boost circuit topology; The logic control and drive circuit includes a pulse generator, an RS flip-flop and a gate drive circuit. The input end of the pulse generator is connected to the output end of the comparator in the power tube drain-source voltage V _DS valley conduction control circuit. The output terminal is connected to the set input terminal S of the RS flip-flop, the reset input terminal R of the RS flip-flop is connected to the output terminal of the pulse frequency modulation comparator in the voltage loop circuit, and the output terminal of the RS flip-flop is connected to the input terminal of the gate drive circuit Connect, the output terminal of the grid drive circuit is connected to the gate of the power transistor M in the topology of the Boost type booster circuit; The power tube drain-source voltage V _DS sampling circuit includes resistors R3 and R4, and one end of the resistor R3 is used as the input end of the power tube drain-source voltage V _DS sampling circuit to be connected to the drain end of the power tube M in the Boost boost circuit topology , the other end of the resistor R3 is connected to one end of the resistor R4 and connected to the inverting input of the comparator as the output of the drain-source voltage V _DS sampling circuit of the power tube, and the other end of the resistor R4 is grounded; The Boost type step-up circuit topology input voltage V _cin sampling circuit includes resistors R1 and R2, one end of the resistor R1 is connected to the positive output end of the full-bridge rectifier, and the other end of the resistor R1 is connected to one end of the resistor R2 as a Boost type Boost circuit topology The output terminal of the input voltage V _cin sampling circuit is connected to the positive input terminal of the subtractor, and the other end of the resistor R2 is grounded; The Boost type boost circuit topology output voltage V _o sampling circuit includes resistors R7 and R8, and one end of the resistor R7 is used as the input terminal of the Boost type boost circuit topology output voltage V _o sampling circuit and the Boost boost circuit topology The cathode of the middle diode D is connected, and the other end of the resistor R7 is connected to one end of the resistor R8 as a boost circuit topology output voltage V _o . The output end of the sampling circuit is connected to the inverting input end of the subtractor. 2. The PFC control circuit for reducing power transistor turn-on power consumption according to claim 1, characterized in that: the comparator in the power transistor drain-source voltage V _DS valley bottom conduction control circuit is a hysteresis comparator. 3. the PFC control circuit that reduces power tube conduction power consumption according to claim 1, is characterized in that: the ratio of described resistance R1 and resistance R2 is 99:1; The ratio of resistance R3 and resistance R4 is 99: 1. The ratio of resistor R7 to resistor R8 is 102:1.