CN103280963B - A kind of PFC control circuit reducing power tube conducting power consumption - Google Patents

A kind of PFC control circuit reducing power tube conducting power consumption Download PDF

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CN103280963B
CN103280963B CN201310149510.0A CN201310149510A CN103280963B CN 103280963 B CN103280963 B CN 103280963B CN 201310149510 A CN201310149510 A CN 201310149510A CN 103280963 B CN103280963 B CN 103280963B
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power tube
voltage
resistor
boost
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CN103280963A (en
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孙伟锋
张允武
宋慧滨
祝靖
陆生礼
时龙兴
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Southeast University
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Abstract

本发明提供了一种降低功率管导通功耗的PFC控制电路,基于Boost升压电路的拓扑结构,包括电压环电路、功率管漏源电压VDS谷底导通控制电路和逻辑控制与驱动电路,电压环电路用于稳定输出和产生功率管的关断信号,功率管漏源电压VDS谷底导通控制电路用于检测功率管漏源VDS并与谷底电压进行比较,产生功率管的导通控制信号,逻辑控制与驱动电路用于驱动控制功率管的开通和关断。通过检测VDS的电压,确保在不同的输入电压情况下,功率管都能在其漏源电压VDS处于谷底电压或者零电压时开启,从而降低了功率管导通时的损耗。

The present invention provides a PFC control circuit for reducing the conduction power consumption of the power tube, which is based on the topology of the Boost circuit, including a voltage loop circuit, a power tube drain-source voltage V DS valley bottom conduction control circuit, and a logic control and drive circuit The voltage loop circuit is used to stabilize the output and generate the shutdown signal of the power tube. The power tube drain-source voltage V DS valley conduction control circuit is used to detect the drain-source V DS of the power tube and compare it with the valley-bottom voltage to generate the conduction of the power tube. Through the control signal, the logic control and drive circuit is used to drive and control the turn-on and turn-off of the power tube. By detecting the voltage of V DS , it is ensured that under different input voltage conditions, the power tube can be turned on when its drain-source voltage V DS is at the bottom voltage or zero voltage, thereby reducing the loss of the power tube when it is turned on.

Description

一种降低功率管导通功耗的PFC控制电路A PFC control circuit for reducing conduction power consumption of power transistor

技术领域technical field

本发明涉及开关电源领域的单相功率因素校正电路,特别涉及一种降低功率管导通功耗的PFC控制电路。The invention relates to a single-phase power factor correction circuit in the field of switching power supplies, in particular to a PFC control circuit for reducing the conduction power consumption of a power tube.

背景技术Background technique

目前,在图1所示的临界导通模式(CRM,CriticalConductionMode)的Boost型PFC中,传统的零电流检测导通方案,在功率管开启瞬间,功率管的源漏电压较大,导通功耗也较大,这是因为输入交流电压Vin的频率相对功率管M的开关频率来说很小,所以可以假设在一个功率管M的开关周期内输入电压的大小不变。假设输入交流电压Vin经全桥整流器输出电压为Vcin,当功率管M处于导通状态时,电感L两端电压VL为Vcin,此时电感L两端电压VL与电感电流iL的关系为:At present, in the Boost PFC of the critical conduction mode (CRM, Critical Conduction Mode) shown in Figure 1, the traditional zero-current detection conduction scheme, when the power transistor is turned on, the source-drain voltage of the power transistor is relatively large, and the conduction work The consumption is also relatively large, because the frequency of the input AC voltage V in is relatively small compared to the switching frequency of the power transistor M, so it can be assumed that the magnitude of the input voltage remains unchanged within one switching cycle of the power transistor M. Assuming that the input AC voltage V in is V cin through the full-bridge rectifier, when the power transistor M is in the conduction state, the voltage V L across the inductor L is V cin , and the voltage V L across the inductor L is equal to the inductor current i The relation of L is:

L di L dt = V L = V cin 公式1 L di L dt = V L = V cin Formula 1

由公式1可知,此时电感电流将线性增加,如果功率管M的导通时间为Ton,那么功率管M导通期间,电感电流iL增加的大小△il(+)为:It can be seen from formula 1 that the inductor current will increase linearly at this time. If the on-time of the power transistor M is T on , then the increase of the inductor current i L during the on-time of the power transistor M is △i l (+) as follows:

Δi L ( + ) = i L ( peak ) = V cin L T on 公式2 Δi L ( + ) = i L ( peak ) = V cin L T on Formula 2

当功率管M处于关断状态时,假设关断时间为Toff,Boost电路的输出电压为Vo,此时电感L两端电压VL与电感电流iL的关系为:When the power tube M is in the off state, assuming the off time is T off and the output voltage of the Boost circuit is V o , the relationship between the voltage V L at both ends of the inductor L and the inductor current i L is:

L di L dt = V L = V cin - V o 公式3 L di L dt = V L = V cin - V o Formula 3

对于Boost升压电路,Vcin-Vo<0,所以功率管M关断期间,电感电流iL将线性减小,且功率管M漏源电压VDS等于输出电压Vo。对于传统的采用零电流检测的PFC控制电路,当检测到电感电流iL降到0时,开启功率管,但是开启瞬间,功率管M漏源电压VDS等于输出电压Vo,因此会产生严重的导通功耗。For the Boost circuit, V cin -V o <0, so when the power tube M is turned off, the inductor current i L will decrease linearly, and the drain-source voltage V DS of the power tube M is equal to the output voltage V o . For the traditional PFC control circuit using zero-current detection, when it detects that the inductor current i L drops to 0, the power tube is turned on, but at the moment of turning on, the drain-source voltage V DS of the power tube M is equal to the output voltage V o , so serious conduction power consumption.

现有技术中,为了降低导通功耗,一种被称为谷底导通(VS,ValleySwitching)或者零电压开关(ZVS,ZeroVoltageSwitching)的方法被广泛使用在CRM的PFC控制电路中。其主要原理是:当检测到Boost电路结构中的电感电流iL下降到零时,功率管M延迟一定时间开启,Boost电路结构中的电感L与功率管的漏源寄生电容Cd将发生串联谐振,功率管的漏源寄生电容Cd开始通过电感放电,假设在谐振发生一段时间Td后,功率管的漏源寄生电容Cd上的电压VDS下降到谷底值或者0,如果恰好使得功率管延迟开启的时间也等于Td,那么就实现了谷底导通或者零电压开关,降低了功率管的导通功耗。In the prior art, in order to reduce conduction power consumption, a method called valley conduction (VS, ValleySwitching) or zero voltage switching (ZVS, ZeroVoltageSwitching) is widely used in the PFC control circuit of the CRM. The main principle is: when it is detected that the inductor current i L in the Boost circuit structure drops to zero, the power tube M is turned on after a certain time delay, and the inductance L in the Boost circuit structure and the drain-source parasitic capacitance C d of the power tube will be connected in series Resonance, the drain-source parasitic capacitance C d of the power tube starts to discharge through the inductor, assuming that after the resonance occurs for a period of time T d , the voltage V DS on the drain-source parasitic capacitance C d of the power tube drops to the bottom value or 0, if it happens to make The delayed turn-on time of the power tube is also equal to T d , so the valley-bottom conduction or zero-voltage switching is realized, which reduces the conduction power consumption of the power tube.

现有技术中一种典型的降低功率管导通功耗的PFC控制电路如图2所示,它的工作原理是:通过在传统的CRM的PFC电感电流检测部分加入RC延时模块,使功率管延迟开启的时间等于谐振周期的一半,使得功率管恰好在功率管漏源电压VDS下降到谷底值时导通,实现降低功率管导通功耗的目的。图2所示电路存在以下的问题:功率管的延迟导通时间与与输入电压有关,而且,对于不同的输入电压,Boost电路结构中的电感与功率管寄生电容将产生不同的串联谐振情况,所以通过加入RC延时模块实现谷底电压或者零电压导通,并不能满足不同大小的输入电压。In the prior art, a typical PFC control circuit for reducing the conduction power consumption of the power transistor is shown in Figure 2. Its working principle is: by adding an RC delay module to the PFC inductor current detection part of the traditional CRM, the power The time for delaying the turn-on of the tube is equal to half of the resonance period, so that the power tube is turned on just when the drain-source voltage V DS of the power tube drops to the bottom value, and the purpose of reducing the power consumption of the power tube is achieved. The circuit shown in Figure 2 has the following problems: the delayed turn-on time of the power tube is related to the input voltage, and for different input voltages, the inductance in the Boost circuit structure and the parasitic capacitance of the power tube will produce different series resonance situations. Therefore, by adding an RC delay module to achieve valley voltage or zero voltage conduction, it cannot satisfy different input voltages.

现有技术中,另一种典型的降低功率管导通功耗的PFC控制电路如图3所示,它利用检测电路确定谐振时几个重要时刻,再根据时谐振时互感电压两端的电压以输入电压为中心对称,便可以通过电路运算知道功率管漏源电压VDS达到谷底电压的时刻。该电路还加入了栅驱动信号的延时,从而能够实现功率管的谷底开启,降低功率管导通功耗。该电路也不能满足不同大小的输入电压的情况,且该电路比较复杂,不易实现。In the prior art, another typical PFC control circuit for reducing the on-state power consumption of the power transistor is shown in Figure 3. It uses the detection circuit to determine several important moments during resonance, and then according to the voltage at both ends of the mutual inductance voltage during resonance and The input voltage is center-symmetric, and the moment when the drain-source voltage V DS of the power tube reaches the valley voltage can be known through circuit calculation. The circuit also adds a delay of the gate drive signal, so that the power tube can be turned on at the bottom of the valley, and the power consumption of the power tube can be reduced. This circuit also cannot meet the conditions of input voltages of different sizes, and the circuit is relatively complicated and difficult to implement.

发明内容Contents of the invention

为了克服现有技术实现VDS谷底电压或者零电压导通时(降低功率管导通功耗),不能满足不同大小的输入电压以及电路结构复杂、不易实现的情况,本发明提供了一种降低功率管导通功耗的PFC控制电路,通过引入功率管漏源电压谷底导通控制电路,在实现降低功率管导通功耗的同时又满足不同的输入电压。该电路结构简单、易于实现,通过检测VDS的电压,确保在不同的输入电压情况下,功率管都能在其漏源电压VDS处于谷底电压或者零电压时开启,从而降低功率管导通时的损耗。In order to overcome the fact that the prior art realizes V DS valley voltage or zero voltage conduction (reducing power tube conduction power consumption), it cannot meet the input voltages of different sizes and the circuit structure is complicated and difficult to realize, the present invention provides a method to reduce The PFC control circuit of the power tube conduction power consumption, through the introduction of the power tube drain-source voltage valley bottom conduction control circuit, can reduce the power tube conduction power consumption while meeting different input voltages. The circuit structure is simple and easy to implement. By detecting the voltage of V DS , it is ensured that the power tube can be turned on when its drain-source voltage V DS is at the bottom voltage or zero voltage under different input voltage conditions, thereby reducing the power tube conduction. time loss.

本发明解决上述技术问题的技术方案如下:The technical scheme that the present invention solves the problems of the technologies described above is as follows:

一种降低功率管导通功耗的PFC控制电路,基于Boost型升压电路的拓扑结构,包括电感L、功率管M、二极管D,电感L的一端与全桥整流器的正输出端连接,电感L的另一端与功率管M的漏极、二极管D的阳极连接,功率管M的源极与全桥整流器的负输出端连接,二极管D的阴极连接负载的一端,负载的另一端连接功率管M的源极;A PFC control circuit for reducing the conduction power consumption of the power tube, based on the topology of the Boost circuit, including an inductor L, a power tube M, and a diode D, one end of the inductor L is connected to the positive output end of the full-bridge rectifier, and the inductor The other end of L is connected to the drain of power tube M and the anode of diode D, the source of power tube M is connected to the negative output terminal of the full-bridge rectifier, the cathode of diode D is connected to one end of the load, and the other end of the load is connected to the power tube source of M;

其特征在于:设有用于稳定输出和产生功率管M关断信号的电压环电路、用于检测功率管M漏源电压VDS并与谷底电压进行比较,产生功率管M导通控制信号的功率管漏源电压VDS谷底导通控制电路和用于驱动控制功率管M开通和关断的逻辑控制与驱动电路,其中:It is characterized in that it is provided with a voltage loop circuit for stabilizing the output and generating the turn-off signal of the power tube M, and is used to detect the drain-source voltage V DS of the power tube M and compare it with the valley voltage to generate the power of the power tube M turn-on control signal The tube drain-source voltage V DS valley conduction control circuit and the logic control and drive circuit for driving and controlling the power tube M to be turned on and off, wherein:

电压环电路包括电阻R5、R6、补偿电容CCOM、误差放大器、参考电压源VREF、锯齿波发生器及脉冲频率调制(PFM)比较器,电阻R5的一端与Boost型升压电路拓扑结构中二极管D的阴极连接,电阻R5另一端与误差放大器的反相输入端及电阻R6的一端连接,电阻R6的另一端接地,误差放大器的同相输入端与参考电压源连接,补偿电容CCOM的一端与误差放大器的输出端及脉冲频率调制比较器的反相输入端连接,补偿电容CCOM的另一端接地,脉冲频率调制比较器的同相输入端与锯齿波发生器的输出端连接;The voltage loop circuit includes resistors R5, R6, compensation capacitor C COM , error amplifier, reference voltage source V REF , sawtooth wave generator and pulse frequency modulation (PFM) comparator, and one end of resistor R5 is connected to Boost type boost circuit topology The cathode of the diode D is connected, the other end of the resistor R5 is connected to the inverting input end of the error amplifier and one end of the resistor R6, the other end of the resistor R6 is grounded, the non-inverting input end of the error amplifier is connected to the reference voltage source, and one end of the compensation capacitor C COM It is connected with the output terminal of the error amplifier and the inverting input terminal of the pulse frequency modulation comparator, the other end of the compensation capacitor C COM is grounded, and the non-inverting input terminal of the pulse frequency modulation comparator is connected with the output terminal of the sawtooth wave generator;

功率管漏源电压VDS谷底导通控制电路包括减法器、比较器、功率管漏源电压VDS采样电路、经全桥整流器整流的Boost型升压电路拓扑结构的输入电压Vcin采样电路及Boost型升压电路拓扑结构的输出电压Vo采样电路,功率管漏源电压VDS采样电路的输入端与Boost型升压电路拓扑结构中功率管M的漏极连接,功率管漏源电压VDS采样电路的输出端与比较器的反相输入端连接,比较器的正向输入端与减法器的输出端连接,减法器的正向输入端与Vcin采样电路的输出端连接,Vcin采样电路的输入端与全桥整流器的正向输出端连接,减法器的反相输入端与Vo采样电路的输出端连接,Vo采样电路的输入端与Boost型升压电路拓扑结构中二极管D的阴极连接;The power tube drain-source voltage V DS valley conduction control circuit includes a subtractor, a comparator, a power tube drain-source voltage V DS sampling circuit, a boost circuit topology input voltage V cin sampling circuit rectified by a full-bridge rectifier, and The output voltage V o sampling circuit of the Boost-type boost circuit topology, the power tube drain-source voltage V DS The input terminal of the sampling circuit is connected to the drain of the power tube M in the Boost-type boost circuit topology, and the power tube drain-source voltage V The output terminal of the DS sampling circuit is connected to the inverting input terminal of the comparator, the positive input terminal of the comparator is connected to the output terminal of the subtractor, the positive input terminal of the subtractor is connected to the output terminal of the V cin sampling circuit, and V cin The input terminal of the sampling circuit is connected to the positive output terminal of the full-bridge rectifier, the inverting input terminal of the subtractor is connected to the output terminal of the V o sampling circuit, and the input terminal of the V o sampling circuit is connected to the diode in the topology of the Boost type booster circuit D's cathode connection;

逻辑控制与驱动电路包括脉冲发生器、RS触发器及栅极驱动电路,脉冲发生器的输入端与功率管漏源电压VDS谷底导通控制电路中比较器的输出端连接,脉冲发生器的输出端与RS触发器的置位输入端(S)连接,RS触发器的复位输入端(R)连接电压环电路中脉冲频率调制比较器的输出端,RS触发器的输出端与栅极驱动电路的输入端连接,栅极驱动电路的输出端连接Boost型升压电路拓扑结构中功率管M的栅极。The logic control and drive circuit includes a pulse generator, an RS flip-flop and a gate drive circuit. The input end of the pulse generator is connected to the output end of the comparator in the power tube drain-source voltage V DS valley conduction control circuit. The output terminal is connected to the set input terminal (S) of the RS flip-flop, the reset input terminal (R) of the RS flip-flop is connected to the output terminal of the pulse frequency modulation comparator in the voltage loop circuit, and the output terminal of the RS flip-flop is connected to the gate drive The input end of the circuit is connected, and the output end of the gate drive circuit is connected to the gate of the power transistor M in the Boost circuit topology.

所述功率管漏源电压VDS采样电路包括电阻R3和R4,电阻R3的一端作为功率管漏源电压VDS采样电路的输入端与Boost升压型电路拓扑结构中功率管M的漏端连接,电阻R3的另一端与电阻R4的一端连接并作为功率管漏源电压VDS采样电路的输出端与比较器的反相输入端连接,电阻R4的另一端接地;The power tube drain-source voltage V DS sampling circuit includes resistors R3 and R4, and one end of the resistor R3 is used as the input end of the power tube drain-source voltage V DS sampling circuit to be connected to the drain end of the power tube M in the Boost boost circuit topology , the other end of the resistor R3 is connected to one end of the resistor R4 and connected to the inverting input of the comparator as the output of the drain-source voltage V DS sampling circuit of the power tube, and the other end of the resistor R4 is grounded;

所述Boost升压电路拓扑结构的输入电压Vcin采样电路包括电阻R1和R2,电阻R1的一端与全桥整流器的正输出端连接,电阻R1的另一端与电阻R2的一端连接并作为Vcin采样电路的输出端与减法器的正向输入端连接,电阻R2的另一端接地;The input voltage V cin sampling circuit of the Boost boost circuit topology includes resistors R1 and R2, one end of the resistor R1 is connected to the positive output end of the full-bridge rectifier, and the other end of the resistor R1 is connected to one end of the resistor R2 as V cin The output end of the sampling circuit is connected to the positive input end of the subtractor, and the other end of the resistor R2 is grounded;

所述Boost升压电路拓扑结构的输出电压Vo采样电路包括电阻R7和R8,电阻R7的一端作为Vo采样电路的输入端与Boost升压型电路拓扑结构中二极管D的阴极连接,电阻R7的另一端与电阻R8一端连接并作为Vo采样电路的输出端与减法器的反相输入端连接。The output voltage V o sampling circuit of described Boost step-up circuit topological structure comprises resistance R7 and R8, and one end of resistance R7 is connected with the cathode of diode D in the Boost step-up circuit topological structure as the input terminal of V o sampling circuit, and resistance R7 The other end of is connected with one end of resistor R8 and connected as the output end of the V o sampling circuit with the inverting input end of the subtractor.

所述功率管漏源电压VDS谷底导通控制电路中的比较器是一个迟滞比较器。The comparator in the drain-source voltage V DS valley bottom conduction control circuit of the power transistor is a hysteresis comparator.

所述的电阻R1与电阻R2的比值为99/1;电阻R3与电阻R4的比值为99/1,电阻R7与电阻R8的比值为102/1。The ratio of the resistor R1 to the resistor R2 is 99/1; the ratio of the resistor R3 to the resistor R4 is 99/1, and the ratio of the resistor R7 to the resistor R8 is 102/1.

与现有技术相比,本发明的有益效果是:Compared with prior art, the beneficial effect of the present invention is:

本发明的PFC控制电路中,加入了漏源电压VDS谷底导通控制电路,通过检测功率管漏源电压VDS,实现了在更广的输入电压范围下实现功率管的谷底导通,降低了导通损耗和EMI干扰;当功率管的寄生电容与升压电感串联谐振时,功率管始终在VDS的第一个谷底或者零电压导通,有效地限制因为串联谐振带来的输入电流总谐波失真(THD,TotalHarmonicDistribution);电阻R1等于电阻R3,电阻R2等于电阻R4,电阻R1与电阻R2的比值大于电阻R7与电阻R8的比值,使得VDS下降到稍大于谷底电压时,导通功率管,部分抵消由于功率管M的栅电容延时所造成的影响。In the PFC control circuit of the present invention, a drain-source voltage V DS valley-bottom conduction control circuit is added, and by detecting the drain-source voltage V DS of the power tube, the valley-bottom conduction of the power tube is realized under a wider input voltage range, reducing Reduce conduction loss and EMI interference; when the parasitic capacitance of the power tube resonates in series with the boost inductor, the power tube is always turned on at the first valley or zero voltage of V DS , effectively limiting the input current caused by the series resonance Total Harmonic Distortion (THD, TotalHarmonicDistribution); resistor R1 is equal to resistor R3, resistor R2 is equal to resistor R4, the ratio of resistor R1 to resistor R2 is greater than the ratio of resistor R7 to resistor R8, so that when V DS drops to slightly greater than the valley voltage, the conduction The power tube is passed to partially offset the influence caused by the delay of the gate capacitance of the power tube M.

附图说明Description of drawings

图1是传统的临界导通模式(CRM)Boost型PFC控制电路;Figure 1 is a traditional critical conduction mode (CRM) Boost PFC control circuit;

图2是现有技术中的一种典型的降低功率管导通功耗的PFC控制电路;Fig. 2 is a kind of typical PFC control circuit of reducing power tube conduction power consumption in the prior art;

图3是现有技术中的另一种典型的降低功率管导通功耗的PFC控制电路结构框图;Fig. 3 is another kind of typical structure block diagram of the PFC control circuit of reducing power tube conduction power consumption in the prior art;

图4是本发明的能够在不同输入电压情况下降低功率管导通功耗的PFC控制电路原理图;Fig. 4 is the schematic diagram of the PFC control circuit capable of reducing the conduction power consumption of the power transistor under different input voltage situations of the present invention;

图5是图4的具体电路图;Fig. 5 is the concrete circuit diagram of Fig. 4;

图6是2Vcin>Vo时,本发明电路的相关波形图;Fig. 6 is when 2V cin >V o , the correlative waveform figure of circuit of the present invention;

图7是2Vcin<Vo时,本发明电路的相关波形图;Fig. 7 is when 2V cin <V o , the correlative waveform figure of circuit of the present invention;

图8是本发明电路的仿真波形图。Fig. 8 is a simulation waveform diagram of the circuit of the present invention.

具体实施方式detailed description

以下结合附图对本发明的原理和特征进行描述,所举的实例只用于解释本发明,并非用于限定本发明的范围。The principles and features of the present invention will be described below in conjunction with the accompanying drawings, and the examples given are only used to explain the present invention, and are not intended to limit the scope of the present invention.

实施例:Example:

如图4,本发明电路基于Boost型升压电路的拓扑结构1,还包括用于稳定输出和产生功率管关断信号的电压环电路2、用于检测VDS并与谷底电压进行比较,产生功率管导通控制信号的功率管漏源电压VDS谷底导通控制电路3及用于驱动控制功率管开通和关断的逻辑控制与驱动电路4。其中Boost型升压电路的拓扑结构1与现有技术相同,包括电感L、功率管M、二极管D,电感L的一端与全桥整流器的正输出端连接,电感L的另一端与功率管M的漏极连接,功率管M的源极与全桥整流器的负输出端连接,功率管M的栅极与逻辑控制与驱动电路中栅极驱动(Driver)的输出端连接,电感L的另一端与二极管D的阳极连接,二极管D的阴极与负载连接。As shown in Figure 4, the circuit of the present invention is based on the topology 1 of the Boost type booster circuit, and also includes a voltage loop circuit 2 for stabilizing the output and generating a power tube shutdown signal, for detecting V DS and comparing it with the valley voltage to generate Power tube conduction control signal power tube drain-source voltage V DS valley bottom conduction control circuit 3 and logic control and drive circuit 4 for driving and controlling power tube on and off. The topology 1 of the boost circuit is the same as that of the prior art, including an inductor L, a power tube M, and a diode D. One end of the inductor L is connected to the positive output terminal of the full-bridge rectifier, and the other end of the inductor L is connected to the power tube M. The drain of the power tube M is connected to the negative output terminal of the full-bridge rectifier, the gate of the power tube M is connected to the output terminal of the gate driver (Driver) in the logic control and drive circuit, and the other end of the inductor L It is connected to the anode of diode D, and the cathode of diode D is connected to the load.

如图5,电压环电路2包括电阻R5、电阻R6、补偿电容CCOM、误差放大器OTA、参考电压源VREF、锯齿波发生器STG、脉冲频率调制(PFM)比较器PCOM,电阻R5的一端与Boost升压电路的拓扑结构中的二极管D的阴极连接,电阻R5另一端误差放大器的反相输入端连接,电阻R6的一端与误差放大器的反相输入端连接,电阻R6的另一端接地,误差放大器的同相输入端与参考电压源VREF连接,补偿电容CCOM的一端与误差放大器的输出连接,补偿电容CCOM的另一端接地,误差放大器的输出与脉冲频率调制较器的反相输入端连接,脉冲频率调制比较器的同相输入端与锯齿波发生器输出连接,脉冲频率调制比较器的输出端与逻辑控制与驱动电路中RS触发器的R输入端连接。As shown in Figure 5, the voltage loop circuit 2 includes resistor R5, resistor R6, compensation capacitor C COM , error amplifier OTA, reference voltage source V REF , sawtooth wave generator STG, pulse frequency modulation (PFM) comparator PCOM, and one end of resistor R5 Connect with the cathode of the diode D in the topology of the Boost circuit, connect the other end of the resistor R5 to the inverting input of the error amplifier, connect one end of the resistor R6 to the inverting input of the error amplifier, and connect the other end of the resistor R6 to ground. The non-inverting input of the error amplifier is connected to the reference voltage source V REF , one end of the compensation capacitor C COM is connected to the output of the error amplifier, the other end of the compensation capacitor C COM is grounded, and the output of the error amplifier is connected to the inverting input of the pulse frequency modulator The non-inverting input terminal of the pulse frequency modulation comparator is connected with the output of the sawtooth wave generator, and the output terminal of the pulse frequency modulation comparator is connected with the R input terminal of the RS flip-flop in the logic control and drive circuit.

功率管漏源电压VDS谷底导通控制电路3包括减法器SUB、比较器COM、VDS采样电路、Vcin采样电路、Vo采样电路,VDS采样电路的输入端与Boost升压电路拓扑结构中功率管M的漏端连接,VDS采样电路的另一端与比较器的反相输入端连接,比较器的输出端与逻辑控制与驱动电路4中脉冲发生器的输入端连接,比较器的正向输入端与减法器的输出端连接,减法器的正向输入端与Vcin采样电路的输出端连接,Vcin采样电路的输入端与全桥整流器的正向输出端连接,减法器的反相输入端与Vo采样电路的输出端连接,Vo采样电路的输入端与Boost升压电路拓扑结构中二极管D的阴极连接。Power tube drain-source voltage V DS valley conduction control circuit 3 includes subtractor SUB, comparator COM, V DS sampling circuit, V cin sampling circuit, V o sampling circuit, the input terminal of V DS sampling circuit and Boost boost circuit topology In the structure, the drain end of the power transistor M is connected, the other end of the V DS sampling circuit is connected with the inverting input end of the comparator, the output end of the comparator is connected with the input end of the pulse generator in the logic control and drive circuit 4, and the comparator The positive input terminal of the subtractor is connected to the output terminal of the subtractor, the positive input terminal of the subtractor is connected to the output terminal of the V cin sampling circuit, the input terminal of the V cin sampling circuit is connected to the positive output terminal of the full-bridge rectifier, and the subtractor The inverting input terminal of the V o sampling circuit is connected to the output terminal of the V o sampling circuit, and the input terminal of the V o sampling circuit is connected to the cathode of the diode D in the topology of the Boost boosting circuit.

逻辑控制与驱动电路4包括脉冲发生器PUL、RS触发器TR、栅极驱动(Driver),脉冲发生器的输出端与RS触发器的S输入端连接,RS触发器的输出端与栅极驱动(Driver)的输入端连接。The logic control and drive circuit 4 includes a pulse generator PUL, an RS flip-flop TR, and a gate driver (Driver). The output of the pulse generator is connected to the S input of the RS flip-flop, and the output of the RS flip-flop is connected to the gate driver. (Driver) input connection.

VDS采样电路包括电阻R3和电阻R4,电阻R3的一端与Boost升压电路拓扑结构中功率管M的漏端连接,电阻R3的另一端与电阻R4的一端连接,电阻R4的另一端接地,电阻R3与电阻R4的连接处为第一采样点a,与比较器的反相输入端连接。The V DS sampling circuit includes a resistor R3 and a resistor R4. One end of the resistor R3 is connected to the drain end of the power transistor M in the Boost circuit topology, the other end of the resistor R3 is connected to one end of the resistor R4, and the other end of the resistor R4 is grounded. The junction of the resistor R3 and the resistor R4 is the first sampling point a, which is connected to the inverting input terminal of the comparator.

Vcin采样电路包括电阻R1和电阻R2,电阻R1的一端与全桥整流器的正输出端连接,电阻R1的另一端与电阻R2的一端连接,电阻R2的另一端接地,阻R1与第二电阻R2的连接处为第二采样点b,与减法器的同相输入端连接。The V cin sampling circuit includes a resistor R1 and a resistor R2. One end of the resistor R1 is connected to the positive output of the full-bridge rectifier, the other end of the resistor R1 is connected to one end of the resistor R2, the other end of the resistor R2 is grounded, and the resistor R1 is connected to the second resistor The connection of R2 is the second sampling point b, which is connected to the non-inverting input terminal of the subtractor.

Vo采样电路包括电阻R7和电阻R8,电阻R7的一端与Boost升压电路拓扑结构中二极管D的阴极连接,电阻R7的另一端与电阻R8一端连接,电阻R8的另一端接地,电阻R7与电阻R8的连接处为第三采样点c,与减法器的反相输入端连接。The V o sampling circuit includes a resistor R7 and a resistor R8. One end of the resistor R7 is connected to the cathode of the diode D in the Boost circuit topology, the other end of the resistor R7 is connected to one end of the resistor R8, the other end of the resistor R8 is grounded, and the resistor R7 and The connection of the resistor R8 is the third sampling point c, which is connected to the inverting input terminal of the subtractor.

在本实施例中,比较器是一个迟滞比较器,电阻R1与电阻R2的比值等于电阻R3与电阻R4的比值,都等于99/1,电阻R7与电阻R8的比值为102/1。In this embodiment, the comparator is a hysteresis comparator, the ratio of the resistor R1 to the resistor R2 is equal to the ratio of the resistor R3 to the resistor R4, both equal to 99/1, and the ratio of the resistor R7 to the resistor R8 is 102/1.

本发明的能够在不同输入电压情况下降低功率管导通功耗的PFC控制电路的工作原理是:The working principle of the PFC control circuit capable of reducing the conduction power consumption of the power transistor under different input voltage conditions of the present invention is:

当功率管M处于关断状态时,电感上的电流iL线性减小,如果当iL减小为0时,功率管未及时开启,电感L和功率管的寄生电容Cd将发生串联谐振。对于不同的Boost升压电路拓扑结构的输入电压,其串联谐振情况也不一样。根据输入电压Vcin的不同主要有下面2种情况:When the power tube M is in the off state, the current i L on the inductor decreases linearly. If the power tube is not turned on in time when i L decreases to 0, series resonance will occur between the inductor L and the parasitic capacitance C d of the power tube . For input voltages of different Boost circuit topologies, the series resonance conditions are also different. According to the difference of the input voltage V cin , there are mainly the following two situations:

(1)2VCin>Vo (1) 2V Cin > V o

图6是这种情况下本发明提供的一种能够在不同输入电压情况下降低功率管导通功耗的PFC控制电路的相关波形图。在t0~t1期间,功率管M导通,电感L的电流线性增加,能量增加,当经过ton时间后,功率管M关断,电感L开始向功率管等器件的寄生电容Cd充电,在t1时刻Cd上的电压达到VO,此时升压二极管D导通。在t0~t1期间,功率管M关断,电感L和VCin开始向负载释放能量,电感L电流线性下降,但输出保持在VO不变,在t2时刻,电感电流下降至零。在t2~t3期间,功率管M仍然关断,电感L和寄生电容Cd发生谐振,串联谐振的周期为:FIG. 6 is a related waveform diagram of a PFC control circuit provided by the present invention that can reduce the on-power consumption of the power transistor under different input voltage conditions in this case. During the period from t 0 to t 1 , the power tube M is turned on, the current of the inductor L increases linearly, and the energy increases. After the t on time, the power tube M is turned off, and the inductor L starts to contribute to the parasitic capacitance C d of the power tube and other devices. Charging, the voltage on C d reaches V O at time t 1 , and the boost diode D is turned on at this moment. During the period from t 0 to t 1 , the power tube M is turned off, the inductor L and V Cin begin to release energy to the load, the current of the inductor L decreases linearly, but the output remains unchanged at V O , and at the time t 2 , the inductor current drops to zero . During the period from t 2 to t 3 , the power tube M is still turned off, the inductance L and the parasitic capacitance C d resonate, and the period of the series resonance is:

T R = 2 &pi; LC d 公式4 T R = 2 &pi; LC d Formula 4

寄生电容Cd开始向电感L放电,寄生电容Cd上的电压开始下降,电感电流反向增大,经过1/4个谐振周期后,电感L的电流iL达到反向最大值,由公式1可得:电感L两端电压为0,所以此时功率管M漏源电压VDS等于Vcin;再经过1/4个谐振周期到达t3时,功率管M漏源电压VDS将达到谷底值VDS(valley),为:The parasitic capacitance C d begins to discharge to the inductance L, the voltage on the parasitic capacitance C d begins to drop, and the inductance current increases in reverse. After 1/4 of the resonance cycle, the current i L of the inductance L reaches the reverse maximum value, according to the formula 1 can be obtained: the voltage at both ends of the inductor L is 0, so the drain-source voltage V DS of the power tube M is equal to V cin at this time; after 1/4 of the resonance cycle reaches t3 , the drain-source voltage V DS of the power tube M will reach The valley value V DS(valley) is:

VDS(valley)=Vo-2(Vo-Vcin)=2Vcin-Vo公式5V DS(valley) =V o - 2 (V o -V cin )= 2 V cin -V oFormula 5

在t0~t3这段时间内的电感电流iL和功率管源漏电压VDS表达式为:The expressions of the inductor current i L and the power tube source-drain voltage V DS during the period from t 0 to t 3 are:

tt 00 ~~ tt 11 :: ii LL == VV CinCin LL (( tt -- tt 00 )) VV DSDS == 00

t 1 ~ t 2 : i L = V Cin L ( t 1 - t 0 ) + ( - V Cin L ) ( t - t 1 ) V DS = V o 公式6 t 1 ~ t 2 : i L = V Cin L ( t 1 - t 0 ) + ( - V Cin L ) ( t - t 1 ) V DS = V o Formula 6

tt 22 ~~ tt 33 :: ii LL == CC dd dVdV dsds dtdt == -- CC dd (( VV oo -- VV CinCin )) sinsin [[ ww (( tt -- tt 22 )) ]] VV DSDS == (( VV oo -- VV CinCin )) coscos [[ ww (( tt -- tt 22 )) ]] ++ VV CinCin ,, ww == LCLC dd

电阻R1与电阻R2的比值等于99/1,所以经Vcin采样电路采样到Boost型升压电路拓扑结构的输入电压为:The ratio of resistor R1 to resistor R2 is equal to 99/1, so the input voltage sampled by the V cin sampling circuit to the Boost circuit topology is:

V b = V cin 100 公式7 V b = V cin 100 Formula 7

电阻R7与电阻R8的比值等于102/1,经Vo采样电路采样到Boost型升压电路拓扑结构的输出电压为:The ratio of the resistor R7 to the resistor R8 is equal to 102/1, and the output voltage sampled by the V o sampling circuit to the Boost circuit topology is:

V c = V o 103 公式8 V c = V o 103 Formula 8

经减法器SUB的输出为:The output of the subtractor SUB is:

V sub = 2 V b - V c = 2 V cin 100 - V o 103 公式9 V sub = 2 V b - V c = 2 V cin 100 - V o 103 Formula 9

电阻R3与电阻R4的比值为99/1,所以经VDS采样电路采样到的功率管M的漏源电压为:The ratio of resistor R3 to resistor R4 is 99/1, so the drain-source voltage of the power tube M sampled by the V DS sampling circuit is:

V a = V DS 100 公式10 V a = V DS 100 Formula 10

到达t3时刻时,功率管漏源电压到达谷底值VDS(valley),且Va<Vsub,所以此时,功率管漏源电压VDS谷底导通控制电路中的迟滞比较器输出低电平,经逻辑控制与驱动电路导通功率管M,实现了VDS谷底导通,由于此时其漏源两端电压VDS降到最低,所以导通功耗也显著下降。At time t3 , the drain-source voltage of the power tube reaches the valley value V DS(valley) , and V a <V sub , so at this time, the output of the hysteresis comparator in the valley-bottom conduction control circuit of the power tube drain-source voltage V DS is low level, the power transistor M is turned on through the logic control and the drive circuit, and the V DS valley conduction is realized. Since the voltage V DS at both ends of the drain and source drops to the minimum at this time, the conduction power consumption is also significantly reduced.

(2)2VCin<Vo (2) 2V Cin < V o

图7是在这种情况下本发明提供的一种能够在不同输入电压情况下降低功率管导通功耗的PFC控制电路的相关波形图。在t0~t1、t1~t2期间,其电压和电流分析与第一种情况相同。但在t2~t3期间,由于2VCin<Vo,所以最后Vds谷底电压变为负的,但由于功率管M的寄生二极管可能会导通,从而将其限制在-0.7V。由于这种情况下,2Vcin-Vo<0,减法器SUB的输出Vsub=0,所以当检测到功率管漏源电压VDS下降到0时,迟滞比较器输出低电平,经逻辑控制与驱动电路导通功率管,实现了VDS零电压导通。从而地降低了功率管M的导通功耗。FIG. 7 is a related waveform diagram of a PFC control circuit provided by the present invention that can reduce the on-power consumption of the power transistor under different input voltage conditions. During t 0 ~ t 1 , t 1 ~ t 2 , its voltage and current analysis is the same as the first case. But during the period from t 2 to t 3 , since 2V Cin <V o , the V ds valley voltage becomes negative at last, but the parasitic diode of the power transistor M may be turned on, thus limiting it to -0.7V. In this case, 2V cin -V o <0, the output V sub of the subtractor SUB =0, so when it is detected that the drain-source voltage V DS of the power tube drops to 0, the hysteresis comparator outputs a low level, and the logic The control and drive circuit turns on the power tube to realize V DS zero-voltage conduction. Thus, the turn-on power consumption of the power transistor M is reduced.

图8是本发明的能够在不同输入电压情况下降低功率管导通功耗的PFC控制电路对输入电压为220V,输出电压为400V的PFC系统进行仿真的仿真波形图。在其纵坐标中,PFC是功率管M的栅驱动信号,VDS是功率管M的漏源电压,iL是电感L上的电流,Vcin是Boost升压电路拓扑结构的输入电压瞬态值,Vo是Boost升压电路拓扑结构的输出电压。在时间t=36.56μs时,Vcin=300V,功率管漏源电压VDS降到谷底值VDS(valley),为200V。且此时2Vcin-Vo=200V,同时功率管的栅驱动信号变为高电平,功率管导通,从而实现了谷底导通,降低了功率管的导通功耗,验证了本发明的可行性。Fig. 8 is a simulation waveform diagram of a PFC control circuit with an input voltage of 220V and an output voltage of 400V simulating by the PFC control circuit of the present invention capable of reducing the on-state power consumption of the power transistor under different input voltage conditions. In its ordinate, PFC is the gate drive signal of the power transistor M, V DS is the drain-source voltage of the power transistor M, i L is the current on the inductor L, and V cin is the input voltage transient of the Boost circuit topology Value, V o is the output voltage of the Boost boost circuit topology. At time t=36.56μs, V cin =300V, the power tube drain-source voltage V DS drops to the valley value V DS(valley) , which is 200V. And at this time 2V cin -V o =200V, at the same time the grid drive signal of the power tube becomes high level, the power tube is turned on, thereby realizing the conduction at the bottom of the valley, reducing the power consumption of the power tube, and verifying the present invention feasibility.

以上所述仅为本发明的优选实例而已,并不限于本发明,对于本领域的技术人员来说,本发明可有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。The above descriptions are only preferred examples of the present invention, and are not limited to the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (3)

1.一种降低功率管导通功耗的PFC控制电路,基于Boost型升压电路的拓扑结构,包括电感L、功率管M、二极管D,电感L的一端与全桥整流器的正输出端连接,电感L的另一端与功率管M的漏极、二极管D的阳极连接,功率管M的源极与全桥整流器的负输出端连接,二极管D的阴极连接负载的一端,负载的另一端连接功率管M的源极;1. A PFC control circuit for reducing the conduction power consumption of the power tube, based on the topology of the Boost type booster circuit, including an inductor L, a power tube M, and a diode D, and one end of the inductor L is connected to the positive output end of the full-bridge rectifier , the other end of the inductor L is connected to the drain of the power tube M and the anode of the diode D, the source of the power tube M is connected to the negative output terminal of the full-bridge rectifier, the cathode of the diode D is connected to one end of the load, and the other end of the load is connected to The source of the power tube M; 其特征在于:设有用于稳定输出和产生功率管M关断信号的电压环电路、用于检测功率管M漏源电压VDS并与谷底电压进行比较,产生功率管M导通控制信号的功率管漏源电压VDS谷底导通控制电路和用于驱动控制功率管M开通和关断的逻辑控制与驱动电路,其中:It is characterized in that it is provided with a voltage loop circuit for stabilizing the output and generating the turn-off signal of the power tube M, and is used to detect the drain-source voltage V DS of the power tube M and compare it with the valley voltage to generate the power of the power tube M turn-on control signal The tube drain-source voltage V DS valley conduction control circuit and the logic control and drive circuit for driving and controlling the power tube M to be turned on and off, wherein: 电压环电路包括电阻R5、R6、补偿电容CCOM、误差放大器、参考电压源、锯齿波发生器及脉冲频率调制比较器,电阻R5的一端与Boost型升压电路拓扑结构中二极管D的阴极连接,电阻R5另一端与误差放大器的反相输入端及电阻R6的一端连接,电阻R6的另一端接地,误差放大器的同相输入端与参考电压源连接,补偿电容CCOM的一端与误差放大器的输出端及脉冲频率调制比较器的反相输入端连接,补偿电容CCOM的另一端接地,脉冲频率调制比较器的同相输入端与锯齿波发生器的输出端连接;The voltage loop circuit includes resistors R5, R6, compensation capacitor C COM , error amplifier, reference voltage source, sawtooth wave generator and pulse frequency modulation comparator, and one end of resistor R5 is connected to the cathode of diode D in the boost circuit topology , the other end of the resistor R5 is connected to the inverting input end of the error amplifier and one end of the resistor R6, the other end of the resistor R6 is grounded, the non-inverting input end of the error amplifier is connected to the reference voltage source, and one end of the compensation capacitor C COM is connected to the output of the error amplifier Terminal and the inverting input end of the pulse frequency modulation comparator are connected, the other end of the compensation capacitor C COM is grounded, and the non-inverting input end of the pulse frequency modulation comparator is connected with the output end of the sawtooth wave generator; 功率管漏源电压VDS谷底导通控制电路包括减法器、比较器、功率管漏源电压VDS采样电路、Boost型升压电路拓扑结构的输入电压Vcin采样电路及Boost型升压电路拓扑结构的输出电压Vo采样电路,功率管漏源电压VDS采样电路的输入端与Boost型升压电路拓扑结构中功率管M的漏极连接,功率管漏源电压VDS采样电路的输出端与比较器的反相输入端连接,比较器的正向输入端与减法器的输出端连接,减法器的正向输入端与Boost型升压电路拓扑结构输入电压Vcin采样电路的输出端连接,Boost型升压电路拓扑结构输入电压Vcin采样电路的输入端与全桥整流器的正向输出端连接,减法器的反相输入端与Boost型升压电路拓扑结构输出电压Vo采样电路的输出端连接,Boost型升压电路拓扑结构输出电压Vo采样电路的输入端与Boost型升压电路拓扑结构中二极管D的阴极连接;Power tube drain-source voltage V DS valley conduction control circuit includes subtractor, comparator, power tube drain-source voltage V DS sampling circuit, input voltage V cin sampling circuit of Boost type boost circuit topology and Boost type boost circuit topology The output voltage V o sampling circuit of the structure, the input terminal of the power tube drain-source voltage V DS sampling circuit is connected with the drain of the power tube M in the topology of the Boost type boost circuit, and the output terminal of the power tube drain-source voltage V DS sampling circuit Connect with the inverting input terminal of the comparator, connect the positive input terminal of the comparator with the output terminal of the subtractor, connect the positive input terminal of the subtractor with the output terminal of the boost circuit topology input voltage V cin sampling circuit , the input terminal of the boost circuit topology input voltage V cin sampling circuit is connected to the positive output terminal of the full-bridge rectifier, the inverting input terminal of the subtractor is connected to the output voltage V o sampling circuit of the boost circuit topology The output terminal is connected, and the input terminal of the Boost type boost circuit topology output voltage V o sampling circuit is connected with the cathode of the diode D in the Boost type boost circuit topology; 逻辑控制与驱动电路包括脉冲发生器、RS触发器及栅极驱动电路,脉冲发生器的输入端与功率管漏源电压VDS谷底导通控制电路中比较器的输出端连接,脉冲发生器的输出端与RS触发器的置位输入端S连接,RS触发器的复位输入端R连接电压环电路中脉冲频率调制比较器的输出端,RS触发器的输出端与栅极驱动电路的输入端连接,栅极驱动电路的输出端连接Boost型升压电路拓扑结构中功率管M的栅极;The logic control and drive circuit includes a pulse generator, an RS flip-flop and a gate drive circuit. The input end of the pulse generator is connected to the output end of the comparator in the power tube drain-source voltage V DS valley conduction control circuit. The output terminal is connected to the set input terminal S of the RS flip-flop, the reset input terminal R of the RS flip-flop is connected to the output terminal of the pulse frequency modulation comparator in the voltage loop circuit, and the output terminal of the RS flip-flop is connected to the input terminal of the gate drive circuit Connect, the output terminal of the grid drive circuit is connected to the gate of the power transistor M in the topology of the Boost type booster circuit; 所述功率管漏源电压VDS采样电路包括电阻R3和R4,电阻R3的一端作为功率管漏源电压VDS采样电路的输入端与Boost升压型电路拓扑结构中功率管M的漏端连接,电阻R3的另一端与电阻R4的一端连接并作为功率管漏源电压VDS采样电路的输出端与比较器的反相输入端连接,电阻R4的另一端接地;The power tube drain-source voltage V DS sampling circuit includes resistors R3 and R4, and one end of the resistor R3 is used as the input end of the power tube drain-source voltage V DS sampling circuit to be connected to the drain end of the power tube M in the Boost boost circuit topology , the other end of the resistor R3 is connected to one end of the resistor R4 and connected to the inverting input of the comparator as the output of the drain-source voltage V DS sampling circuit of the power tube, and the other end of the resistor R4 is grounded; 所述Boost型升压电路拓扑结构输入电压Vcin采样电路包括电阻R1和R2,电阻R1的一端与全桥整流器的正输出端连接,电阻R1的另一端与电阻R2的一端连接并作为Boost型升压电路拓扑结构输入电压Vcin采样电路的输出端与减法器的正向输入端连接,电阻R2的另一端接地;The Boost type step-up circuit topology input voltage V cin sampling circuit includes resistors R1 and R2, one end of the resistor R1 is connected to the positive output end of the full-bridge rectifier, and the other end of the resistor R1 is connected to one end of the resistor R2 as a Boost type Boost circuit topology The output terminal of the input voltage V cin sampling circuit is connected to the positive input terminal of the subtractor, and the other end of the resistor R2 is grounded; 所述Boost型升压电路拓扑结构输出电压Vo采样电路包括电阻R7和R8,电阻R7的一端作为Boost型升压电路拓扑结构输出电压Vo采样电路的输入端与Boost升压型电路拓扑结构中二极管D的阴极连接,电阻R7的另一端与电阻R8一端连接并作为Boost型升压电路拓扑结构输出电压Vo采样电路的输出端与减法器的反相输入端连接。The Boost type boost circuit topology output voltage V o sampling circuit includes resistors R7 and R8, and one end of the resistor R7 is used as the input terminal of the Boost type boost circuit topology output voltage V o sampling circuit and the Boost boost circuit topology The cathode of the middle diode D is connected, and the other end of the resistor R7 is connected to one end of the resistor R8 as a boost circuit topology output voltage V o . The output end of the sampling circuit is connected to the inverting input end of the subtractor. 2.根据权利要求1所述的降低功率管导通功耗的PFC控制电路,其特征在于:所述功率管漏源电压VDS谷底导通控制电路中的比较器是一个迟滞比较器。2. The PFC control circuit for reducing power transistor turn-on power consumption according to claim 1, characterized in that: the comparator in the power transistor drain-source voltage V DS valley bottom conduction control circuit is a hysteresis comparator. 3.根据权利要求1所述的降低功率管导通功耗的PFC控制电路,其特征在于:所述的电阻R1与电阻R2的比值为99:1;电阻R3与电阻R4的比值为99:1,电阻R7与电阻R8的比值为102:1。3. the PFC control circuit that reduces power tube conduction power consumption according to claim 1, is characterized in that: the ratio of described resistance R1 and resistance R2 is 99:1; The ratio of resistance R3 and resistance R4 is 99: 1. The ratio of resistor R7 to resistor R8 is 102:1.
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