CN104022672B - Self adaptation adjustable delay circuit for Sofe Switch ZVT changer - Google Patents

Self adaptation adjustable delay circuit for Sofe Switch ZVT changer Download PDF

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CN104022672B
CN104022672B CN201410294420.5A CN201410294420A CN104022672B CN 104022672 B CN104022672 B CN 104022672B CN 201410294420 A CN201410294420 A CN 201410294420A CN 104022672 B CN104022672 B CN 104022672B
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switch
master switch
door
changer
circuit
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CN104022672A (en
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王玉斌
董彦彦
林意斐
封�波
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Shandong University
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention discloses the self adaptation adjustable delay circuit for Sofe Switch ZVT changer, Sofe Switch ZVT changer, introduce auxiliary switch in main circuit, auxiliary switch turns on prior to corresponding master switch, uses auxiliary switch to control the start time of resonance;Self adaptation adjustable delay circuit includes the master switch zero cross detection circuit for detecting changer master switch voltage over zero and for being automatically adjusted the main and auxiliary switching logic control circuit of delay time between changer auxiliary switch and master switch;Described main and auxiliary switching logic control circuit makes master switch open when master switch voltage is down to zero according to the zero crossing of master switch zero cross detection circuit detection master switch.The present invention is automatically adjusted the delay time between auxiliary switch and master switch, make master switch open just to occur when master switch voltage is down to zero, achieve the Self Adaptive Control of ZVT, make changer Sofe Switch high-efficiency operation in full load excursion.

Description

Self adaptation adjustable delay circuit for Sofe Switch ZVT changer
Technical field
The present invention relates to a kind of self adaptation adjustable delay circuit for Sofe Switch ZVT changer, particularly relate to that a kind of bridge-type is soft opens Close the self adaptation adjustable delay circuit of ZVT inverter.
Background technology
High power density and miniaturization are one of development trends of converters, and high frequency realizes this target Inevitable choice.High switching loss that traditional hard switching causes with the raising of switching frequency, high voltage and current stress, make conversion Device efficiency reduces, reliability decrease, thus limits miniaturization and the lightweight of changer.Soft switch technique is by introducing resonance Circuit, switching process to switching device are controlled so that it is switch under no-voltage or zero current condition, thus be obviously reduced Even eliminate switching loss.Therefore, soft switch technique is converters miniaturization and light-weighted inevitable requirement.Soft open Close the Typical Representative that ZVT changer is current soft switch circuit.
When Sofe Switch ZVT changer works, auxiliary switch is open-minded prior to corresponding master switch, the time opened in advance generally by Fixing delay circuit realizes.When the excursion of load current size is wider, this method is it is difficult to ensure that the ZVS of master switch Performance.As a example by the most popular coupling inductance Sofe Switch ZVT inverter, one bridge topology is as shown in Figure 1.If used Fixing delay time, when the load electric current is small, in delay time, master switch quickly reaches zero-voltage state, but to wait until to prolong Time the time to opening, effective duty cycle may be caused to lose;And load current bigger time, due to coupling inductance electric current rise To load current and the overlong time of beginning resonance, master switch is caused to reach the time lengthening of no-voltage, more than fixing time delay Time, when delay time to, master switch is opened because the most non-resonance of the voltage at its two ends is to zero, therefore cannot realize ZVS.For Solution the problems referred to above, it has been proposed that and change fixing time delay into adjustable delays time to control, basic ideas are according to load current Size and Orientation regulates delay time, but load current size and Orientation is difficult to judge when zero crossing, and it is dry to there is noise Disturb and the biasing problem of current regulating circuit.
Summary of the invention
For solving the deficiency that prior art exists, the invention discloses the self adaptation adjustable delay electricity for Sofe Switch ZVT changer Road, this circuit is automatically adjusted the delay time between auxiliary switch and master switch, makes master switch open just and occurs at master switch electricity In the moment of pressure drop to zero, it is achieved that the Self Adaptive Control of ZVT, make changer Sofe Switch in full load excursion high Efficiency is run.
For achieving the above object, the concrete scheme of the present invention is as follows:
Draw in the self adaptation adjustable delay circuit of Sofe Switch ZVT changer, the main circuit of described Sofe Switch ZVT changer Entering auxiliary switch, auxiliary switch turns on prior to corresponding master switch, uses auxiliary switch to control the start time of resonance;
Described self adaptation adjustable delay circuit includes the master switch zero cross detection circuit for detecting changer master switch voltage over zero And for being automatically adjusted the main and auxiliary switching logic control circuit of delay time between changer auxiliary switch and master switch;Described master, Auxiliary switch logic control circuit makes master switch open at master switch electricity according to the zero crossing of master switch zero cross detection circuit detection master switch The moment of pressure drop to zero.
The master switch of described changer and auxiliary switch are gated transistor IGBT or field effect transistor M OSFET.
Described master switch zero cross detection circuit includes fast recovery diode and high speed voltage comparator, the negative electrode of fast recovery diode and The colelctor electrode of master switch connects, and the anode of fast recovery diode and the inverting input of high speed voltage comparator connect, high speed voltage The reference ground of comparator connects with the emitter stage of master switch, and the in-phase input end of high speed voltage comparator connects with resistor network.
The in-phase input end of described high speed voltage comparator connects with resistor network composition hysteresis loop comparator, on described hysteresis loop comparator Limit Uref+It is given by:
U ref + = R 2 | | R 3 R 1 + R 2 | | R 3 × V + - R 1 | | R 3 R 2 + R 1 | | R 3 × V - - - - ( 1 )
Hysteresis loop comparator lower limit Uref-It is given by:
U ref - = R 2 | | R 3 R 1 + R 2 | | R 3 × V + - ( R 1 | | R 3 R 2 + R 1 | | R 3 + R 1 | | R 2 R 3 + R 1 | | R 2 ) × V - - - - ( 2 )
Upper limit U of hysteresis loop comparatorref+Hysteresis loop comparator lower limit Uref-The return difference Δ U constituted is:
ΔU = U ref + - U ref - = R 1 | | R 2 R 3 + R 1 | | R 2 × V - - - - ( 3 )
Wherein, R1R2R3For constituting the resistance of resistor network, V+For the positive supply voltage of high speed voltage comparator, V-For at a high speed The negative supply voltage of voltage comparator.
Described main and auxiliary switching logic control circuit includes that first prolongs with door or door, dead band delay circuit and reset with door and second Time circuit, described first connects with the output of the high speed voltage comparator in master switch zero cross detection circuit with an input of door, First connects with the output of door with another input and second of door, second and an input of door and control circuit output Pwm signal connects, and second connects with by pwm signal output after the delay circuit of dead band with another input of door, and first With the outfan of door with or an input of door connect, or another input of door with by second with the output of door through reset delay Output after circuit connects, or the output signal of door is as the control signal of master switch, second with the output of door as auxiliary switch Control signal.
Operation principle: the pwm switching signal exported by control circuit, through Dead Time (for avoiding upper and lower two Guan Zhi of same bridge Logical and the time delay that introduces) to go to control auxiliary switch open-minded for control signal after time delay.When opening of rear master switch opened by auxiliary switch Carve and then regulated, in the zero cross detection circuit of master switch, when the electricity at master switch two ends by the voltage adaptive at detection master switch two ends Pressure drop is to reference voltage Uref-, high speed voltage comparator output switching activity uprises, through first with door and or master switch control signal behind the door Uprise, now can control master switch no-voltage open-minded.Thus complete the Self Adaptive Control to master switch ZVT.
Beneficial effects of the present invention:
The present invention is automatically adjusted the delay time between auxiliary switch and master switch, makes master switch open just and occurs at master switch electricity In the moment of pressure drop to zero, it is achieved that the Self Adaptive Control of ZVT, make changer Sofe Switch in full load excursion high Efficiency is run.
The results show, when master switch turns off, collection radio pressure is not the most obvious crosses punching, and voltage stress is the least, it is seen then that soft open Close while reducing switching loss, improving efficiency, also optimize the running environment of switch, reduce electromagnetic interference.Work as output During by underloading to specified change, the efficiency surveying this Sofe Switch ZVT inverter maintains about 98%.
Accompanying drawing explanation
Fig. 1 is coupling inductance Sofe Switch ZVT inverter one bridge topological diagram;
Fig. 2 is control signal sequential chart and main oscillogram;
Fig. 3 is master switch S in the present invention1Zero cross detection circuit figure;
Fig. 4 is major-minor switching logic control circuit figure in the present invention;
Fig. 5 is present invention experimental waveform figure (Io=0.3A) when coupling inductance Sofe Switch ZVT inverter control;
Fig. 6 is present invention experimental waveform figure (Io=7.6A) when coupling inductance Sofe Switch ZVT inverter control.
Detailed description of the invention:
The present invention is described in detail below in conjunction with the accompanying drawings:
In the application, Sofe Switch ZVT changer is as a example by coupling inductance Sofe Switch ZVT inverter, and one bridge topology is such as Fig. 1 institute Show.S in Fig. 11、S2It is respectively the upper and lower master switch of same bridge;Sx1、Sx2It is respectively S1、S2Auxiliary switch;Tr1、 Tr2It is two coupling inductances, Lm1、Lr1It is respectively Tr1Magnetizing inductance and leakage inductance, Lm2、Lr2It is respectively Tr2Excitation electricity Sense and leakage inductance;C1、C2For resonant capacitance;Dx1-Dx6For booster diode.Master switch and auxiliary switch all select IGBT to manage. Two set topologys identical with Fig. 1 i.e. may make up single-phase H bridge Sofe Switch ZVT inverter, wherein master switch bridge midpoint, The exchange output of inverter is produced after LC low pass filter filters.
Fig. 2 is the main and auxiliary control signal helping switch and main voltage and current waveform, and wherein PWM is from controller Pulse-width signal;ugs1、ugs2、ugsx1、ugsx2It is respectively master switch S1、S2With auxiliary switch Sx1、Sx2Control signal; I0It is load current, can approximate when analyzing Sofe Switch process and regard constant as;iLrIt it is resonance current;uce1For master switch S1On electricity Pressure;uLm1、iLm1It is respectively Tr1Voltage and current on magnetizing inductance.In order to explain the self adaptation adjustable delay circuit of the present invention, First combine Fig. 2 and the operation principle of coupling inductance Sofe Switch ZVT inverter is described.
Assume circuit original state: t0Before moment, S1It is in off-state, S2It is in on-state (by the sense of current in figure, actually D2Conducting).
1) mode [t0~t1]: t0Moment, master switch S2Zero voltage turn-off, load current I0Through anti-paralleled diode D2Afterflow.
2) mode [t1~t2]: t1Moment, master switch S1Auxiliary switch Sx1Controlled open-minded, meanwhile, diode Dx3Also open Begin to turn on, make coupling inductance Tx1In electric current iLrLinearly increasing, exciting current iLm1Start from scratch foundation.
3) mode [t2~t3]: t2Moment, electric current iLrRise to and load current I0Equal, hereafter leakage inductance and resonant capacitance C1、 C2Start resonance, iLrContinue to increase, C2Charging, C1Electric discharge.Therefore S1Both end voltage uce1Begin to decline, in like manner S2Two ends Voltage uce2Begin to ramp up.
4) mode [t3~t4]: t3Moment, C2Charging voltage rise to DC voltage Udc, C1Then discharging into voltage is zero, i.e. uce1Drop to zero, now control S1No-voltage is open-minded, resonance current iLrBegin to decline.
5) mode [t4~t5]: t4Moment, booster diode Dx3Naturally turn off, resonance current iLrDrop to exciting current value iLm1, Due to the voltage u on hereafter windingLm1It is zero, therefore this stage exciting current value iLm1Keep constant.
6) mode [t5~t6]: t5Moment, auxiliary switch Sx1Controlled shutdown, diode Dx4Afterflow is open-minded, exciting current iLm1Open Begin to reset.Because resetting voltage is equal to DC voltage Udc, therefore iLm1Reset-to-zero rapidly.
7) mode [t6~t7]: t6Moment, exciting current iLm1Reset-to-zero, diode Dx4Naturally turn off, this stage master switch S1Flow through whole load current.
8) mode [t7~t8]: t7Moment, S1Zero voltage turn-off, load current I0Then flow through C1、C2, i.e. to C1Charging, C2 Electric discharge, uce1Begin to ramp up, uce2Begin to decline.
9) mode [t8~t9]: t8Moment, C1Charge complete, terminal voltage uce1Rise to Udc。C2Discharge off, uce2Drop to Zero, load current is by diode D2Afterflow.
10) mode [t9~t0]: t9Moment S2No-voltage is open-minded, it is contemplated that the direction of load current, actually from t8After moment, Always D2Afterflow undertakes whole load current, and in circuit, each amount does not changes.S during this periodx2Controlled open-minded, but because of this There is not resonance, that is S in one stagex2Though having opened but no current to flow through, belong to zero current turning-on.
When load current is reverse, operation principle and waveform are similar to above, are not repeating.
Explained below how to realize ZVS Sofe Switch by self adaptation adjustable delay circuit.Without loss of generality, with S1As a example by explanation. Because of resonant capacitance C1With S1Parallel connection, S1Always can realize zero voltage turn-off, therefore, following Main Analysis how adjust by self adaptation Joint delay time makes S1Realize no-voltage open-minded.As it has been described above, at mode [t2~t3], as electric current iLrRise to and load current I0 After, leakage inductance and resonant capacitance C1、C2Start resonance, iLrContinue to increase, C2Charging, C1Electric discharge.That is t2Moment, uce1 Begin to decline until t3Moment is reduced to zero.If now controlling S1Open-minded, then S1It is no-voltage open-minded.
Fig. 3 is the zero cross detection circuit of master switch in the present invention, without loss of generality, with S1As a example by illustrate, its zero cross detection circuit By high speed voltage comparator A1, fast recovery diode VD1, and resistance R1、R2And R3Composition, wherein VD1Negative electrode and The colelctor electrode of master switch connects, VD1Anode and A1Inverting input connect, A1Reference ground and the emitter stage phase of master switch Connect, A1In-phase input end and R1-R3The resistor network of composition connects.So connect, A1Inverting input can detect master Switch S1Collection emitter voltage uce1, in-phase input end is reference voltage Uref.In order to prevent uce1Testing circuit is attached at zero crossing Near shake, causing switching noise, high speed voltage comparator is designed to hysteresis loop comparator, A shown in Fig. 3 by the present invention1Homophase Input and R1-R3The resistor network of composition constitutes hysteresis loop comparator.
Hysteresis loop comparator upper limit Uref+It is given by:
U ref + = R 2 | | R 3 R 1 + R 2 | | R 3 × V + - R 1 | | R 3 R 2 + R 1 | | R 3 × V - - - - ( 1 )
Hysteresis loop comparator lower limit Uref-It is given by:
U ref - = R 2 | | R 3 R 1 + R 2 | | R 3 × V + - ( R 1 | | R 3 R 2 + R 1 | | R 3 + R 1 | | R 2 R 3 + R 1 | | R 2 ) × V - - - - ( 2 )
Return difference Δ U is:
ΔU = U ref + - U ref - = R 1 | | R 2 R 3 + R 1 | | R 2 × V - - - - ( 3 )
Return difference Δ U typically may be designed to about 2V, and zero cross detection circuit can be avoided in the shake of near zero-crossing point.When uce1>Uref+Time, hysteresis loop comparator output logic low;uce1≤ Uref-Time, hysteresis loop comparator output switching activity becomes logic high electricity Flat, show master switch S1Collection emitter voltage zero passage.
Fig. 4 is master switch S in the present invention1、S2With auxiliary switch Sx1、Sx2Logic control circuit, without loss of generality, still with S1 And Sx1As a example by illustrate: by two input with door AND1And AND2, two input or door OR1, dead band time delay Y1And reset delay Y2Composition, wherein with door AND1An input and master switch S1High speed voltage comparator A in zero cross detection circuit1's Output connect, another input with door AND2Output connect, with door AND2An input and control circuit export Pwm signal connect, another input with by pwm signal through dead band time delay Y1After output connect, or door OR1One Individual input with door AND1Output connect, another input with by AND2Output through reset delay Y2After output phase Connect, or door OR1Output signal as control signal u of master switchgs1, with door AND2Output as the control of auxiliary switch Signal u processedgsx1.So connect, control signal u of major-minor switch as shown in Figure 2 can be producedgs1、ugsx1Deng.
Implementation brief introduction is as follows: the pwm switching signal exported by control circuit, through Dead Time (for avoiding on same bridge The time delay that lower two pipes are straight-through and introduce) control signal u after time delaygsx1Go to control auxiliary switch Sx1Open (in corresponding diagram 2 t1Moment).Sx1Open rear master switch S1When open then by detection S1The voltage u at two endsce1Automatic adjusument, by Fig. 3 The zero cross detection circuit of S1 understands, and works as uce1It is down to reference voltage Uref, comparator output switching activity uprises, warp and door AND1With or Door OR1Rear ugs1Uprise, now can control S1No-voltage opens the (t in corresponding diagram 23Moment).Thus complete to open main Close the Self Adaptive Control of ZVT.
Fig. 5, Fig. 6 are present invention experimental waveforms when coupling inductance Sofe Switch ZVT inverter control different loads electric current, Wherein load current Io=0.3A in Fig. 5, load current Io=7.6A in Fig. 6.Experiment condition is: inverter direct current input electricity Pressure is for 400V, and inverter output is followed by an adjustable resistance as load through LC low pass filter, tests Sofe Switch ZVT inverse Become the performance of device.Com-parison and analysis Fig. 5 and Fig. 6, it can be clearly seen that coupling inductance resonance current peak value has with load current size Closing, load current is the biggest, and resonance current peak value is the highest, and the time that master switch voltage is down to zero is the longest;Otherwise it is the shortest.But Owing to have employed self adaptation adjustable delay method, regardless of load current size, master switch always can realize no-voltage (ZVS) Switch, experimental waveform matches with theory analysis.And, when master switch turns off, collection radio pressure is the most obvious crosses punching, voltage Stress is the least, it is seen then that Sofe Switch, while reducing switching loss, improving efficiency, also optimizes the running environment of switch, fall Low electromagnetic interference.When output is by underloading to specified change, the efficiency surveying this Sofe Switch ZVT inverter maintains 98% left side The right side, this is hard switching circuit and uses the ZVT Sofe Switch of constant time lag method to realize.
Although the detailed description of the invention of the present invention is described by the above-mentioned accompanying drawing that combines, but not limit to scope System, one of ordinary skill in the art should be understood that on the basis of technical scheme, and those skilled in the art need not pay Go out various amendments or deformation that creative work can make still within protection scope of the present invention.

Claims (5)

1. for the self adaptation adjustable delay circuit of Sofe Switch ZVT changer, being adapted to regulate bridge-type two level converter, it is special Levying and be, introduce auxiliary switch in the main circuit of described Sofe Switch ZVT changer, auxiliary switch turns on prior to corresponding master switch, Auxiliary switch is used to control the start time of resonance;Described self adaptation adjustable delay circuit includes for detecting changer master switch electricity Press through the master switch zero cross detection circuit of zero point and the conducting of the ON time and master switch for being automatically adjusted changer auxiliary switch The main and auxiliary switching logic control circuit of delay time between time;Described main and auxiliary switching logic control circuit is according to master switch mistake The zero crossing of zero testing circuit detection master switch makes master switch open when master switch voltage is down to zero;
Described master switch zero cross detection circuit includes fast recovery diode and high speed voltage comparator, the negative electrode of fast recovery diode and The colelctor electrode of master switch connects, and the anode of fast recovery diode and the inverting input of high speed voltage comparator connect, high speed voltage The reference ground of comparator connects with the emitter stage of master switch, and the in-phase input end of high speed voltage comparator connects with resistor network;
The in-phase input end of described high speed voltage comparator connects with resistor network composition hysteresis loop comparator;
Described main and auxiliary switching logic control circuit includes that first prolongs with door or door, dead band delay circuit and reset with door and second Time circuit, described first connects with the output of the high speed voltage comparator in master switch zero cross detection circuit with an input of door, First connects with the output of door with another input and second of door, second and an input of door and control circuit output Pwm signal connects, and second connects with by pwm signal output after the delay circuit of dead band with another input of door, and first With the outfan of door with or an input of door connect, or another input of door with by second with the output of door through reset delay Output after circuit connects, or the output signal of door is as the control signal of master switch, second with the output of door as auxiliary switch Control signal.
2. the self adaptation adjustable delay circuit for Sofe Switch ZVT changer as claimed in claim 1, is characterized in that, described The master switch of changer and auxiliary switch are gated transistor IGBT or field effect transistor M OSFET.
3. the self adaptation adjustable delay circuit for Sofe Switch ZVT changer as claimed in claim 1, is characterized in that, institute State upper limit U of hysteresis loop comparatorref+It is given by:
U r e f + = R 2 | | R 3 R 1 + R 2 | | R 3 × V + - R 1 | | R 3 R 2 + R 1 | | R 3 × V - - - - ( 1 )
Wherein, R1、R2、R3For constituting the resistance of resistor network, V+For the positive supply voltage of high speed voltage comparator, V_For height The negative supply voltage of speed voltage comparator.
4. the self adaptation adjustable delay circuit for Sofe Switch ZVT changer as claimed in claim 3, is characterized in that, stagnant Return comparator lower limit Uref-It is given by:
U r e f - = R 2 | | R 3 R 1 + R 2 | | R 3 × V + - ( R 1 | | R 3 R 2 + R 1 | | R 3 + R 1 | | R 2 R 3 + R 1 | | R 2 ) × V - - - - ( 2 )
Wherein, R1、R2、R3For constituting the resistance of resistor network, V+For the positive supply voltage of high speed voltage comparator, V_For height The negative supply voltage of speed voltage comparator.
5. the self adaptation adjustable delay circuit for Sofe Switch ZVT changer as claimed in claim 4, is characterized in that, stagnant Return upper limit U of comparatorref+With hysteresis loop comparator lower limit Uref-The return difference Δ U constituted is:
Δ U = U r e f + - U r e f - = R 1 | | R 2 R 3 + R 1 | | R 2 × V - - - - ( 3 )
Wherein, R1、R2、R3For constituting the resistance of resistor network, V+For the positive supply voltage of high speed voltage comparator, V_For height The negative supply voltage of speed voltage comparator.
CN201410294420.5A 2014-06-25 2014-06-25 Self adaptation adjustable delay circuit for Sofe Switch ZVT changer Active CN104022672B (en)

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