JP2006216205A - Sample and hold circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly accurate sample and hold circuit, capable of preventing generation of wrong voltage due to the clock field-through of the switching operation of a switch. <P>SOLUTION: During a sampling period, a switching S1 and a switching circuit S4 are turned ON, while a switch S3 is turned OFF. During switching period, the switching circuit S4 is first switched to OFF state, the switch S1 is switched to OFF state, and then the switch S3 is switched to ON state. Transistors Q1 and Q2 are equal in size, and gate/drain capacitances Cn and Cp are equal. Thus, by properly setting the bias voltage TPH, when the switches S4a and S4b are switched to OFF states, charges Qn and Qp stored in the gate/drain capacitances Cn and Cp offset each other by clock field-through, so as not to be stored in a capacitor C1. During holding period, the switch S1 and the switch circuit S4 are switched to OFF states, and the switch S3 is switched to ON state. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a sample and hold circuit.

In order to convert a continuously changing analog input signal into a digital signal, the sample hold circuit takes out the input signal as a sample for a certain period of time (sampling, sampling), and holds (holds) the voltage of the sampled input signal constant. This circuit outputs from the output terminal.
Sample hold circuits are widely used in electronic circuits, such as being connected to the front stage of an A / D converter or connected to output terminals of various sensors.

Conventionally, a sample hold circuit including a first to a fourth switch circuit, a first capacitor, a second capacitor, and an operational amplifier has been disclosed (see Patent Document 1).
One end of the first switch circuit is connected to the input end of the sample and hold circuit, and the other end is connected to one end of the first capacitor.
The second switch circuit has one end connected to a reference voltage source end and the other end connected to one end of a second capacitor having a capacitance value equal to that of the first capacitor, and is synchronized with the rise of the first switch circuit. And operates with a small duty cycle.
The operational amplifier has an inverting input terminal connected to the other end of the first capacitor, and a normal rotation input terminal connected to one end of the second capacitor.
The third switch circuit is inserted between the output terminal of the operational amplifier and the first capacitor, and performs the reverse operation of the first switch circuit.
The fourth switch circuit is inserted between the inverting input terminal and the output terminal of the operational amplifier and operates in phase with the second switch circuit.
JP-A-2-202720 (pages 1-5, FIGS. 1-5)

In an electronic circuit, a semiconductor type is used for a switch circuit that performs a high-speed switching operation. Among semiconductor types, a CMOS (Complementary MOS) type transmission gate (analog switch) is mainly used.
The CMOS type transmission gate has a feature that the leakage current, the offset voltage, the on-resistance are small, and the occupied area (layout area) on the semiconductor chip is small when a monolithic IC (Integrated Circuit) is formed.

Patent Document 1 also discloses a CMOS transmission gate as a specific example of the switch circuit.
In Patent Document 1, the transmission gate is described as a “transfer gate”.

  In a CMOS type transmission gate, when switching from an on state to an off state, a phenomenon occurs in which charge flows through a parasitic capacitance between the electrodes of the two transistors constituting the CMOS type transmission gate (between the gate and drain and between the gate and source). . This phenomenon is called clock field through.

  In the technique of Patent Document 1, when the second switch circuit and the second capacitor are omitted, when the fourth switch circuit is switched from the on state to the off state, the CMOS transmission that constitutes the fourth switch circuit The injected charge due to the clock field through of the gate is accumulated in the first capacitor, and an error voltage due to the injected charge is generated between the input voltage and the output voltage of the sample hold circuit.

Therefore, in the technique of Patent Document 1, the second switch circuit and the second capacitor are provided, and when the second switch circuit is switched from the on state to the off state, the CMOS type transmission gate constituting the second switch circuit is provided. Charges injected by the clock field through are accumulated in the second capacitor.
Here, the capacitance values of the second capacitor and the first capacitor are equal, and the second switch circuit and the fourth switch circuit are simultaneously switched from the on state to the off state.

Therefore, the first injected charge due to the clock field through of the fourth switch circuit flows into the inverting input terminal (inverting input terminal) of the operational amplifier, and at the same time, the second charge due to the clock field through of the second switch circuit. The injected charge flows into the normal input terminal (non-inverting input terminal) of the operational amplifier.
Here, since the first injected charge and the second injected charge are equal, the error voltage due to the first injected charge and the error voltage due to the second injected charge cancel each other, and the input voltage and the output voltage of the sample hold circuit are equal. Become.

However, the technique of Patent Document 1 has the following problems.
[First problem]
In the technique of Patent Document 1, in order to completely cancel the error voltage described above, the voltage of the reference voltage source and the voltage at the output terminal of the operational amplifier (the output voltage of the sample hold circuit) must be the same voltage. .
However, since the voltage of the reference voltage source and the output voltage are actually different, it is difficult to completely cancel the above error voltage, and the error voltage remaining without being canceled is the input voltage of the sample hold circuit. There is a problem that it becomes an error voltage between the output voltage and the output voltage.

  Even when other types of semiconductor switch circuits (for example, diode bridge type, bipolar transistor type, etc.) are used in addition to the CMOS type transmission gate, errors due to clock field through of the switch circuit are the same as described above. A voltage is generated.

[Second problem]
When the capacitor (capacitance) is monolithic IC, the layout area on the semiconductor chip is larger than that of the MOS transistor, and a large layout area is required to obtain a sufficient hold time.
The technique of Patent Document 1 has a problem that when the sample-and-hold circuit is formed as a monolithic IC by the amount of the second capacitor, the layout area on the semiconductor chip increases, which hinders the area reduction of the semiconductor chip.

The present invention has been made to solve the above-described problem, and an object of the present invention is to provide a highly accurate sample-and-hold circuit capable of preventing the occurrence of an error voltage due to clock field through of switch switching operation. It is to provide.
Another object of the present invention is to provide a sample and hold circuit capable of achieving high integration by reducing a layout area on a semiconductor chip when a monolithic IC is formed.

The invention described in claim 1
In the sample hold circuit that samples the input voltage applied to the input terminal, holds the sampled input voltage and outputs it from the output terminal,
A capacitor charged by the input voltage;
A first switch connected between the input terminal and the first electrode of the capacitor;
A second switch connected between the output terminal and the first electrode of the capacitor;
A differential amplifier having an inverting input terminal connected to the second electrode of the capacitor;
A reference voltage source for applying a reference voltage to a non-inverting input terminal of the differential amplifier;
A first output circuit that amplifies the output voltage of the differential amplifier and outputs the amplified output voltage from the output terminal;
A second output circuit that amplifies the output voltage of the differential amplifier and outputs the amplified output voltage to the inverting input terminal of the differential amplifier;
A third switch connected between the differential amplifier and the second output circuit;
An operational amplifier is composed of the differential amplifier, the first output circuit, and the second output circuit,
The second output circuit includes first and second transistors of different conductivity types connected in series,
The third switch connects the output terminal of the differential amplifier and the input side of the first transistor, and applies a bias voltage to the second transistor to turn it on when the third switch is turned on.
The third switch turns off both the first transistor and the second transistor during the off operation,
Technically, the third switch operates in the same phase in synchronization with the ON operation of the first switch, and the second switch operates in the reverse phase in synchronization with the ON operation of the first switch.

The invention described in claim 2
The sample and hold circuit according to claim 1,
The first switch repeats on / off operation at a constant duty cycle,
The duty cycle of the on / off operation of the third switch is technically characterized by being set smaller than the duty cycle of the first switch by a first delay time.

The invention according to claim 3
The sample and hold circuit according to claim 2,
The duty cycle of the on / off operation of the second switch is technically characterized by being set smaller than the duty cycle of the first switch by a second delay time.

The invention according to claim 4
The sample and hold circuit according to any one of claims 1 to 3,
A technical feature is that a bias voltage generation circuit is provided that generates the bias voltage applied to the second transistor based on an output voltage of the differential amplifier.

The invention described in claim 5
In the sample hold circuit according to any one of claims 1 to 4,
The second output circuit is a CMOS buffer circuit;
The first transistor is an N-channel MOS transistor;
The second transistor is a P-channel MOS transistor;
The third switch connects the output terminal of the differential amplifier and the gate of the first transistor, and applies a bias voltage to the gate of the second transistor to turn on the third switch.
The third switch is characterized by applying a low voltage to the gate of the first transistor and turning it off by applying a high voltage to the gate of the second transistor when the third switch is turned off.

The invention described in claim 6
In the sample hold circuit according to any one of claims 1 to 4,
The second output circuit is a CMOS buffer circuit;
The first transistor is a P-channel MOS transistor;
The second transistor is an N-channel MOS transistor;
The third switch connects the output terminal of the differential amplifier and the gate of the first transistor, and applies a bias voltage to the gate of the second transistor to turn on the third switch.
The third switch is characterized by applying a high voltage to the gate of the first transistor and turning it off by applying a low voltage to the gate of the second transistor when the third switch is turned off.

(Claim 1)
In the sample period of the first aspect of the invention, the first switch and the third switch are controlled to be switched on and the second switch is switched off.
The input voltage is applied to the capacitor via the first switch in the on state, and the capacitor is charged by the input voltage.

At this time, since the third switch is in the ON state, negative feedback is applied to the operational amplifier, and the voltage (differential input voltage) between the input terminals of the operational amplifier (differential amplifier) becomes zero due to an imaginary short. Therefore, the voltage of the inverting input terminal becomes equal to the voltage (reference voltage) of the non-inverting input terminal.
However, when the operational amplifier has an input offset voltage, the voltage at the inverting input terminal is a value obtained by adding the input offset voltage to the reference voltage.
Therefore, the charge accumulated in the capacitor during the sample period becomes a value obtained by multiplying the value obtained by subtracting the input voltage from the value obtained by adding the input offset voltage to the reference voltage, and the capacitance of the capacitor.

Next, in the switching period, the first switch and the third switch are switched to the off state, and the second switch is switched to the on state.
At this time, when the third switch is switched from the on operation to the off operation, an injection charge is generated due to clock field through of the semiconductor switch circuit constituting the third switch.
The injected charge due to the clock field through of the third switch is accumulated in the interelectrode capacitance of each transistor of the second output circuit.

Here, the input side voltage of the second transistor when the third switch is on is a bias voltage, and the difference voltage between the bias voltage and the input side voltage of the second transistor when the third switch is off is the first voltage. One differential voltage (ΔVp) is assumed.
The input side voltage of the first transistor when the third switch is on is the output voltage of the differential amplifier, and the difference between the output voltage and the input side voltage of the first transistor when the third switch is off. The voltage is defined as a second differential voltage (ΔVn).

Here, if each transistor is made the same transistor size, the capacitance between the electrodes of each transistor 2 becomes equal.
Therefore, by appropriately setting the bias voltage, if the first difference voltage and the second difference voltage are made substantially equal, the charges accumulated in the interelectrode capacitance of each transistor can be made almost equal. Cancel each other and disappear, and the charge can be prevented from being accumulated in the capacitor.

In the hold period (output period), the first switch and the third switch are controlled to be switched off and the second switch is switched on.
The charge accumulated in the capacitor during the hold period is multiplied by the capacitance of the capacitor by the value obtained by subtracting the output voltage of the first output circuit (the output voltage of the sample hold circuit) from the value obtained by adding the input offset voltage to the reference voltage. It becomes the value.

Since the charge accumulated in the capacitor in the sample period and the charge accumulated in the capacitor in the hold period are held and the same, the input voltage and the output voltage are also equal.
The input offset voltage of the operational amplifier is also canceled.

  Therefore, according to the first aspect of the present invention, it is possible to prevent an error voltage due to the clock field through of the third switch from being generated between the input voltage and the output voltage of the sample hold circuit, and to input the operational amplifier. Since an error voltage due to the offset voltage is prevented and the input voltage and the output voltage can be made equal, a highly accurate sample-and-hold circuit can be realized.

  According to the first aspect of the present invention, even when the reference voltage of the reference voltage source is different from the output voltage, the error voltage due to the clock field through of the third switch does not occur, and the clock field through Therefore, the first problem of the technique of Patent Document 1 can be solved.

  In addition, according to the first aspect of the present invention, only the capacitor corresponding to the first capacitance of Patent Document 1 is provided, and it is not necessary to provide the capacitor corresponding to the second capacitance of Patent Document 1. When the circuit is formed as a monolithic IC, the layout area on the semiconductor chip can be reduced to achieve high integration, and the second problem of the technique of Patent Document 1 can be solved.

(Claim 2)
According to the invention of claim 2, by setting the first delay time, the third switch is switched from the on state without being affected by the fluctuation of the input voltage when the first switch is switched from the on state to the off state. Since it is possible to switch to the off state, the input voltage at the time when the third switch is switched to the off state can be sampled and held with high accuracy.

The first delay time may be set by experimentally finding an optimum value by cut-and-try. For example, the first delay time may be set to 1/5 of the time during which the first switch is on. .
In this case, if the duty cycle of the on / off operation of the first switch is 50%, the duty cycle of the on / off operation of the third switch is 40%, which is smaller by the first delay time.

(Claim 3)
According to the invention of claim 3, by setting the second delay time, the second switch is switched to the on state after the first switch is completely switched to the off state, and the first switch and the second switch are simultaneously Since it is possible to reliably prevent the ON state, the input voltage can be accurately sampled and held.

The second delay time may be set by experimentally finding an optimum value by cut-and-try, for example, by setting it to 1/5 of the time during which the first switch is on. .
In this case, if the duty cycle of the on / off operation of the first switch is 50%, the duty cycle of the on / off operation of the second switch is 40%, which is smaller by the second delay time.

(Claim 4: Corresponds to the second embodiment or the fourth embodiment)
According to the invention of claim 4, by generating the bias voltage based on the output voltage of the differential amplifier, the bias voltage that makes the difference voltages (ΔVn, ΔVp) of the invention of claim 1 equal can be easily obtained. And since it can set reliably, the effect | action and effect of invention of Claim 1 can be obtained still more reliably.

(Claim 5: Corresponds to the first embodiment or the second embodiment)
In the invention of claim 5, the second output circuit is composed of a high-performance CMOS buffer circuit. Compared with other types of buffer circuits (for example, buffer circuits using bipolar transistors), the CMOS type buffer circuit has a simple configuration and high performance, and the layout area on the semiconductor chip in the case of a monolithic IC is large. Since it is small, the operation and effect of the inventions of claims 1 to 4 can be obtained more reliably.

(Claim 6: Corresponds to the third embodiment or the fourth embodiment)
Also in the invention of claim 6, the same operation and effect as those of the invention of claim 5 can be obtained.

(Explanation of terms)
The correspondence between the constituent elements described in [Means for Solving the Problems] described above and the constituent members described in [Best Mode for Carrying Out the Invention] described below is as follows. .

The “first switch” corresponds to the switch S1.
The “second switch” corresponds to the switch S3.
The “third switch” corresponds to the switch circuit S4 (switches S4a and S4b).
The “first output circuit” corresponds to the output circuit OCb.
The “second output circuit” corresponds to the output circuit OCa.

The “first transistor” corresponds to the transistor Q1 in the sample hold circuit 10 of the first embodiment or the sample hold circuit 20 of the second embodiment, and the sample hold circuit 30 of the third embodiment or the sample hold of the fourth embodiment. In the circuit 40, it corresponds to the transistor Q2.
The “input side of the first transistor” corresponds to the gate of the transistor Q1 or the transistor Q2.

The “second transistor” corresponds to the transistor Q2 in the sample and hold circuit 10 of the first embodiment or the sample and hold circuit 20 of the second embodiment, and the sample and hold circuit 30 of the third embodiment or the sample and hold of the fourth embodiment. In the circuit 40, it corresponds to the transistor Q1.
The “first delay time” corresponds to the delay time ta.
The “second delay time” corresponds to the delay time tb.

  Hereinafter, embodiments embodying the present invention will be described with reference to the drawings. In each embodiment, the same constituent members are denoted by the same reference numerals, and redundant description of the same content is omitted.

(First embodiment)
FIG. 1 is a circuit diagram showing a sample and hold circuit 10 of the first embodiment.
The sample and hold circuit 10 includes an unbalanced operational amplifier (op-amp) OP, switches S1 and S3, a reference voltage source VB, a capacitor C1, an input terminal Vin, an output terminal Vout, and a control circuit 11.
The unbalanced operational amplifier OP includes an unbalanced differential amplifier DA, output circuits OCa and OCb, terminals AOUTa and AOUTb, a power supply terminal VDD, a switch circuit S4, and a phase compensation circuit PC.

The input terminal Vin is connected to the inverting input terminal INM of the differential amplifier DA through the switch S1 and the capacitor C1 connected in series, and is connected to the output terminal Vout through the switch S3.
That is, the first electrode of the capacitor C1 is connected to the switch S1, and the second electrode of the capacitor C1 is connected to the inverting input terminal INM of the differential amplifier DA.
The inverting input terminal INM and the non-inverting input terminal (normal input terminal) INP of the differential amplifier DA function as an inverting input terminal and a non-inverting input terminal of the operational amplifier OP.
A non-inverting input terminal INP of the differential amplifier DA is connected to a reference voltage source VB, and a reference voltage VB which is a constant voltage is applied.

The output circuit OCa is a CMOS buffer circuit composed of an N channel MOS transistor Q1 and a P channel MOS transistor Q2. The transistors Q1 and Q2 are connected in series, the source of the transistor Q1 is grounded, the source of the transistor Q2 is connected to the power supply terminal VDD, and the power supply voltage VDD is applied.
The drains of the transistors Q1 and Q2 are connected to the inverting input terminal INM of the differential amplifier DA via the terminal AOUTa.
The gates of the transistors Q1 and Q2 are connected to the switch circuit S4.

A parasitic capacitance (gate / drain capacitance) Cn is formed between the gate and drain of the transistor Q1.
A parasitic capacitance (gate / drain capacitance) Cp is formed between the gate and drain of the transistor Q2.
The transistors Q1 and Q2 have the same transistor size, and the gate / drain capacitances Cn and Cp are equal (Cn = Cp).

The output circuit OCb is a CMOS type buffer circuit composed of an N channel MOS transistor Q3 and a P channel MOS transistor Q4.
The transistors Q3 and Q4 are connected in series, the source of the transistor Q3 is grounded, the source of the transistor Q4 is connected to the power supply terminal VDD, and the power supply voltage VDD is applied.
The drains of the transistors Q3 and Q4 are connected to the output terminal Vout via the terminal AOUTb.

The gate of the transistor Q3 is connected to the output terminal of the differential amplifier DA.
A bias voltage TPH which is a constant voltage is applied to the gate of the transistor Q4, and the transistor Q4 functions as a load of the transistor Q3.
Therefore, the output circuit OCb functions as an inverting amplifier, inverts and amplifies the output voltage output from the output terminal of the differential amplifier DA, and outputs the inverted and amplified output voltage (output signal) via the terminal AOUTb. Output from Vout.

  The output circuits OCa and OCb have the same characteristics. That is, the transistors Q1 and Q3 have the same characteristics with the same transistor size, and the transistors Q2 and Q4 have the same characteristics with the same transistor size.

  The phase compensation circuit PC is composed of a transistor Q3 and a capacitor Ca connected between its gate and drain, and prevents the oscillation of the sample hold circuit 10 by compensating the phase of the output signal at the output terminal Vout. The operation is stabilized.

The switch circuit S4 includes two two-contact switches S4a and S4b.
When the switch circuit S4 is in an ON state (ON operation), the switches S4a and S4b are simultaneously switched to the ON (ON) side. When the switch circuit S4 is in an OFF state (OFF operation), the switches S4a and S4b are simultaneously OFF. Switched to the (off) side.

  When the switch circuit S4 is turned on (when the switches S4a and S4b are switched to the ON side), the gate of the transistor Q1 is connected to the output terminal of the differential amplifier DA, and the bias voltage TPH is applied to the gate of the transistor Q2. Is applied to turn on the transistor Q2, and the transistor Q2 functions as a load of the transistor Q1.

Therefore, when the switch circuit S4 is turned on, the output circuit OCa functions as an inverting amplifier, inverts and amplifies the output voltage (output signal) output from the output terminal of the differential amplifier DA, and outputs the inverted and amplified output. The voltage is output to the inverting input terminal INM of the differential amplifier DA via the terminal AOUTa.
That is, when the switch circuit S4 is turned on, the output terminal of the differential amplifier DA and the inverting input terminal INM are connected via the output circuit OCa and the switch circuit S4, and negative feedback is applied to the operational amplifier OP.

When the switch circuit S4 is turned off (when the switches S4a and S4b are switched to the OFF side), the gate of the transistor Q1 is grounded, the transistor Q1 is turned off, and the gate of the transistor Q2 is connected to the power supply terminal VDD. The power supply voltage VDD is applied and the transistor Q2 is turned off.
Therefore, when the switch circuit S4 is turned off, the drains of the transistors Q1 and Q2 of the output circuit OCa are fixed to a constant voltage, and the switch circuit S4 between the output terminal and the inverting input terminal INM of the differential amplifier DA is connected. Connection is interrupted.

Each one-contact type switch S1 to S3 is constituted by one CMOS type transmission gate, and each two-contact type switch S4a, S4b is constituted by two CMOS type transmission gates.
The control circuit 11 controls switching of the switches S1 to S3 and the switch circuit S4.

[Operations and effects of the first embodiment]
According to the first embodiment, the following actions and effects can be obtained.

[1-1]
FIG. 2 is a timing chart for explaining the operation of the sample and hold circuit 10.
The sample hold circuit samples the input voltage Vin applied to the input terminal Vin, holds the sampled input voltage Vin, and outputs it from the output terminal Vout.

The duty cycle of the ON / OFF operation of the switch S1 is 50%.
The switch circuit S4 operates in phase with the ON operation of the switch S1, and the duty cycle of the ON / OFF operation of the switch circuit S4 is set smaller than the duty cycle of the switch S1 by the delay time ta.
The switch S3 operates in reverse phase in synchronization with the ON operation of the switch S1, and the duty cycle of the ON / OFF operation of the switch S3 is set smaller than the duty cycle of the switch S1 by the delay time tb.

<Sample period>
In the sample period Ts, the control circuit 11 controls the switch S1 and the switch circuit S4 to be switched on and the switch S3 to be switched off.
A continuously changing analog input signal is input to the input terminal Vin, and the voltage (input voltage) Vin of the analog input signal is applied to the capacitor C1 through the switch S1 in the ON state, and the capacitor is generated by the input voltage Vin. C1 is charged.

At this time, since the switching circuit S4 is in the ON state, negative feedback is applied to the operational amplifier OP, and the voltage (differential input) between the input terminals INM and INP of the operational amplifier OP (differential amplifier DA) due to an imaginary short circuit. Voltage) becomes zero, the voltage VINM of the inverting input terminal INM becomes equal to the voltage VB of the non-inverting input terminal INP.
However, when the operational amplifier OP has the input offset voltage Vofs, the voltage VINM is expressed by Equation 1.

  VINM = VB + Vofs (Equation 1)

  Therefore, the charge Qs accumulated in the capacitor C1 in the sample period Ts is expressed by Equation 2 using the input voltage Vin, the voltage VINM, the reference voltage VB, the input offset voltage Vofs, and the capacitance C1 of the capacitor C1.

  Qs = C1 (VINM−Vin) = C1 (VB + Vofs−Vin) (equation 2)

<Switching period>
In the switching period Tc, the control circuit 11 first switches the switch circuit S4 to the OFF state, then switches the switch S1 to the OFF state after the delay time ta, and then switches the switch S3 to the ON state after the delay time tb. .

At this time, when the switches S4a and S4b of the switch circuit S4 are switched from the ON side to the OFF side, injected charges are generated by the clock field through of the CMOS transmission gates constituting the switches S4a and S4b.
The charge injected by the clock field through of the switch S4a is accumulated in the gate / drain capacitance Cp of the transistor Q2 in the output circuit OCa.
Also, the charge injected by the clock field through of the switch S4b is accumulated in the gate / drain capacitance Cn of the transistor Q1 in the output circuit OCa.

Here, the gate voltage of the transistor Q2 when the switch S4a is on is the bias voltage TPH, and the gate voltage of the transistor Q2 when the switch S4a is off is the power supply voltage VDD, and the difference between the voltages TPH and VDD. Let the voltage be ΔVp.
The gate voltage of the transistor Q1 when the switch S4b is on is the output voltage of the differential amplifier DA, and the gate voltage of the transistor Q1 when the switch S4b is off is the ground voltage. Is a difference voltage ΔVn.

Then, when the switch S4a is switched from the ON side to the OFF side, the electric charge Qp accumulated in the gate / drain capacitance Cp is expressed by Expression 3.
Further, the charge Qn accumulated in the gate / drain capacitance Cn when the switch S4b is switched from the ON side to the OFF side is expressed by Equation 4.

  Qp = Cp × ΔVp (Equation 3)

  Qn = Cn × ΔVn (equation 4)

Here, the transistors Q1 and Q2 have the same transistor size, and the gate / drain capacitances Cn and Cp are equal (Cn = Cp).
Therefore, by appropriately setting the bias voltage TPH, if the difference voltages ΔVn and ΔVp are made substantially equal (ΔVn≈ΔVp), the charges Qn and Qp can be made almost equal (Qn≈Qp).
If the charges Qn and Qp are substantially equal, the charges Qn and Qp cancel each other and disappear, and the charges Qn and Qp can be prevented from being accumulated in the capacitor C1.
The bias voltage TPH may be set by experimentally finding the optimum value by cut-and-try.

<Hold period>
In the hold period (output period) Th, the control circuit 11 switches and controls the switch S1 and the switch circuit S4 to the OFF state and the switch S3 to the ON state.
The charge Qh accumulated in the capacitor C1 in the hold period Th is expressed by Equation 5 using the voltage (output voltage) Vout of the output terminal Vout, the voltage VINM, the reference voltage VB, the input offset voltage Vofs, and the capacitance C1 of the capacitor C1. It is represented by

  Qh = C1 (VINM−Vout) = C1 (VB + Vofs−Vout) (Equation 5)

The electric charge accumulated in the capacitor C1 is held in each period Ts, Tc, Th and is the same, and the electric charges Qs, Qh are equal (Qs = Qh). The voltage Vout is also equal (Vin = Vout).
Further, as shown in Expression 2 and Expression 5, the input offset voltage Vofs of the operational amplifier OP is also canceled.

  Therefore, according to the first embodiment, an error voltage due to the clock field through of the switch circuit S4 is prevented from being generated between the input voltage Vin and the output voltage Vout of the sample and hold circuit 10, and an operational amplifier. Since an error voltage due to the input offset voltage Vofs of OP is prevented and the voltages Vin and Vout can be equalized, a highly accurate sample hold circuit 10 can be realized.

[1-2]
According to the first embodiment, even when the reference voltage VB and the output voltage Vout are different, the error voltage due to the clock field through of the switch circuit S4 does not occur and is not affected by the clock field through. Therefore, the first problem of the technique of Patent Document 1 can be solved.

[1-3]
According to the first embodiment, only the capacitor C1 corresponding to the first capacitance of Patent Document 1 is provided, and it is not necessary to provide the capacitor corresponding to the second capacitance of Patent Document 1. When the monolithic IC is formed, the layout area on the semiconductor chip can be reduced to achieve high integration, and the second problem of the technique of Patent Document 1 can be solved.

[1-4]
By setting the delay time ta, the switch circuit S4 can be switched from the ON state to the OFF state without being affected by the fluctuation of the input voltage Vin when the switch S1 is switched from the ON state to the OFF state. The input voltage Vin when the switch circuit S4 is switched to the OFF state can be sampled and held with high accuracy.

The delay time ta may be set by experimentally finding the optimum value by cut-and-try, and may be set to 1/5 of the time during which the switch S1 is in the ON state, for example.
In this case, since the duty cycle of the ON / OFF operation of the switch S1 is 50%, the duty cycle of the ON / OFF operation of the switch circuit S4 is 40% which is smaller by the delay time ta.

[1-5]
By setting the delay time tb, the switch S3 is switched to the ON state after the switch S1 is completely switched to the OFF state, so that it is possible to reliably prevent the switches S1 and S3 from being turned ON at the same time. The input voltage Vin can be accurately sampled and held.

The delay time tb may be set by experimentally finding the optimum value by cut-and-try, and may be set to 1/5 of the time during which the switch S1 is in the ON state, for example.
In this case, since the duty cycle of the ON / OFF operation of the switch S1 is 50%, the duty cycle of the ON / OFF operation of the switch S3 is 40% which is smaller by the delay time tb.

[1-6]
Each output circuit OCa, OCb is a CMOS buffer circuit. Compared with other types of buffer circuits (for example, buffer circuits using bipolar transistors), the CMOS type buffer circuit has a simple configuration and high performance, and the layout area on the semiconductor chip in the case of a monolithic IC is large. Since it is small, the action / effect can be enhanced.

(Specific example of the first embodiment)
FIG. 3 is a main part circuit diagram showing a main part configuration of a specific example (example) of the first embodiment.
In the specific example shown in FIG. 3, the differential amplifier DA includes N channel MOS transistors Q5 and Q6, P channel MOS transistors Q7 to Q9, and a power supply terminal VDD.
If the differential amplifier DA is configured as in the specific example shown in FIG. 3, the operations and effects of the first embodiment can be obtained with certainty.

The gate of the differential input transistor Q7 is connected to the inverting input terminal INM, and the gate of the differential input transistor Q8 is connected to the non-inverting input terminal INP.
The sources of the transistors Q7 and Q8 are connected to the drain of the transistor Q9, the source of the transistor Q9 is connected to the power supply terminal VDD, and the power supply voltage VDD is applied.
A bias voltage TPH is applied to the gate of the transistor Q9, and the transistor Q9 functions as a constant current source (source current source, tail current source) that supplies a constant current to the transistors Q7 and Q8.

The sources of the transistors Q5 and Q6 are grounded, the gates of the transistors Q5 and Q6 are connected to the drains of the transistors Q5 and Q7, and the transistors Q5 and Q6 constitute a wideler type current mirror circuit having the transistor Q5 as an input side. is doing. The current mirror circuit functions as an active load for the transistors Q7 and Q8.
The drain of the transistor Q8 functions as an output terminal of the differential amplifier DA and is connected to the drain of the transistor Q6.
The transistors Q7 and Q8 have the same transistor size and the same characteristics, and the transistors Q5 and Q6 have the same transistor size.

(Second Embodiment)
FIG. 4 is a circuit diagram showing the sample hold circuit 20 of the second embodiment.
The sample hold circuit 20 differs from the sample hold circuit 10 of the first embodiment only in that a TPH generation circuit 21 that generates a bias voltage TPH based on the output voltage of the differential amplifier DA is provided.
According to the second embodiment, by generating the bias voltage TPH based on the output voltage of the differential amplifier DA, the difference voltages ΔVn and ΔVp in [1-1] of the first embodiment become equal. Since the bias voltage TPH can be set easily and reliably, the operation and effect of [1-1] can be obtained more reliably.

(First specific example of the second embodiment)
FIG. 5 is a main part circuit diagram showing a main part configuration of a first specific example of the second embodiment.
The first specific example shown in FIG. 5 is different from the specific example of the first embodiment shown in FIG. 3 only in that a TPH generation circuit 21 is provided.
The TPH generation circuit 21 of the first specific example is composed of N channel MOS transistors Q10 and Q11, P channel MOS transistors Q12 to Q14, and a power supply terminal VDD.
If the TPH generation circuit 21 is configured as in the first specific example, the operation and effect of the second embodiment can be reliably obtained.

The source of the transistor Q10 is grounded, the gate of the transistor Q10 is connected to the drain of the transistor Q6, and the drain of the transistor Q10 is connected to the drain of the transistor Q12.
The source of the transistor Q11 is grounded, the gate of the transistor Q11 is connected to the gates of the transistors Q5 and Q6, and the drain of the transistor Q11 is connected to the drain of the transistor Q13. That is, each of the transistors Q5, Q6, and Q11 constitutes a dual output type Wideler current mirror circuit that shares the input-side transistor Q5.

The sources of the transistors Q12 and Q13 are connected to the power supply terminal VDD and the power supply voltage VDD is applied, the gates of the transistors Q12 and Q13 are connected to the drain of the transistor Q12, and the transistors Q12 and Q13 are connected to the transistor Q12 on the input side. A wideler type current mirror circuit is configured.
The gate and drain of the transistor Q14 are connected.
The transistors Q13 and Q14 are connected in parallel, and the bias voltage TPH is generated from the common drain.
The transistors Q5, Q6, and Q11 are the same transistor, and the transistors Q12 to Q14 have the same transistor size.

(Second specific example of the second embodiment)
FIG. 6 is a main part circuit diagram showing a main part configuration of a second specific example of the second embodiment.
The second specific example shown in FIG. 6 differs from the first specific example shown in FIG. 5 only in the internal configuration of the differential amplifier DA.
The differential amplifier DA of the second specific example is a symmetric type composed of N channel MOS transistors Q5, Q6, Q15 to Q17, P channel MOS transistors Q7 to Q9, Q18 to Q21, and a power supply terminal VDD.
In the second embodiment, if the differential amplifier DA is configured as in the second specific example, the performance of the differential amplifier DA can be improved as compared with the first specific example.・ Effects can be obtained more reliably.

Each of the transistors Q15 to Q21 constitutes a differential amplifier circuit.
The gate of the differential input transistor Q17 is connected to the inverting input terminal INM, and the gate of the differential input transistor Q16 is connected to the non-inverting input terminal INP.
That is, the differential input transistors Q16 and Q17 and the reverse conductivity type differential input transistors Q7 and Q8 form a symmetrical circuit type.

The sources of the transistors Q16 and Q17 are connected to the drain of the transistor Q15, and the source of the transistor Q15 is grounded.
A bias voltage TNL is applied to the gate of the transistor Q15, and the transistor Q15 functions as a constant current source (source current source, tail current source) that supplies a constant current to the transistors Q16 and Q17.

  The sources of the transistors Q18 and Q19 are connected to the power supply terminal VDD and applied with the power supply voltage VDD, the gates of the transistors Q18 and Q19 are connected to the drains of the transistors Q16 and Q19, and the drain of the transistor Q18 is connected to the transistors Q5 and Q5. The transistors Q18 and Q19 are connected to the gates of Q6 and Q11, and each transistor Q18 and Q19 constitutes a Wideler type current mirror circuit having the transistor Q19 as an input side, and the current mirror circuit functions as an active load of the transistor Q16.

The sources of the transistors Q20 and Q21 are connected to the power supply terminal VDD and applied with the power supply voltage VDD, the gates of the transistors Q20 and Q21 are connected to the drains of the transistors Q17 and Q20, and the drain of the transistor Q21 is the gate of the transistor Q10. The transistors Q20 and Q21 constitute a Wideler type current mirror circuit having the transistor Q20 as an input side, and the current mirror circuit functions as an active load of the transistor Q17.
The transistors Q16 and Q17 have the same transistor size and the same characteristics, and the transistors Q18 to Q21 have the same transistor size.

(Third embodiment)
FIG. 7 is a circuit diagram showing the sample hold circuit 30 of the third embodiment.
The sample and hold circuit 30 includes an unbalanced operational amplifier OP, switches S1 and S3, a reference voltage source VB, a capacitor C1, an input terminal Vin, an output terminal Vout, and a control circuit 11.
The unbalanced operational amplifier OP includes an unbalanced differential amplifier DA, output circuits OCa and OCb, terminals AOUTa and AOUTb, a power supply terminal VDD, a switch circuit S4, and a phase compensation circuit PC.

  The sample hold circuit 30 of the third embodiment differs from the sample hold circuit 10 of the first embodiment in that when the switch circuit S4 is turned on (when the switches S4a and S4b are switched to the ON side), the transistor Q2 Is connected to the output terminal of the differential amplifier DA, a bias voltage TNL is applied to the gate of the transistor Q1, and the transistor Q1 functions only as a load of the transistor Q2.

[Operation and Effect of Third Embodiment]
According to the third embodiment, the following actions and effects can be obtained.

[3-1]
FIG. 2 is a timing chart for explaining the operation of the sample hold circuit 30.
The control circuit 11 switches and controls the switches S1 and S3 and the switch circuit S4 as in the first embodiment.
In the sample period Ts and the hold period Th, the operation of the sample hold circuit 30 of the third embodiment is the same as the operation of the sample hold circuit 10 described in [1-1] of the first embodiment.

  In the switching period Tc, when the switches S4a and S4b of the switch circuit S4 are switched from the ON side to the OFF side, injected charges are generated by the clock field through of the CMOS transmission gates constituting the switches S4a and S4b. The injected charge due to the clock field through of S4a is accumulated in the gate / drain capacitance Cp of the transistor Q2 in the output circuit OCa, and the injected charge due to the clock field through of the switch S4b is the gate / drain capacitance of the transistor Q1 in the output circuit OCa. Accumulated in Cn.

Here, in the sample hold circuit 30 of the third embodiment, the gate voltage of the transistor Q2 when the switch S4a is on is the output voltage of the differential amplifier DA, and the gate of the transistor Q2 when the switch S4a is off. The voltage is the power supply voltage VDD, and the difference voltage between the output voltage and the power supply voltage VDD is ΔVp.
In the sample hold circuit 30 of the third embodiment, the gate voltage of the transistor Q1 when the switch S4b is on is the bias voltage TNL, and the gate voltage of the transistor Q1 when the switch S4b is off is the ground voltage. Yes, the difference voltage between the bias voltage TNL and the ground voltage is ΔVn.

Then, when the switch S4a is switched from the ON side to the OFF side, the charge Qp accumulated in the gate / drain capacitance Cp is expressed by Equation 3 as in the first embodiment.
Further, when the switch S4b is switched from the ON side to the OFF side, the electric charge Qn accumulated in the gate / drain capacitance Cn is expressed by the equation 4 as in the first embodiment.

Here, the transistors Q1 and Q2 have the same transistor size, and the gate / drain capacitances Cn and Cp are equal (Cn = Cp).
Therefore, by appropriately setting the bias voltage TNL, if the difference voltages ΔVn and ΔVp are substantially equal (ΔVn≈ΔVp), the charges Qn and Qp can be approximately equal (Qn≈Qp).
If the charges Qn and Qp are substantially equal, the charges Qn and Qp cancel each other and disappear, and the charges Qn and Qp can be prevented from being accumulated in the capacitor C1.
The bias voltage TNL may be set by experimentally finding an optimum value by cut-and-try.

[3-2]
According to [3-1], according to the third embodiment, the same operations and effects as [1-2] to [1-5] of the first embodiment can be obtained.

(Specific example of the third embodiment)
FIG. 8 is a principal circuit diagram showing a principal part configuration of a specific example of the third embodiment.
In the specific example shown in FIG. 8, the differential amplifier DA is composed of P-channel MOS transistors Q35 and Q36, N-channel MOS transistors Q37 to Q39, and a power supply terminal VDD.
If the differential amplifier DA is configured as in the specific example shown in FIG. 8, the operations and effects of the third embodiment can be obtained with certainty.

The gate of the differential input transistor Q37 is connected to the inverting input terminal INM, and the gate of the differential input transistor Q38 is connected to the non-inverting input terminal INP.
The sources of the transistors Q37 and Q38 are connected to the drain of the transistor Q39, and the source of the transistor Q39 is grounded.
A bias voltage TNL is applied to the gate of the transistor Q39, and the transistor Q39 functions as a constant current source (source current source, tail current source) that supplies a constant current to the transistors Q37 and Q38.

The sources of the transistors Q35 and Q36 are connected to the power supply terminal VDD and the power supply voltage VDD is applied, the gates of the transistors Q35 and Q36 are connected to the drains of the transistors Q35 and Q37, and the transistors Q35 and Q36 connect the transistor Q35. A wideler type current mirror circuit is formed on the input side. The current mirror circuit functions as an active load for the transistors Q37 and Q38.
The drain of the transistor Q38 functions as an output terminal of the differential amplifier DA and is connected to the drain of the transistor Q36.
The transistors Q37 and Q38 have the same transistor size and the same characteristics, and the transistors Q35 and Q36 have the same transistor size.

  That is, the differential amplifier DA shown in FIG. 8 is configured by reversing the conductivity types of the transistors Q5 to Q9 constituting the differential amplifier DA shown in FIG.

(Fourth embodiment)
FIG. 9 is a circuit diagram showing the sample hold circuit 40 of the fourth embodiment.
The sample hold circuit 40 is different from the sample hold circuit 30 of the third embodiment only in that a TNL generation circuit 41 that generates a bias voltage TNL based on the output voltage of the differential amplifier DA is provided.
According to the fourth embodiment, by generating the bias voltage TNL based on the output voltage of the differential amplifier DA, the difference voltages ΔVn and ΔVp in [3-1] of the third embodiment become equal. Since the bias voltage TNL can be set easily and reliably, the operation and effect of [3-1] can be obtained more reliably.

(First specific example of the fourth embodiment)
FIG. 10 is a main part circuit diagram showing a main part configuration of a first specific example of the fourth embodiment.
The first specific example shown in FIG. 10 is different from the specific example of the third embodiment shown in FIG. 8 only in that a TNL generation circuit 41 is provided.
The TNL generation circuit 41 of the first specific example includes P channel MOS transistors Q40 and Q41, N channel MOS transistors Q42 to Q44, and a power supply terminal VDD.
If the TNL generation circuit 41 is configured as in the first specific example, the operation and effect of the fourth embodiment can be reliably obtained.

The source of the transistor Q40 is connected to the power supply terminal VDD and the power supply voltage VDD is applied, the gate of the transistor Q40 is connected to the drain of the transistor Q36, and the drain of the transistor Q40 is connected to the drain of the transistor Q42.
The source of the transistor Q41 is connected to the power supply terminal VDD and the power supply voltage VDD is applied, the gate of the transistor Q41 is connected to the gates of the transistors Q35 and Q36, and the drain of the transistor Q41 is connected to the drain of the transistor Q43. That is, each of the transistors Q35, Q36, and Q41 constitutes a double output type Wideler current mirror circuit that shares the input side transistor Q35.

The sources of the transistors Q42 and Q43 are grounded, the gates of the transistors Q42 and Q43 are connected to the drain of the transistor Q42, and the transistors Q42 and Q43 constitute a wideler type current mirror circuit having the transistor Q42 as an input side. .
The gate and drain of the transistor Q44 are connected.
The transistors Q43 and Q44 are connected in parallel, and the bias voltage TNL is generated from the common drain.
Each transistor Q35, Q36, Q41 is the same transistor, and each transistor Q42-Q44 is the same transistor size.

  That is, the TNL generation circuit 41 shown in FIG. 10 is configured by reversing the conductivity types of the transistors Q10 to Q14 constituting the TPH generation circuit 21 shown in FIG.

(Second specific example of the fourth embodiment)
FIG. 11 is a main part circuit diagram showing a main part configuration of a second specific example of the fourth embodiment.
The second specific example shown in FIG. 11 is different from the first specific example shown in FIG. 10 only in the internal configuration of the differential amplifier DA.
The differential amplifier DA of the second specific example is a symmetrical type composed of P-channel MOS transistors Q35, Q36, Q45-Q47, N-channel MOS transistors Q37-Q39, Q48-Q51, and a power supply terminal VDD.
In the fourth embodiment, if the differential amplifier DA is configured as in the second specific example, the performance of the differential amplifier DA can be improved as compared with the first specific example.・ Effects can be obtained more reliably.

Each of the transistors Q45 to Q51 constitutes a differential amplifier circuit.
The gate of the differential input transistor Q47 is connected to the inverting input terminal INM, and the gate of the differential input transistor Q46 is connected to the non-inverting input terminal INP.
That is, the differential input transistors Q46 and Q47 and the reverse conductivity type differential input transistors Q37 and Q38 form a symmetrical circuit type.

The sources of the transistors Q46 and Q47 are connected to the drain of the transistor Q45, the source of the transistor Q45 is connected to the power supply terminal VDD, and the power supply voltage VDD is applied.
A bias voltage TPH is applied to the gate of the transistor Q45, and the transistor Q45 functions as a constant current source (source current source, tail current source) that supplies a constant current to the transistors Q46 and Q47.

  The sources of the transistors Q48 and Q49 are grounded, the gates of the transistors Q48 and Q49 are connected to the drains of the transistors Q46 and Q49, and the drain of the transistor Q48 is connected to the gates of the transistors Q35, Q36, and Q41. Q48 and Q49 constitute a wideler type current mirror circuit having the transistor Q49 as an input side, and the current mirror circuit functions as an active load of the transistor Q46.

The sources of the transistors Q50 and Q51 are grounded, the gates of the transistors Q50 and Q51 are connected to the drains of the transistors Q47 and Q50, the drain of the transistor Q51 is connected to the gate of the transistor Q40, and the transistors Q50 and Q51 are transistors A wideler type current mirror circuit having Q50 as an input side is configured, and the current mirror circuit functions as an active load of the transistor Q47.
The transistors Q46 and Q47 have the same characteristics with the same transistor size, and the transistors Q48 to Q51 have the same transistor size.

  That is, the TNL generation circuit 41 shown in FIG. 11 is configured by reversing the conductivity types of the transistors Q10 to Q21 constituting the TPH generation circuit 21 shown in FIG.

[Another embodiment]
By the way, the present invention is not limited to the above-described embodiments, and may be embodied as follows. Even in this case, operations and effects equivalent to or more than those of the above-described embodiments can be obtained.

[1] The differential amplifier DA in the specific example of the first embodiment shown in FIG. 3 may be replaced with the differential amplifier DA in the second specific example of the second embodiment shown in FIG.
Further, the differential amplifier DA in the specific example of the third embodiment shown in FIG. 8 may be replaced with the differential amplifier DA in the second specific example of the fourth embodiment shown in FIG.

  [2] In each of the above embodiments, when the switch circuit S4 is turned off (when the switches S4a and S4b are switched to the OFF side), the gate of the transistor Q1 is grounded, the transistor Q1 is turned off, and the transistor Q2 The gate is connected to the power supply terminal VDD, the power supply voltage VDD is applied, and the transistor Q2 is turned off.

However, when the switch circuit S4 is turned off, an appropriate low voltage is applied to the gate of the transistor Q1 to turn off the transistor Q1, and an appropriate high voltage is applied to the gate of the transistor Q2 to turn off the transistor Q2. You may make it make it.
Note that the voltage applied to the gates of the transistors Q1 and Q2 may be set by experimentally finding an optimum value by cut-and-try so that the transistors Q1 and Q2 are surely turned off.

  [3] The switches S1 and S3 and the switch circuit S4 in each of the above embodiments are constituted by CMOS type transmission gates, but by other types of semiconductor type switch circuits (for example, diode bridge type, bipolar transistor type, etc.). It may be configured.

  [4] The MOS transistors Q1 to Q51 of the above embodiments may be replaced with bipolar transistors. In this case, the P channel MOS transistor may be replaced with a PNP transistor, and the N channel MOS transistor may be replaced with an NPN transistor.

  [5] Although the current mirror circuit of each of the above embodiments is a wideler type, other types of current mirror circuits (for example, a Wilson type, a cascode type, a resistance addition type to which a source resistance (emitter resistance) is added, etc.) are used. It may be replaced.

1 is a circuit diagram showing a sample and hold circuit 10 according to a first embodiment that embodies the present invention; FIG. The timing chart for demonstrating operation | movement of each embodiment which actualized this invention. The principal part circuit diagram which shows the principal part structure of the specific example of 1st Embodiment. The circuit diagram which shows the sample hold circuit 20 of 2nd Embodiment which actualized this invention. The principal part circuit diagram which shows the principal part structure of the 1st specific example of 2nd Embodiment. The principal part circuit diagram which shows the principal part structure of the 2nd specific example of 2nd Embodiment. The circuit diagram which shows the sample hold circuit 30 of 3rd Embodiment which actualized this invention. The principal part circuit diagram which shows the principal part structure of the specific example of 3rd Embodiment. The circuit diagram which shows the sample hold circuit 40 of 4th Embodiment which actualized this invention. The principal part circuit diagram which shows the principal part structure of the 1st specific example of 4th Embodiment. The principal part circuit diagram which shows the principal part structure of the 1st specific example of 4th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 20, 30, 40 ... Sample hold circuit 11 ... Control circuit 21 ... TPH generation circuit 41 ... TPL generation circuit OP ... Operational amplifier
INM: Inverted input terminal
INP: Non-inverting input terminal S1, S3: Switch S4: Switch circuit VB: Reference voltage source C1: Capacitor Vin: Input terminal (input voltage)
Vout: Output terminal (output voltage)
DA ... Differential amplifier OCa, OCb ... Output circuit
AOUTa, AOUTb ... terminal VDD ... power supply terminal PC ... phase compensation circuit
TPH, TPL ... Bias voltage Q1-Q51 ... Transistor

Claims (6)

In the sample hold circuit that samples the input voltage applied to the input terminal, holds the sampled input voltage and outputs it from the output terminal,
A capacitor charged by the input voltage;
A first switch connected between the input terminal and the first electrode of the capacitor;
A second switch connected between the output terminal and the first electrode of the capacitor;
A differential amplifier having an inverting input terminal connected to the second electrode of the capacitor;
A reference voltage source for applying a reference voltage to a non-inverting input terminal of the differential amplifier;
A first output circuit that amplifies the output voltage of the differential amplifier and outputs the amplified output voltage from the output terminal;
A second output circuit that amplifies the output voltage of the differential amplifier and outputs the amplified output voltage to the inverting input terminal of the differential amplifier;
A third switch connected between the differential amplifier and the second output circuit;
An operational amplifier is composed of the differential amplifier, the first output circuit, and the second output circuit,
The second output circuit includes first and second transistors of different conductivity types connected in series,
The third switch connects the output terminal of the differential amplifier and the input side of the first transistor, and applies a bias voltage to the second transistor to turn it on when the third switch is turned on.
The third switch turns off both the first transistor and the second transistor during the off operation,
The sample and hold circuit, wherein the third switch operates in the same phase in synchronization with the ON operation of the first switch, and the second switch operates in the reverse phase in synchronization with the ON operation of the first switch. The sample and hold circuit according to claim 1,
The first switch repeats on / off operation at a constant duty cycle,
The sample hold circuit, wherein the duty cycle of the on / off operation of the third switch is set smaller than the duty cycle of the first switch by a first delay time. The sample and hold circuit according to claim 2,
The sample hold circuit, wherein the duty cycle of the on / off operation of the second switch is set smaller than the duty cycle of the first switch by a second delay time. The sample and hold circuit according to any one of claims 1 to 3,
A sample and hold circuit, comprising: a bias voltage generation circuit that generates the bias voltage applied to the second transistor based on an output voltage of the differential amplifier. In the sample hold circuit according to any one of claims 1 to 4,
The second output circuit is a CMOS buffer circuit;
The first transistor is an N-channel MOS transistor;
The second transistor is a P-channel MOS transistor;
The third switch connects the output terminal of the differential amplifier and the gate of the first transistor, and applies a bias voltage to the gate of the second transistor to turn on the third switch.
The third switch is turned off by applying a low voltage to the gate of the first transistor and turning off by applying a high voltage to the gate of the second transistor when the third switch is turned off. . In the sample hold circuit according to any one of claims 1 to 4,
The second output circuit is a CMOS buffer circuit;
The first transistor is a P-channel MOS transistor;
The second transistor is an N-channel MOS transistor;
The third switch connects the output terminal of the differential amplifier and the gate of the first transistor, and applies a bias voltage to the gate of the second transistor to turn on the third switch.
The third switch is turned off by applying a high voltage to the gate of the first transistor and turning off by applying a low voltage to the gate of the second transistor when the third switch is turned off. .

Images