JPS6064520A - Comparator circuit - Google Patents

Abstract

PURPOSE:To discriminate a minute potential difference in high speed by providing a feedback circuit in a comparator circuit. CONSTITUTION:It is when a difference DELTAE between voltages E1 and E2 applied to terminals 28 and 29 is small that the response in high speed is a problem, and the change in the DELTAE inputted to a gate of an inverter 33 is -G1.DELTAE at a drain output of the inverter 33, where -G1 is the amplification factor of the inverter 33 and -G2 is the amplification factor of a clocked gate inverter 36. Moreover, the change is G1.G2.DELTAE at the drain output of the clocked gate inverter 36. Since G1>>1 and G2>>1 exist in general, the change in DELTAE is amplified very largely and fed back and the feedback is repeated through the same loop, the voltage is converged into a high or a low potential side in a very short time.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor (hereinafter MO).
The present invention relates to a comparator circuit using an 8FET (abbreviated as 8FET), particularly a high-speed comparator circuit used in an analog-to-digital conversion circuit.

Conventionally, there are various comparator circuits in circuits using MOSFETs or M08 integrated circuits, but the comparator circuits used in parallel processing type analog-to-digital conversion circuits aiming at high-speed analog-to-digital conversion circuits have a small number of elements. A small pattern area and high-speed response are strongly required. The circuit on the U road side in FIG. 1 is considered to be the closest conventional circuit to meeting this requirement. First, the conventional circuit shown in FIG. 1 will be explained.

In the circuit of FIG. 1, 12 is a first input terminal, 16 is a second input terminal, 16 is a capacitor, 17 is an inverter,
14.18 is a transmission gate whose opening/closing is controlled by φ, and 15 is φ.

transmission gate whose opening and closing are controlled by
19 is an output terminal. Transmission gate 14
is connected between the first input terminal 12 and the first terminal of the capacitor 16. The transmission gate 15 is connected between the input terminal 13 of @2 and the first terminal of the capacitor 15. A second terminal of capacitor 16 is connected to a gate input of inverter 17, and a drain output of inverter 17 is connected to output terminal 19. Transmission gate 18 is connected between the gate input and drain output of inverter 17. Note that FIG. 2 shows the actual 4Vtj configuration of the transmission gate used in the circuit of FIG. 1. In FIG. 2, 20 is a P channel MO8FFiT, and 21 is an N
Channel MO8FET. M'08FET20 and 2
1 are connected in parallel, the terminal 22 of the supply 1 and the second terminal 23
have. Furthermore, a control signal φ is connected to the gate electrode of the N-channel MOBYET, and a control signal φ is connected to the gate electrode of the N-channel MOBYET.
A control signal 7, which is an inverted signal of φ, is connected to the gate electrode of . At this time, the transmitter gate shown in FIG.
F) Do. Further, FIG. 3 shows an actual configuration when the inverter used in the circuit of FIG. 1 is a complementary inverter. In Fig. 3, 24 is P channel M
O8FIIIT, 25 is 08F11fT between N channels
It is. P CHi w ne kM OS F E T 24 (
7) '/- is connected to +VDD, N-channel MO8
The source of 1FBT25 is connected to -VSS. P
Channel MO8FFiT24 drain and N channel M
The drain of O8FFfT25 is connected and serves as the output terminal 27 of the inverter. P channel MO8F
K T 24 (7) Gate and N-channel M OB F
The gate of Ff T25 is connected and serves as the input terminal 26 of the inverter. Now, the operation of the conventional comparator circuit shown in FIG. 1 will be explained. In the circuit of FIG. 1, the clock signal φ1 controlling the transmission gate 14°18 and the transmission gate 1
As shown in the timing chart of FIG. 4, φ is an inverted signal of φ1. Therefore, when φ1 is at a high potential, transmission gates 14 and 1B are on, and transmission gate 15 is off. At this time, the potential EI is applied to the first input terminal 12, and the potential E is applied to the second input terminal 13.
2 is given, the first terminal of the capacitor 16 becomes E8 potential. Further, since the gate input and drain output of the inverter 17 are short-circuited by the transmission gate, both the gate input potential and the drain output potential are at logic level VL, and the second terminal of the capacitor 16 is at VL%. Here, the logic level VL will be briefly explained. Figure 3 shows the actual configuration of the inverter.
The conductance constant β of T24 is βP, the threshold voltage is VTP, and the N-channel MO8FBT25
Let β be βN, the threshold hold pressure be VTN,
Also, -VSS is set to 0 potential, +VDD and -V
Let the potential difference of SS be VDD. And gate human power 2
Gate power 26 when short-circuiting 6 and drain output 27
If the potential of
Since L-VTR)2 holds true, solving this gives the following equation. When this "logic level VL is the gate potential of inverter 7, P channel MO8F1!1T24
Since the J'E dynamics of N-channel Mo5F]riT2s are equal, if the potential is even slightly higher or lower than the logic level, N-channel MO8FF; T or P-channel M
Either O8FInT is dominant. Therefore (1
The potential VL expressed by the formula 01) is called a logic level. From the above, when the clock signal φ1 is at a high potential, the first terminal of the capacitor 6 is at the E1 potential, the second terminal is at the ■L potential, and the gate input potential and drain output potential of the inverter 7 are at the logic level VL. Next, when clock signal φ1 becomes low potential, clock signal φ2
is at a high potential, so the transmission gate 14,1
8 is turned off, and transmission cage 15 is turned on. Therefore, the first terminal of the capacitor 16 has a potential of E.

Further, since the voltage across the capacitor 16 is conserved, the potential at the second terminal of the capacitor 16, that is, the gate input potential of the inverter 17 becomes 2-El potential at VL+. Therefore Fj2)Fj.

In this case, the drain output of the inverter 17, that is, the potential of the output terminal 19 as a comparator becomes a low potential.

Also Fj2(K.

In this case, the potential of the output terminal 19 becomes a high potential.

The above is the operating principle of the conventional humpator circuit shown in FIG. 1, but it is not necessarily sufficient. For example, in a comparator circuit in a high-speed, multi-bit analog-to-digital conversion circuit, E2 and E are used.

Even if the difference between E and If the difference between and El is very small, the response of the inverter 17 will be poor and the high speed requirement will not be met. The reason why the response of the inverter 17 is poor is that when the difference between E2 and El is small, the 6th
In the inverter circuit shown in the figure, P-channel MO8FFiT
The main reason is that both N-channel MO8 and NET25 are on, and there is only a slight difference in driving ability. As described above, it can be said that the conventional comparator circuit has a problem when determining an unlikely voltage difference at high speed.

An object of the present invention is to provide a comparator circuit that can quickly determine a weak voltage difference and that can be realized with a small number of elements and a small pattern area.

The present invention adds an inverter circuit controlled by a clock signal, which corresponds to a feedback circuit, to the inverter circuit that plays the most central role in judgment in the comparator circuit, thereby allowing even the slightest voltage difference to be fed back. This speeds up the judgment as a comparator circuit.

Hereinafter, the present invention will be explained in detail based on examples.

FIG. 5 is a circuit diagram showing a first embodiment of the present invention. In Figure 5, 28 is the first input terminal, 29 is the second input terminal, 32 is the capacitor, 33 is the inverter, 50, 3
．． 4 is a transmission gate whose opening/closing is controlled by φ1, 31 is a transmission gate whose opening/closing is controlled by φ2), 35 is an output terminal, and 36 is a clocked gate inverter whose output is controlled by φ3. The transmission gate 60 is connected to the first input terminal 2
8 and the first terminal of the capacitor 62. The transmission gate 31 is connected to the second input terminal 29
and the first terminal of the capacitor 62.

The second terminal of the capacitor 32 is connected to the gate input of the inverter 33, and the drain output of the inverter 56 is connected to the output terminal 35 by J7. Transmission gate 34 is connected between the gate input and drain output of inverter 33. Clocked gate inverter 36
The gate input of clocked gate inverter 36 is connected to the drain output of inverter 56, and the drain output of clocked gate inverter 36 is connected to the gate input of inverter 33. The circuit configuration described above is basically the same as the circuit shown in FIG. 1 except for the clocked gate inverter 36. In other words, the feature of the present invention is that the clocked gate inverter 36 is added. Note that FIG. 6 shows an example of the actual configuration of the clocked gate inverter used in the circuit of FIG. In Figure 6, 37.41 is P channel MO8F
ET and 38.42 is an N-channel M08FEiT. The source of P channel MOBFInT41 is +VD
The source of the N-channel MO8F]nT42 is connected to -VgSK. P channel MO81
Drain of FInT41 and P channel MO81MCT5
7 sources are connected. N-channel MOsF]n
The drain of T42 and the source of N-channel MO8FET3B are connected. P channel MO8F] 1cT37
The drain of the N-channel MO8FET 3B is connected to the output terminal 59. P channel MO8FF! T37 gate and N channel MO8F
] 1tT3B is connected and connected to the input terminal 40. The gate of the N-channel MO8FIliT42 is connected to the control signal φ, and the gate of the P-channel MO8FIliT42 is connected to the control signal φ.
φ8, which is an inverted signal of φ, is connected to the gate of nT41. Now, in the circuit shown in Figure 5, as a clock signal φ
1, φ2, and φ are used, and the relationship among these signals is shown in the timing chart of FIG. As shown in FIG. 7, φ is an inverted signal of φ, and φ is equal to φ2. Next, the operation of the comparator circuit shown in FIG. 5 will be explained. When clock signal φI is at a high potential, transmission gates 30, 34 are turned on, transmission gate 51 is turned off, and clocked gate inverter 36 does not output. Therefore, the potential E1 is applied to the first input terminal 28, and the potential E! is applied to the second input terminal 29. is given, the first terminal of the capacitor 32 will be at the level of Ktt, and the gate input potential and drain output of the inverter 33 will be at the logic level vL, so the second terminal of the capacitor 32 will be at the level of VLt. Also, inverter 6
VL, which is the logic level of 6, can be made equal to the logic level of the clocked gate inverter 36 if it is designed with good balance. Next, when the clock signal φ1 becomes a low potential, the clock signals φ2 and φ3 become a high potential, so the transmission gates 30 and 54 are turned off, the transmission gate 31 is turned on, and the clocked gate inverter 36 outputs a drain output according to the gate potential. It begins to generate electric potential. Therefore, the potential of the first terminal of the capacitor 52 is
It becomes 2. Further, assuming that the logic level of the inverter 63 and the clocked gate inverter 66 are equal, the clock signals φ1, φ2 . At the moment when φ is switched, the potential of the second terminal of the capacitor 32 and the gate input potential of the multi-inverter 36 become VL+E, -]lit potential. Now, high-speed response becomes a problem when the difference ΔE between E and E□ is small.The amplification factor of the inverter 33 is -G, and the amplification factor of the clock toy/meter 36 is -G! Then, the change in ΔE input to the gate of the Inno Kuichi Taro 6 becomes -01・muE at the drain output of the inno(−ta) 36, and further becomes G1・G2・ΔE at the drain output of the clocked gate inverter 36. Here, since generally Gl>>1tGt)1, the change in ΔE has been greatly increased by 11·b) and λ). Furthermore, since the feedback is repeated through the same loop, it converges very quickly,
It saturates at high potential or low level. Also, the fact that it is fed back means that there is no problem even if ΔE is very small. Whether the output terminal 65 has a low potential or a high potential completely depends on the positive/negative of ΔE, that is, the magnitude relationship between E2 and El, so the circuit shown in Figure 5 functions as a high-precision, high-speed comparator circuit. I understand that. Also, faster convergence means less time spent sitting at an intermediate potential, resulting in lower current consumption. Further, as long as φ is at a high potential and φ1 is at a low potential, the determination data is stored, so it is possible to have it also serve as a latch circuit.

Figure 8 shows the clock signals φ1, φ2, φ of the circuit in Figure 5.
3 shows a state in which the relationship in FIG. 3 is slightly changed from the relationship in the timing chart of FIG. In FIG. 8, φ2 is still an inverted signal of φ1, but the relationship in FIG. 7 is that φ3 rises slightly later than φ2 at the time of rise. As shown in FIG. 8, the lock signal φ1. If we make the relationship between φ2 and φ3, φ1 , φ2 , φ
It is possible to reduce the possibility that the noise at the time of switching of the inverter 33 cancels out the difference ΔE between E and El entered into the gate input of the inverter 33, that is, the possibility of malfunction can be further reduced. Furthermore, FIGS. 9 and 10 show other examples of clocked gate inverters, in which the M
08FFiT and MO driven by clock signal
The positional relationship of the SFET with respect to the power supply is changed.

However, the function as a clocked gate inverter remains unchanged and it can be used as the clocked gate inverter 56 in the circuit of FIG.

FIG. 11 is a circuit diagram showing a second embodiment of the present invention.

In FIG. 11, 55 is a first input terminal, 56 is a second input terminal, 59 is a capacitor, 60 and 63 are inverters, 57.61 is a transmission gate whose opening is controlled by φ□, and 58 is a transmission gate whose opening/closing is controlled by φ2, 64 is a transmission gate whose opening uJ is restricted by φ, and 62 is an output terminal.Transmission gate 5
7 is connected between the input terminal 55 of &'51 and the 1 terminal of the capacitor 59. A transmission gate 58 is connected between the second input terminal 56 and the first terminal of the capacitor 59 . The second terminal of capacitor 59 is connected to the gate input of inverter 60 , and the drain output of inverter 60 is connected to output terminal 62 .

Transmission gate 61 is connected between the gate input and drain output of inverter 60. The gate input of the Inno Kuichi Taro 3 is connected to the drain output of the inverter 60. The drain output of the inverter 63 passes through the transmission gate 64 to
connected to the gate input of The circuits 4i and 7 described above use an inverter 66 and a transmission gate 64 controlled by the clock signal φ3 instead of the clocked gate inverter 36 controlled by the clock signal φ in the circuit shown in FIG. Therefore, the circuit operation of the circuit shown in FIG. 11 and the circuit shown in FIG. 5 is basically the same, but in the case of the circuit configuration shown in FIG. It has the characteristic that it is easy to do.

Further, in the circuits of FIGS. 5 and 11, the opening/closing circuit has been explained using a transmission gate, but the transmission gate may not be used as long as it serves an equivalent role as a switch circuit that is turned on and off by a clock signal.

As described above, by providing a return circuit in a comparator circuit, the present invention realizes a comparator circuit that can handle a weak potential difference at high speed with a small number of elements and pattern area, and also responds quickly and saturates. Since the current consumption is low and the pattern area is small, there is an effect that it is easy to integrate a circuit using a comparator circuit and a converter circuit.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an example of a conventional comparator circuit, Figure 2 is a circuit diagram showing the actual configuration of a transmission gate, Figure 3 is a circuit diagram showing the actual configuration of an inverter, and Figure 4 is a circuit diagram showing an actual configuration of an inverter. The clock signal φ used in the 1-threshold circuit,
5 is a circuit diagram showing the first embodiment of the converter circuit of the present invention, and FIG. 6 is a circuit showing an actual configuration example of a clocked gate inverter. 7, and 8 show the clock signals φ1, φ7, . . . used in the circuit of FIG. 9 and 1D are circuit diagrams showing actual configuration examples other than those shown in FIG. 6 of the clocked gate inverter. FIG. 11 is a second embodiment of the comparator circuit of the present invention. FIG.

Claims (1)

[Scope of Claims] (i) A first input terminal, a second input terminal, a capacitor, and a first clock signal connected between the first input terminal and the first terminal of the capacitor. a first switching circuit whose opening/closing is controlled by a second switching circuit; and a second switching circuit whose UFJ closing is controlled by a second clock signal connected between the second input terminal and the first terminal of the capacitor. a first inverter to which a second terminal of the capacitor is connected to a gate input; an output terminal to which a drain output of the first inverter is connected; and a gate input and a drain output of the first inverter. a third switching circuit whose opening and closing are controlled by a first clock signal connected therebetween; and a second inverter whose output is controlled by the third clock signal, the gate of the first inverter A comparator circuit characterized in that the drain output of the second inverter is connected to the input, and the gate input of the second inverter is connected to the inverter drain output of the M1. 1. The comparator circuit according to claim 1, wherein the second and third opening/closing circuits are both comprised of transmission gates. (3) The second comparator circuit whose output is controlled by the fifth clock signal. The comparator circuit (4) according to claim 1 or 2, wherein the inverter is a clocked gate inverter whose output is controlled by the sixth clock signal. 4''fH'r' The comparator circuit according to claim 1, 2 or 3, wherein the third clock signal and the third clock signal are the same signal.