JPS61214608A - Clamping circuit - Google Patents

Abstract

PURPOSE:To make the title circuit small in size by providing a level comparator for comparing an input signal and a reference voltage and outputting a comparing signal corresponding to a voltage difference of both the signals, a switch for turning on and off the input signal, based on the comparing signal and a capacitor for sample holding. CONSTITUTION:When an input signal VI is applied to an input terminal 101, level comparators 105, 106 compare directly levels of the input signal VI and a reference voltage +VR, -VR and in case when the amplitude of the input signal VI is smaller than a value of the reference voltage +VR and -VR, outputs of each level comparator 105, 106 become an L level, respectively and an output of a gate circuit 107 becomes an H level. When the amplitude of the input signal VI exceeds the reference voltage +VR or -VR, the output of the level comparator 105 or 106 and the output of the gate circuit 107 become an H level and an L level, respectively and a switch 108 becomes off. A charging voltage +VR or -VR appears as it is in an output terminal 104 from an output terminal of an operational amplifier 110 and an output signal VO is clamped by the reference voltage +VR or -VR. In this way, an LSI, etc. can be made small in size.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a clamp circuit suitable for downsizing of LSIs (Large Scale Integrated Circuits) and the like.

(Prior art) Conventionally, as a technology in this field, IEICE Technical Report 84 [
11] (19B4) Institute of Electronics and Communication Engineers P, 1-8. The configuration will be explained below using figures.

FIG. 2 is a schematic diagram of a conventional clamp circuit. This clamp circuit has an input terminal 1 to which an input signal Vl is applied.
, a power supply terminal 2 to which a positive reference voltage ÷VR is applied, a power supply terminal 3 to which a negative reference voltage -VR is applied. It is comprised of an output terminal 4 to which an output signal vO is sent, a level comparison circuit 5, a clock generator 6, an input signal holding circuit 7, and an output selector part 8.

Here, the level comparison circuit 5 uses reference voltages ◆VR, -VR
This circuit compares the level of the input signal Vl and the input signal Vl. Then, a switch IQ, 11 that turns on and off the reference voltages +VR and -VR, a switch 12.13 that turns on and off the input signal VI, and a switch 10.11 or 12.13.
A sample-and-hold capacitor 14 that accumulates the reference voltage ÷VR, -VR or the input signal VI applied via the
．． 15, the positive input terminal is grounded and the negative input terminal is connected to capacitor 1.
Level comparator 1B, 1? connected to 4.15? and a switch 18.19 connected between the input and output terminals of the level comparator 113.17. Switch lO~13,1
8.19 is turned on to the clock signal of the control circuit (not shown);
Controlled off.

The clock generator 6 is a circuit that is composed of a plurality of gate circuits and generates a clock signal for opening and closing the switch based on the output signal of the level comparator 113.17.

The input signal holding circuit 7 temporarily holds the input signal v■, and has a switch 20 that turns on and off the input signal Vl.
, a sample-and-hold capacitor 21 that accumulates an input signal Vl applied through a switch 20, and an operational amplifier 22 whose negative input terminal and output terminal are short-circuited and whose positive input terminal is connected to the capacitor 21. The switch 20 is turned on and off by a clock signal from a control circuit (not shown).

The output selector part 8 is an output switching circuit that is controlled based on the clock signal of the clock generator 6 and includes three sets of sample-and-hold capacitors with switches.

That is, this output selector part 8 includes sample and hold capacitors 30, 31, and 32 that accumulate the output of the operational amplifier 22 and the reference voltages VR and -VR, respectively, and each capacitor y? Switches 33, 34, 35, 38.3 for charging 30, 31, 32? , 38, and a switch 3 that applies the charging voltage of each capacitor 30 to 32 to the output terminal 4.
It consists of 9, 40, 41, 42, 43.44.

The operation of the clamp circuit configured as above will be explained.

First, in the first precert mode to establish initial conditions, the switches 1G, 11, 18.19 are turned on, and the positive and negative reference voltages VR, -VR are detected by the level comparators 1111.
0th order precharged to 17, sample hold Φ
In the output selection mode, the switch 12.13.20 is turned on, the input signal Vl is sampled and held by the capacitor 14.15.21, and the level comparator 18
．． At step 17, the level is compared with reference voltages +VR and -VR, and the comparison result is transferred to the clock generator 6. Furthermore, when the preset mode is entered again, the switch to, 11, 1
Since the switches 33 to 38 in addition to 8 and 113 are turned on, the input signal Vl and the positive and negative reference voltages ◆VR and -VR are precharged to the capacitors 30 to 32. In the sample-and-hold output selection mode, switches 39 and 40.
1, 42, 43, and 44 are turned on, and the signal with the smallest amplitude among the three signals ÷VR, -VR, and Vl is output from the output terminal 4. Therefore, the amplitude of the output signal vo is limited to the positive and negative reference voltages ◆VR1-VR or less every l clock signal.

(Problems to be Solved by the Invention) However, the clamp circuit with the above configuration not only requires a clock signal to control the on/off of the switches 10 to 13 and 18 to 20, but also requires a part of the output selector. Since the clock generator 6 is required to control the on/off of the switches 33 to 44 in the circuit 8, there are problems in that the circuit configuration becomes complicated and the circuit size increases.

The present invention provides a clamp circuit that solves the problems of the prior art, such as the fact that the circuit configuration becomes complicated due to the need for a clock signal, and the circuit scale becomes large. .

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention compares the input signal with a reference voltage to which the input signal should be clamped, limits the amplitude of the input signal to below the reference voltage, and outputs the signal as an output signal. In the output clamp circuit, a level comparator that compares the input signal with a reference voltage and outputs a comparison signal according to the voltage difference between the two signals, and a switch that turns on and off the input signal based on the comparison signal. and a sample-and-hold capacitor that accumulates the input signal via this switch.

(Function) According to the present invention, since the clamp circuit is configured as described above, the level comparison circuit directly compares the input signal and the reference voltage, and controls the switch to be turned on or off based on the comparison result. The switch works as follows: when the amplitude of the input signal is smaller than the reference voltage, the switch turns on and outputs the input signal as is, and also charges the sample and hold capacitor, and when the amplitude of the input signal is larger than the reference voltage becomes off state. By turning off this switch, the charging voltage of the capacitor, that is, the reference voltage is output. Therefore, it is possible to send out an output signal with the amplitude of the input signal limited to below the reference voltage. Therefore, the above problem can be eliminated.

(Embodiment) FIG. 1 is a circuit diagram of a clamp circuit showing an embodiment of the present invention.

In FIG. 1, 101 is an input terminal to which an input signal Vl is applied, 102 is a power supply terminal to which a reference voltage divided by VR is applied, 103 is a power supply terminal to which a negative reference voltage -VR is applied,
and 104 are output terminals to which the output signal vO is sent. And input signal V! The first level comparison circuit 105 that directly compares the positive reference voltage +VR with the positive reference voltage +VR has its positive input terminal connected to the input terminal 101 and its negative input terminal connected to the power supply terminal 102, respectively. Similarly, a second level comparison circuit 106 directly compares the input signal Vl and the negative reference voltage -VR.
has its positive input terminal connected to the power supply terminal 103 and its negative input terminal connected to the input terminal 101, respectively. The respective output terminals of the first and second level comparators 105 and 106 are connected to the input terminal of a gate circuit 107 that performs NAND operation, and the output of this gate circuit 107 controls the on/off of switch +08.

One end of the switch 10 is connected to the input terminal 101, and the other end is connected to the grounded sample-hold capacitor 108 and the positive input terminal of the output buffer operational amplifier 110, respectively. The negative input terminal and output terminal of the operational amplifier 110 are short-circuited, and the output terminal is connected to the output terminal 1.
It is connected to 04.

Note that the level comparators 105 and 108 and the gate circuit 10
7. Switch 108, capacitor 1G! 1 and the operational amplifier 110 are composed of MOS transistors and the like.

Next, the operation of the clamp circuit configured as described above will be explained with reference to FIGS. 1 and 3. Note that FIG. 3 is an input/output waveform diagram, where the dotted line waveform represents the input signal VI, and the solid line waveform represents the output signal vO.

First, when the input signal Vl is applied to the input terminal 101,
The level comparator 105, ioe directly compares the levels of the input signal Vl and the reference voltages +VR and -VR. If the amplitude of the input signal VI is smaller than the values of the reference voltages ◆VR and -VR, each level comparator to5. When the output of the gate circuit 107 is at the H level, the switch 108 is turned on. The input signal VI charges the capacitor 109 and is applied to the positive input terminal of the operational amplifier 110 through this switch. Then, since the operational amplifier 110 is a voltage follower whose output voltage is directly fed back to the negative input terminal, the output signal vO having the same waveform as the input signal VI input to the positive input terminal is impedance-converted and output from the output terminal 104. Output.

Next, the amplitude of the input signal Vl is set to the reference voltage ◆VR or -V
When R is exceeded, the output of the level comparator 105 or 10G becomes H level, which causes the output of the gate circuit 107 to become L level, and the switch 108 is turned off.

When the switch 108 is turned off, the charging voltage +VR or -VR of the capacitor 109 when it is off is applied to the positive input terminal of the operational amplifier 110, so that the charging voltage ◆VR or -VR is directly transferred from the output terminal of the operational amplifier 11G. The signal is output and appears at the output terminal 104. Therefore, the output signal vO is clamped to the reference voltage ◆VR or -VR without following the input signal VI.

According to this embodiment, the output signal v■ whose amplitude of the input signal VI is limited to the reference voltage ◆VR, -VR or less is applied to the LS
It can be obtained with a small number of elements suitable for I-conversion.

A comparison of the number of elements between the circuit of this embodiment shown in FIG. 1 and the conventional circuit shown in FIG. 2 is as follows.

(1) Circuit level comparators 105, 108...2 in FIG. 1, gate circuit 107...1, switch lO8...1, capacitor 109...1, operational amplifier 110...・1 piece,
Total of 6 pieces.

(2) Circuit level comparators 18, 19...2 in Figure 2, clock generator 6
Gate circuits constituting...Several pieces, switches lO~13
．． 18~20.33~44...13 pieces, capacitor 1
4.15, 21.30-32...6 pieces, operational amplifier 2
2...1 piece, 28 or more pieces in total.

In this way, in this embodiment, not only can the number of elements be significantly reduced compared to the conventional one, but also the switch 10 can be reduced as compared to the conventional one.
-13. Since a two-phase clock signal for controlling ON/OFF of 18 to 20 is not required, the circuit configuration is simplified.

Note that in the above embodiment, two level comparators 105.1
08, but if you want to limit the clamp voltage range to only the positive side or only the negative side, remove the level comparator 10B or 105 and invert the output of the comparator 105 or 106 that is not removed. knot circuit (
N07 circuit) is newly provided, and the switch 108 is controlled on and off by the output of this N07 circuit.
When the number of reference voltage values to be clamped is increased from that shown in FIG. 1, the number of level comparators may be three or more.

As described above, various modifications can be made without departing from the spirit of the invention.

(Effects of the Invention) As described in detail above, according to the present invention, the level comparator directly compares the input signal and the reference voltage, controls the on/off of the switch based on the comparison result, and controls the switch. Charge the sample hole capacitor through
Since the charging voltage of the capacitor is output when the switch is off and the output signal is limited to below the reference voltage, there is no need for a clock signal generation circuit for controlling the on/off of the switch, and the circuit component can significantly reduce the number of Therefore, the single circuit configuration is simple and the circuit scale is small, making it possible to provide a clamp circuit suitable for downsizing of LSIs and the like.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a clamp circuit showing an embodiment of the present invention;
FIG. 2 is a circuit diagram of a conventional clamp circuit, and FIG. 3 is an input/output waveform diagram of FIG. 1. 105.108...Level comparator, 108...
...Switch, 108...Sample and hold capacitor, vr...Input signal, vO...
...Output signal, +VR, -VR...Reference voltage.

Claims (1)

[Claims] In a clamp circuit that compares an input signal with a reference voltage to be clamped, limits the amplitude of the input signal to below the reference voltage, and outputs it, the input signal and the reference voltage are input, and the two inputs are compared to determine the voltage difference. a level comparator that outputs a comparison signal according to the comparison signal, a switch that turns on and off the input signal based on the comparison signal, and a sample-hold capacitor that accumulates the input signal via this switch. A clamp circuit characterized by: