JPS6350997A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To process parallel data at high speed, to convert it into serial data and to output it without using a shift register by using a clocked CMOS circuit in output stage. CONSTITUTION:The respective output terminals of the clocked CMOS inverters 11-14 are connected to be data output terminals in common. The respective data transferred through an I/O line is simultaneously inputted to the terminals of the inverters 11-14. The data shifts clocks phi1-phi4 impressed to the respective inverters 11-14 impressed to the respective inverters 11-14 a little by a little. Thereby, it is converted into the serial data and outputted to the one data output terminal. In the gates of the respective MOSFETs of the inverters 11-14, a BiCMOS inverters 2 (21-26) are provided as a driver. Thereby the parallel data can be processed at high speed, converted into the serial data and outputted without using the shift register.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Industrial Application Field) The present invention relates to an output buffer circuit that converts parallel data into serial data and outputs the same.

(Prior Art) FIG. 6 is a configuration example of a data output circuit in a conventional dRAM. This converts 4-bit parallel data into columns.
This is an output circuit in a 4-bit nibble mode that converts to serial data and outputs it by toggling the address strobe signal (CAS clock). The 4-bit parallel data D1 to D4 are subjected to parallel/serial conversion by the shift register 51, and the resulting serial data is converted into three stages of CMOS inverters 521 to 521 in this example.
523 and extracted. The CMOS inverter array, which is the output buffer stage of this circuit, has an output load (
(usually 100pF constant load and 22TTL load)
It is designed to have sufficient driving ability to operate within a limited time period below sea level. In general, the first and second stages of 0
The channel width of the MoS transistor constituting MO8 is 1
A ratio of :3 is almost the optimum size ratio. The number of stages of the inverter array is usually 3 to 4 stages.

In such an output buffer having a multi-stage configuration of inverters, signal delay in this portion poses a problem, and this becomes a limiting factor in memory access time. For example, in the case of a 4-bit nibble, when the first address of the 4 bits is accessed, 4 bits of data are simultaneously transferred to the shift register, which is converted to serial data by toggling the CAS and output, but in this case the access time is Determined by the operating speed of the shift register and inverter array.

It is easy to increase the speed of a shift register by making some circuit improvements, but it is difficult to increase the speed using an inverter array.

This is because the final stage inverter needs to be large in order to drive a large load capacity, and in order to drive it at high speed, a CM whose gate input capacitance gradually decreases is required.
This is because a multi-stage configuration of the OS inverter is required, and this multi-stage configuration causes a signal delay.

(Problems to be Solved by the Invention) As described above, the conventional nibble mode dRAM has a problem in that the signal delay in the output buffer is large in order to enable faster access.

An object of the present invention is to solve these problems and provide an output buffer circuit that has a parallel/serial conversion function and can operate at high speed.

[Structure of the Invention (Means for Solving Problems)] The output buffer circuit according to the present invention is composed of a plurality of clock 960M08 circuits whose output terminals are connected in parallel,
It is characterized in that parallel data is converted into serial data and output by switching the clock signal to each clock 960M08 circuit.

(Function) The clock 960M08 circuit can maintain the output terminal in a high impedance state regardless of the input state when no clock signal is input.

Therefore, by connecting multiple clock 10M03 circuits in parallel and switching the clock signals, each clock 960
Data transferred in parallel to the M08 circuit can be converted into serial data and output. This configuration does not require a shift register for parallel/serial conversion and does not require multi-stage connection of inverters, so high-speed operation is possible. Therefore, if used in the data output circuit section of dRAM, high-speed access in nibble mode becomes possible.

By the way, a clocked CMOS inverter is a normal CM
Two MOS transistors are added in series to the OS inverter. Therefore, in order to make the load driving capability of a clocked CMOS inverter the same as that of a normal CMOS inverter, if the gate length of each MOS transistor is the same, the gate width must be doubled.

Therefore, a clocked CMOS inverter is a normal CMOS inverter.
It requires a larger area than an S inverter, and naturally has a larger input capacitance, so if the driving ability of the driver that drives it is small, high-speed operation will be hindered. In order to compensate for this, a clocked CMOS inverter using a bipolar transistor with a large current driving capacity in its output section may be used as the driver stage of the clocked CMOS inverter.

(Example) The present invention will be explained in detail below.

FIG. 1 shows an embodiment in which the present invention is applied to a data output buffer 7 of a 4-bit nibble mode dRAM. Four clocked CMOS inverters 11 to 14 are provided, and their output terminals are commonly connected to serve as a data output terminal. 4-bit data Ds transferred via the I10 line.

D1 to D4, D4 are four clocked CMOS at the same time
It enters the input terminals of inverters 11-14.

These data are stored in each clocked CMOS inverter 1.
By slightly shifting the clocks Φ1 to Φ4 applied to signals 1 to 14, the data is converted into serial data and output to one data output terminal. Each configuration MoS of each clocked CMOS inverter 11 to 14
At the gate of the transistor, as a driver, a CMOS inverter using a bipolar transistor in the output stage,
In this case, wIBiCMOS inverters 2 (21 to 26) are provided. The number of B i CMOS inverters in each gate section is one or two in consideration of each drive phase.

6. FIG. 2 shows an example of the configuration of the B i CMOS inverter 2. In FIG. The output stage includes an npn transistor Ql.

Q2 is connected in series. An npn transistor Q is connected between the base and emitter of the transistor Q1 on the power supply Vce side.
3 is diode-connected. Output stage transistor Q
1. The part that drives Q2 includes a p-channel MOS transistor Tt, T2 and an n-channel MoS transistor T.
3. 0MO8 consisting of T4 and Ts is used.

P channel MOS transistors Tt and Ta are for activating this buffer.

In this B i CMOS inverter, the control signal O8 is L
I! When the level is high, the MoS transistor T1 is on, and therefore the output stage transistor Q1 is on,
The output terminal is kept at the "H" level regardless of the input IN's "l HI+" or "L I+".The control signal C8 is ")l"
When the level becomes II, the MoS transistor T1 turns off and T
3 is turned on and the circuit is activated. and input IN
When is at "H" level, transistor Q1 is turned off, transistor Q2 is turned on, and a 111 II level output is obtained. Input IN
When is at #L TJ level, the output becomes 'H' level.

This B i CMOS inverter is advantageous when the load capacitance is large because the output stage is a transistor with a large current driving ability. FIG. 3 shows the relationship between delay time and load capacitance per stage of a B i CMOS inverter and a normal CMOS inverter. As is clear from the figure, in the B i CMOS inverter, even if the load capacity increases, the delay time does not increase that much.

FIG. 4 is a signal waveform diagram showing how data is output from the output buffer according to this embodiment. The row address strobe signal (RAS clock) goes to the Lt+ level, then the column address strobe signal (CAS clock) goes to the 111IT level, and the predetermined address signal is read in synchronization with these. A memory cell is selected.

In the case of this embodiment, since the mode is 4-bit nibble mode, the data D1 to D4 of four memory cells among the memory cells connected to one word line selected by the row address are
are simultaneously transferred in parallel to each separate T10 line.

These data D1-D4 enter each clocked CMOS inverter of the output buffer of FIG. Then, the parallel data is sequentially selected and taken out as serial data by the clocks Φ1 to Φ4 whose phases are slightly shifted.

Thus, in this embodiment, by using a plurality of clocked CMOS inverters, parallel data can be converted into serial data and output without using a shift register. And in this example output buffer,
High-speed operation is possible because parallel/serial conversion is performed only by switching the clocks of a plurality of clocked CMOS inverters.

Furthermore, if a normal CMOS inverter is used in the output stage, it is necessary to connect the inverters in multiple stages in order to operate at high speed when the load capacitance is large, and signal delay due to this multi-stage connection poses a problem. On the other hand, in this embodiment, B i is used as the driver stage of the clocked CMOS inverter.
This problem is solved by using a CMOS inverter.

That is, in this embodiment, even if the clocked CMOS inverter has a large area and has sufficient driving capacity,
It is possible to operate this at high speed without making multi-stage connections. Therefore, according to this embodiment, a nibble mode dRAM capable of high-speed access can be realized.

The present invention is not limited to the above embodiments.

For example, the configuration of the clocked CMOS inverter is not limited to that shown in FIG. 1, and various configuration methods such as those shown in FIGS.
In case of e), (a) and (i), when the input is at the 'H' level, the output is at the 'H' level, and therefore, although they are not inverters, they can be used as buffer circuits in the same way as the other circuits.

Also, in the embodiment, the case of 4-bit nibble was explained, but
The number of bits is arbitrary. Furthermore, multiple clocked CMOS
The output terminals of the inverter are basically independent and have a multi-bit parallel output configuration, and when using the nibble mode, a transfer gate is provided to commonly connect each output terminal, or they are commonly connected using an optional mask on the metal wiring layer. For example, the same pattern can be used effectively.

Furthermore, if a large area is allowed for the output buffer circuit, a normal CMOS inverter can be used as the driver stage of the clocked CMOS inverter.

[Effect of the invention] As described above, according to the present invention, the clock 10M08
By using a circuit in the output stage, parallel data can be processed at high speed, converted to serial data, and output.
In particular, a useful output buffer circuit can be realized when applied to nibble mode dRAM.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an output buffer 7 circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing a B i CMOS inverter used in the circuit, and FIG. 3 is a diagram showing a B i CMOS inverter used in the circuit.
A diagram showing the characteristics of a CMOS inverter in comparison with a normal CMOS inverter. Figure 4 is a signal waveform diagram for explaining the operation of a nibble mode dRAM using the output buffer circuit of Figure 1. Figure 5 (a) ~(+) is a clocked commercial
FIG. 6, which is a diagram showing another example of the configuration of O3, is a diagram showing the configuration of a data output section of a conventional nibble mode dRAM. 11 to 14...Clocked CMOS inverter, 21
~26...B1CMo5 inverter, Dt. the law of nature. Applicant's representative Patent attorney Takehiko Suzue Vcc Vcc VccWh 2
Figure Load Capacity 3 Factor 10 〇 and 0 3 1e Castle 10
θ − θ re z re to x −10θ 0 3 1°

Claims (2)

[Claims] (1) Multiple clocked CMOs with common output terminals connected
1. An output buffer circuit comprising an S circuit, wherein parallel data is converted into serial data by switching a clock signal to each clocked CMOS circuit and taken out from the output terminal. (2) The output buffer circuit according to claim 1, wherein the driver of each clocked CMOS circuit uses a bipolar transistor in an output stage.