JP2538628B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION [Table of Contents] Overview Industrial field of application Conventional technology (Figs. 6 to 8) Problems to be solved by the invention Means for solving problems Problems Working Examples Basic of the present invention Principle (FIG. 5) One embodiment of the present invention (FIGS. 1 to 4) Effect of the invention [Overview] A semiconductor integrated circuit having a repetitive circuit such as a ROM, a RAM, and a PLA. In addition to reducing the output load of the circuit to improve the responsiveness and reduce the layout area, a first operation array for cooking operation of input data, and a first operation array,
In the semiconductor integrated circuit, the output array outputs the operation result of the operation array in response to a predetermined timing signal, and the second operation array logically operates the output data of the output array. A timing signal generation circuit for generating the timing signal in response to a potential change at substantially the end of the input data transmission signal line disposed therein is provided, and the output array outputs the output from the first operation array. The precharge operation is maintained at one logic level, while the discharge operation is performed in synchronization with the timing signal when the output is at another logic level.

[Industrial applications]

The present invention relates to a semiconductor integrated circuit, and particularly to a large-scale PLA (Programmable Logic Ar) using dynamic logic.
The present invention relates to a semiconductor integrated circuit which is applied to a ray) and the like and has a high speed with a minimum chip occupation area.

Recently, semiconductor integrated circuits have become LSI (Large Scale Integrate).
d circuit) to VLSI (Very LSI)
In order to improve the integration density, ROM (Read Only Memor
y), RAM (Random Acssess Memory), PLA and other repetitive circuits tend to be used. In addition, there is a strong demand for speeding up, and it is not unusual for discussions to develop in the order of several ns these days.

In such VLSI, dynamic logic is often used for the purpose of reducing power consumption and reducing heat generation, and circuit load is reduced by precharging and discharging.

Moreover, even when configuring a random logic, it is recommended to use a repetitive circuit, and large-scale random logic is being realized by PLA.

[Conventional technology]

As described above, there are various VLSIs, but here, a dynamic PLA will be described as an example.

It is well known as a cellular logic theory that an AND-OR two-stage logic circuit can realize an arbitrary logic function.
Is based on this logic.

As a conventional PLA of this type, for example, there is one as shown in FIGS. In FIG. 6, 1 is a PLA, and PLA1 is composed of an AND array 2 composed of many AND gates and an OR array 3 composed of many OR gates.
The output of the AND array 2 is input to the OR array 3, and AND
Array 2 is precharged and discharged based on clock φ1 and clock φ1 bar, respectively. On the other hand, precharging and discharging of the OR array 3 are performed based on the clock φ2 and the clock φ2 bar, and according to four types of clock timings.
PLA1 is precharged and discharged.
As shown in FIG. 7, each clock timing is different on the AND array 2 side and the OR array 3 side. After the output logic level on the AND array 2 side is determined, the clock timing is transmitted to the OR array 3 side and then on the OR array 3 side. The output logic level is fixed.

To explain the details, as shown in FIG.
The output of AND array 2 is clocked between
A buffer 4 for transmitting to the OR array 3 is provided according to 2 bars, and all the outputs of the AND array 2 are input to the corresponding NAND gates 5a to 5n. Each NAND gate 5a
The clock φ2 bar that specifies the discharge timing on the OR array 3 side is input to ~ 5n. When the discharge on the AND array 2 side is completed and the output logic level is fixed, the clock φ2 bar becomes H level and the AND array The logical operation result on the 2 side is transmitted to the OR array 3 side. In addition, (6a ~ 6n) is a buffer.

As shown in FIG. 9, when viewed from the OR array 3 side, when the clock φ2 bar is at the L level, the P channel (hereinafter referred to as Pch) precharge transistor (hereinafter referred to as PCTr) 7 causes the OR side. Although the output signal line 8 is precharged, the logical output level of the AND array 2 is fixed before the precharge of the three OR arrays is completed.
Therefore, the clock φ2 bar is at the H level, that is,
When the clock φ2 becomes L level, the OR side output signal line 8 is discharged by the DCTr9 according to the output logic level on the AND array 2 side. In this way, according to the discharge timing, from the AND array 2 side to the OR array 3
The logic level is transmitted to the side. In addition, 10 is a buffer.

[Problems to be solved by the invention]

However, in such a conventional semiconductor integrated circuit, in consideration of speeding up the response, it is necessary to improve the response of the discharge, and the chip area of the semiconductor integrated circuit is expanded as compared with the case where the speeding up is not intended. There is a tendency. Further, since a plurality of timings for precharge and discharge are also required, it is necessary to configure a plurality of high-speed timing signal generation circuits, which also causes an increase in chip area. Therefore, there is a problem in that it is difficult to increase the speed while maintaining the minimum chip area required to configure the logic circuit.

That is, taking the above PLA as an example, as shown in FIG. 8, the clock φ2 bar is input to a large number of NAND gates 5a to 5n, and all the drivers of the clock φ2 bar (hereinafter referred to as clock driver φ2) are input. NAND gates 5a-5n
Must simultaneously drive the input capacitance of. Therefore, it is necessary to configure the clock driver φ2 with a transistor having a large gate width capable of handling a large load current, that is, a transistor having a large area due to an increase in load capacitance. Further, in order to discharge the OR array 3 side at high speed, the output circuit area of the buffer 4 and the OR shown in FIG.
For the same reason, it is necessary to increase the area of the DCTr 9 that discharges the side output signal line 8. Furthermore, when the load capacitance increases, a large time constant occurs even with a slight wiring resistance, and the responsiveness deteriorates.

As described above, in a large-scale semiconductor integrated circuit, achieving high-speed response with a minimum logic circuit and a minimum layout pattern pitch has been a contradictory issue.

Therefore, an object of the present invention is to simplify the configuration of the timing generation circuit and reduce the output load of the circuit to improve the responsiveness and reduce the layout area.

[Means for solving problems]

The semiconductor integrated circuit according to the present invention achieves the above object,
A first operation array for logically operating input data, an output array for outputting the operation result of the first operation array in response to a predetermined timing signal, and a second operation for logically operating the output data of the output array A semiconductor integrated circuit including an array, the semiconductor integrated circuit being arranged in the first arithmetic array,
In response to the potential change at the almost end of the input data transmission signal line,
A timing signal generating circuit for generating the timing signal is provided, and the output array maintains the precharge operation when the output from the first arithmetic array is at one logic level, while the output array is at the other logic level. The discharge operation is performed in synchronization with the timing signal.

[Work]

According to the present invention, the potential at the substantially terminal end of the input data transmission signal line always changes after the calculation result of the first calculation array is determined, and the discharge operation of the output array is limitedly performed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. For convenience of description, the basic principle of the present invention will be described first with reference to FIG.

FIG. 3A is a diagram explaining the first basic principle. In the figure, 11 is a transfer transistor of a predetermined conductivity type (N conductivity type in the figure) (hereinafter referred to as TFTr), and TFTr
The data signal IN is input to the gate of 11. Inverter 12 is connected to the drain side of TFTr11 and Pch
PCTr13 is provided. The precharge on the drain side of TFTr1 is the clock signal CLK2 input to the gate of PCTr13.
Is based on. On the other hand, the clock signal CLK1 is input to the source of the TFTr11, and the TFTr11 is turned on under a specific condition. That is, the PCTr13 is turned on in advance to precharge the drain side of the TFTr11, and after the data signal IN is set to the H level, when the clock signal CLK1 becomes the L level, the TFTr11 is maintained while the clock signal CLK1 is at the L level.
Turns ON. At this time, the charge precharged by the PCTr13 is sucked into the driver side of the clock signal CLK1 and the TFTr
The drain side of 11 becomes L level, and the output signal OUT of the inverter 12 becomes H level. Therefore, when the above conditions are not satisfied, for example, when the data signal IN is at L level or the clock CLK1 is at H level, TFTr11
Is not turned on and the drain side of TETr11 is not discharged. Therefore, if the data signal IN is activated at the H level, the TFTr11 can be turned on and discharged to output the data signal only when it is active, and the TETr11 can be turned off when it is inactive.
That is, the clock signal CLK1 only when discharging
Since a load is applied to the driver of, the circuit in which the ratio of the data signal IN becoming active is small, for example, the decoder that selects a memory cell, PLA, etc. Can be significantly reduced. As a result, it is not necessary to configure the driving circuit, that is, the driver of the clock signal CLK1 with a large-area transistor intended for high-speed operation in the circuit of FIG. Due to the reduction of the delay time constant, high-speed response can be realized while maintaining the minimum circuit configuration and layout pattern pitch.

FIG. 5 (b) is a diagram for explaining the second basic circuit.
The data signal IN is input to the gate of Nch DCTr21, and DCTr2
1 output signal line 22 is clock signal CLK1 by Nch PCTr23
Is precharged based on. Output signal line 22 is TFTr24
Is connected to the output buffer 25 via, and a Pch PCT 26 is provided on the output side of the TFTr 24. The clock signal CLK2 is input to the gate of the TFTr24, the precharge by the PCTr26 is performed in advance, and the level of the output signal line 22 is L.
After the level is fixed, TFTr24 is turned on in response to the H level of the clock signal CLK2.

Here, this basic circuit is characterized by precharging by the PCTr23, which will be described in detail. Clock signal now
When CLK1 goes high, PCTr23 turns on, but at this time the output signal line 22 is not completely precharged to the power supply voltage Vcc. For example, if the power supply voltage Vcc is 5V, the output signal line 2
2 is only precharged up to about 3V. This decrease is called the Beckgate effect. Back gate effect is Pch T
It also occurs at r, and in this case, even if it is intended to discharge to an L level (for example, 0V) by a Pch transistor of H level (for example, 5V), it does not completely become 0V and a potential of about 2V remains. Therefore, the Nch Tr can completely transmit the L level, and the Pch Tr can perfectly transmit the H level. By the way, in this basic circuit, the back gate effect is positively used. Since the precharge voltage by the PCTr23 is about 3V, when the data signal IN becomes H level and the DCTr21 is turned ON, the output signal line 22 It is possible to shorten the time required until the potential of becomes 0V. That is, it means that when the potential of the output signal line 22 is set to a low value of about 3V, the time taken to discharge to 0V can be shortened and the high-speed response of the DCTr 21 can be realized, when the potential is set to about 3V.

FIGS. 1 to 4 are diagrams showing an embodiment in which the first and second basic circuits described above are applied to a PLA.

First, the configuration will be described. In FIG. 3, 31 is a PLA, and PLA 31 is an AND array consisting of many AND gates (corresponding to the first operation array described in the gist of the invention) 32 and an OR array consisting of many OR gates (the gist of the invention). (Corresponding to the second operation array described in 1). The data signal IN of PLA31 is input to the AND array 32 via the input buffer 34,
Further, it is input to the OR array 33 via an intermediate buffer (corresponding to the output array described in the gist of the invention) 35 provided between the AND array 32 and the OR array 33. Incidentally, 36 is an output buffer. The AND array 32 is provided with a dummy AND circuit (corresponding to the timing signal generating circuit described in the gist of the invention) 37 including the same AND gate as the AND array 32.
Precharging and discharging are performed by the same timing signal φ as in the above. That is, the dummy AND circuit 37
4 has the same structure as the AND array 32 as shown in FIG. 4, and is formed at a position farthest from the input buffer 34 in layout. The output of the dummy AND circuit 37 is input to the intermediate buffer 35, and the intermediate buffer 35 is connected to the AND array 32.
When the output of is determined, the data is transmitted to the OR array 33 according to the output signal of the dummy AND circuit 37.

FIG. 1 is a circuit diagram based on the block configuration diagram shown in FIG. 3, and for convenience of explanation, an AND array 32 and an OR array 33.
Is omitted.

In the figure, the input buffer 34 has a large number of buffers 41 composed of a single logical operation layer, and one buffer 41 is a TFTr.
42, PCTr43, inverter 44 and output buffer 45. Each output of the input buffer 34 is input to the dummy AND circuit 37 via the AND array 32, and the input buffer 34, the intermediate buffer 35 and the dummy AND circuit 37 are precharged and discharged based on the timing signal φ. Input signal lines (corresponding to the input data transmission signal lines described in the gist of the invention) 46 and 47 of the AND array 32 are provided with DCTrs 50 and 51 for discharging corresponding output signal lines 48 and 49, respectively. A PCTr 52 is arranged on each of the lines 48 and 49. The input signal lines 46 and 47 are DCTr54 and 55 of the dummy AND circuit 37.
The DCTr54 and 55 are discharged to the output signal line 56 of the dummy AND circuit 37 precharged by the PCTr53. The output of the dummy AND array 37 is the inverter 5
It is input to the intermediate buffer 35 via 7, 58. The intermediate buffer 35 follows the output of the inverter 58 and the AND array 32.
Is transmitted to the OR array 33. Where the intermediate buffer
The first basic circuit is applied to 35, and the second basic circuit is applied to the OR array 33 side, and the same components as those shown in FIGS. 4 (a) and 4 (b) are used. Are denoted by the same reference numerals and description thereof will be omitted. The output of the intermediate buffer 35 is input to the input signal lines 59 and 60 of the OR array 33,
The gate of Tr23 is connected to the input signal line 61. Input signal line
The output of the inverter 58 is input to the inverter 61 via the inverters 62 and 63, and the PCTr 23 precharges the output signal line 22.
The output signal line 22 of the OR array 33 is connected to the output buffer 36, and the TFTr 24 of the output buffer 36 has its gate connected to Vcc and turns on according to the logic level of the output signal line 22.
At this time, the output buffer 25 inverts the output of the OR array 33 and outputs it to the outside.

The operation of each part when the timing signal φ and the data signal IN are applied as shown in FIG. For convenience of explanation, the signal names of the respective parts are made to correspond by attaching the symbol S to each member number.

First, PCTr43 is the engine whose timing signal φ is L level.
S _46, S ₄₇ and ON are at the L level, as well PCTr5
2, 53 are turned on, and S ₄₈ , S ₄₉ , and S ₅₆ (S ₅₆ corresponds to a predetermined timing signal described in the gist of the invention) are at H level. Now, assuming that the data signal IN is at the L level, S ₄₆ becomes the H level in response to the rise of the timing signal φ, but since S ₄₇ remains at the L level, S ₄₉ also maintains the H level. There is. When S ₄₆ becomes the H level DCTr50 and D
CTr54 is S ₄₈ and S ₅₆ performs the discharge becomes L level. At this time, since the DCTr250 and the DCTr54 are formed apart from each other, the DC resistance is affected by the wiring resistance of the input signal line 46.
The operation of Tr54 is slightly later than the operation of DCTr50. Therefore, a similar delay occurs when the timing signal φ becomes L level. That is, dummy AND
Since the circuit 37 is formed on the extension of the fastest AND array 32 from the input buffer 34, an intentional delay is generated in the signal of the output signal line 56 to provide the discharge timing on the OR array 33 side. Further, since the dummy AND circuit 37 has the same configuration as the AND array 32, it can be formed as a repeating circuit similar to the AND array 32. From the above, the circuit configuration does not become complicated because a plurality of timing generation circuits are provided unlike the conventional case. In addition, since the dummy AND circuit 37 is added only to the output signal line 56, the dummy AN
It is possible to realize the DCTrs 54, 55, etc. that form the D circuit 37 with the minimum necessary layout pattern.

When S ₅₆ goes to L level, inverters 57, 58 and 62, 6
After going through 3, S ₆₁ goes to L level. At this time, AND array 32
The output of is determined before the level of S ₅₆ is determined, and is already input to the intermediate buffer 35. Of S ₄₈ and S ₄₉ input to the intermediate buffer 35, S ₄₉ is at the H level (active), so that TFTr11 connected to the output signal line 49 is turned ON upon the rising of S ₅₆ , and the precharge charge by the PCTr 13 is converted to the inverter. 58 sucks. On the other hand, S ₄₆ is at the L level, TFTr11 no ON leading to an output signal line 48. That is, it is similar to the first basic circuit described above, and the intermediate buffer
Only when 35 inputs are active (for example, H level)
TFTr11 is turned on and discharging is performed. Therefore, the fewer active signal inputs the inverter
The load capacitance of 58 can be reduced, and the responsiveness of discharge can be improved while realizing the inverter 58 with the minimum layout pattern.

DCTr21b is ON when S ₆₀ becomes H level, discharges the precharge voltage by PCTr23. At this time, PC
Due to the back gate effect of Tr23, the output signal line 22b is precharged at a voltage lower than the power supply voltage.
The time required to discharge to V can be shortened. That is, as in the case of the second basic circuit described above, the precharge by the PCTr23 is intentionally set to a value lower than the power supply voltage, and therefore the responsiveness of the discharge by the DCTr21b can be improved.

Data output OUTb when S _22b becomes L level to H level.

On the other hand, when the data signal IN becomes the H level, the S ₄₈ becomes L-level at the rising edge of the timing signal phi, S ₄₈ remains at H level. DCTr51 is ON in response to the H level of the S ₄₇
Then, since the TFTr 11 connected to the output signal line 49 maintains the OFF state, the S ₆₀ remains at the L level When the L level of S ₄₉ is determined, S ₅₆ and S ₆₁ become the L level. At this time, S
_{Since 48} is at H level, S ₅₉ goes to H level in response to the rise of S ₅₆ . Therefore, S _22a becomes L level and the data output OUTa becomes H level.

In the above embodiments, the case where the present invention is applied to the PLA has been described, but the present invention can be applied to a semiconductor integrated circuit having a plurality of repetitive circuit networks such as ROM and RAM, and similar effects can be obtained. it can.

〔effect〕

According to the present invention, since the potential at the substantially terminal end of the input data transmission signal line always changes after the calculation result of the first calculation array is determined, an appropriate timing signal can be generated by the timing generation circuit having a simple structure. The operation result of the first operation array can be given to the two operation arrays at the optimum timing.

Further, since the discharge operation of the output array is limitedly performed according to the calculation result of the first calculation array, the load of the timing signal can be reduced.

[Brief description of drawings]

1 to 4 are diagrams showing an embodiment of a semiconductor integrated circuit according to the present invention, FIG. 1 is a circuit diagram showing a main part thereof, FIG. 2 is a timing chart explaining its operation, and FIG. Is an overall configuration diagram thereof, FIG. 4 is a configuration diagram showing a main part thereof, FIG. 5 is a configuration diagram illustrating the basic principle of a semiconductor integrated circuit according to the present invention, and FIGS. 6-9 are conventional semiconductor integrated circuits. FIG. 6 is a diagram showing an example, FIG. 6 is an overall configuration diagram thereof, FIG. 7 is a timing chart showing its clock timing, FIG. 8 is a configuration diagram showing its intermediate buffer, and FIG. 9 is a main part of its OR array. It is a circuit diagram showing. 32 ... AND array (first operation array), 33 ... OR array (second operation array), 35 ... Intermediate buffer (output array), 37 ... Dummy AND circuit (timing signal generation circuit), 46 …… Input signal line (input data transmission signal line), 47 …… input signal line (input data transmission signal line).

Claims (1)

(57) [Claims] 1. A first arithmetic array for logically operating input data, an output array for outputting the arithmetic result of the first arithmetic array in response to a predetermined timing signal, and a logical operation for output data of the output array. A semiconductor integrated circuit including a second operation array, wherein the timing signal generation circuit generates the timing signal in response to a potential change at a substantially terminal end of an input data transmission signal line arranged in the first operation array. While providing a circuit, the output array maintains a precharge operation when the output from the first operation array is at one logic level,
A semiconductor integrated circuit, wherein the discharge operation is performed in synchronization with the timing signal when the output is at another logic level.