JP3071273B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[Industrial applications]

[0001] The present invention relates to a decoder circuit suitable for use in a memory IC or the like.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing an example of a conventional semiconductor memory device . In this figure, reference numeral 1 denotes a memory cell for storing data. This memory cell 1 is, for example,
Depletion type or depending on the content of the data to be stored,
Or forming an N-channel MOS transistor of the enhancement type, the memory cells are arranged in array form
Thus, a memory cell array (without sign) is configured . The gate terminals of the transistors forming such a memory cell array, is connected to a word line which is not shown, the row-side address signal for designating the predetermined memory cell is supplied to the word line . That is, the low-side address signals is adapted to specify a "row" of the memory cell array.

Reference numerals 2 and 2 denote select transistors, and select lines SL1 and SL2 are connected to their gate terminals, respectively. To the select lines SL1 and SL2, a column address signal for selecting the bit lines B1 and B2 is supplied .
"Column " is selected. Reference numeral 3 denotes a sensor amplifier that reads data from a memory cell specified by the above-described row-side address signal and column-side address signal and outputs the data from an OUT terminal. FIG. 4 shows a configuration example of the sensor amplifier 3.

In FIG. 4, reference numeral 4c denotes a driving transistor 4
a and a level shift circuit composed of an inverter 4b. The level shift circuit 4c generates a level according to the connection state of the memory cell specified by the row address signal and the column select signal described above,
This is output to the sense line S. Reference numeral 50 denotes a reference circuit which generates a predetermined reference level voltage from the positive power supply voltage + Vdd, and outputs this to the reference line R. Reference numeral 6 denotes a differential amplifier, which differentially amplifies signals supplied to the reference line R and the sense line S and outputs the amplified signal.

In the semiconductor memory device having the above configuration, data is read out as follows. That is, when accessing a predetermined memory cell of the memory cell array, first, the bit line by the column-side address signals B1,
Select one of B2 and the memory comprising the memory cell 1
A "column" of a cell array is designated, and a memory cell comprising a memory cell 1 connected to the designated bit line
A "row" of the array is specified by a row address signal. When the specified memory cell holds data, the sensor amplifier 3 outputs an “H” level signal (data “1”) from the output terminal OUT.
When the memory cell does not hold data, an “L” level signal (data “0”) is output from the output terminal OUT.

[0006]

By the way, the above-mentioned half
In the conductive memory device , the following problem has occurred with the switching of the bit line performed according to the column address signal supplied from the outside. Hereinafter, this will be described with reference to FIGS. First, as shown in FIG. 5, the switching period between the bit line B1 and the bit line B2 is T1, T2, T3, and the columns T1 to T3 designate the "column" of the memory cell array including the memory cells 1 in these periods. An address signal is supplied, and expected values of data read at each timing are set to “1”, “1”,
Let it be "1".

At this time, when the bit line B2 is selected in the periods T1 and T3 and the bit line B1 is selected in the period T2, the bit line B1 is discharged to the level Vss in the periods T1 and T3, while the period T2 , The bit line B2 is discharged to the level Vss. Note that the level Vss indicates the potential level of the source terminal of the transistor included in the memory cell.

As described above, when the discharge is performed in accordance with the switching of the bit line, the level change shown in FIG. 5 appears at the node A of the decoder circuit. That is, when the bit line is switched, as shown in FIG.
The level of the sense line S in the sensor amplifier 3 temporarily drops below the reference line R level due to discharge,
Thereafter, it is charged and shifts to the “H” level. When the level of the sense line S is lower than the level of the reference line R, the sensor amplifier 3 recognizes the level as the “L” level.

As a result, there is a problem that the sensor amplifier 3 outputs erroneous data "0" which becomes noise due to the above-mentioned malfunction, although the data to be read is "1". In addition, as shown in FIG. 6, such noise appears along with the internal delay Td in the sensor amplifier 3 after the switching of the bit line, so that it takes time to read the true data, which is the access time. Came from a delay. The present invention has been made in view of the above circumstances, it is possible to prevent erroneous data generated as noise, and the semiconductor SL can be shortened even access time
It is intended to provide storage devices .

[0010]

SUMMARY OF THE INVENTION The present invention relates to a memory cell.
Are arranged in an array and connected to each bit line.
A memory cell array composed of Te, during the first selection means for selecting one of the bit lines according to a column side address signal for designating a column <br/> of said memory cell array, a power input end A driving transistor to be connected, and an inverter for inputting an input signal from the input terminal and outputting the signal to the gate of the driving transistor. From a connection point between the driving transistor and the inverter, a row-side address and a column-side select signal are used. A level shift circuit that outputs a level signal according to a connection state of a specified memory cell to a sense line, a reference circuit that generates a predetermined reference level voltage from a power supply voltage, and outputs the reference level voltage to a reference line; A differential amplifier that differentially amplifies and outputs each signal supplied to the sense line and the reference line; Rannahli, among the memory cell array connected to the bit line selected by said first selection means,
A sensor amplifier for reading data of a predetermined memory cell
A semiconductor memory device comprising: a second selection unit that selects all bit lines other than the bit line selected by the first selection unit; and a dummy amplifier having the same configuration as the sensor amplifier, and Pulling up all of the bit lines selected by the selection means , the second selection means
Note connected to all bit lines selected by the stage
Voltage supply means for supplying a voltage corresponding to the data held by the recell .

[0011]

According to the above arrangement, the second selecting means selects all the bit lines other than the bit lines selected by the first selecting means, and the voltage supply means selects the second selecting means.
For all bit lines selected by said all bits
A constant voltage is supplied according to the data held by the memory cells connected to the line to prevent a bit line level from being lowered when the bit line is switched.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. 1 according to an embodiment according to the invention
FIG. 3 is a circuit diagram illustrating a configuration of a semiconductor storage device . In this figure, parts common to the respective parts shown in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted. In addition, the semiconductor shown in this figure
The point that the body memory device differs from that shown in FIG.
Select transistors 4 and 4 that operate as switches are respectively connected in series to the other ends of the first and second transistors B1 and B2.
Is connected. Hereinafter, such a configuration will be described.

The select transistors 4 and 4 operate in the same manner as the select transistors 2 and 2 and switch the bit lines B1 and B2 in accordance with the column address signals supplied to the select lines SL3 and SL4. . A column address signal is supplied to the select lines SL3 and SL4 so as to reverse the switching operation of the select transistors 2 and 2. That is, when select transistors 2 and 2 select bit line B1 (or B2), select transistors 4 and 4 select bit line B1 (or B2).
The column address signal is supplied so as to select 2 (or B1).

The dummy amplifier 5 has the same configuration as the sensor amplifier 3 described above (see FIG. 4), and pulls up the bit line selected by the select transistors 4 and 4 to a constant potential. That is, the dummy amplifier 5 keeps the bit line selected by the select transistors 4 and 4 in accordance with the column side address signal at a constant potential, and prevents the bit line from being discharged to the level Vss when switching. ing. The constant potential is, for example, a potential that is about 100 mV lower than the potential that the sensor amplifier 3 recognizes as the “H” level.

Next, a read operation of the semiconductor memory device having the above configuration will be described with reference to FIG. In the description of the operation, as shown in FIG. 2, the bit lines B1 and B
2 is defined as T1, T2, and T3, and the memory cell array including the memory cells 1 is used in these periods T1 to T3.
Column address signal that specifies the “column” of
The expected values of the data read at each of these timings are “1”, “1”, and “1”, respectively.

In such a situation, in the period T1, the selector line SL2 is set to the "H" level, and the bit line B
2 is selected (see the waveform of SL2 shown in FIG. 2). At this time, the select line SL3 is set to the “H” level, whereby the bit line B1 is connected to the dummy amplifier 5 and is kept at a constant potential (see the waveform of the node B shown in FIG. 2). Then, when transitioning from this period T1 to the next period T2, the selector line SL1 is set to “H” level according to the column address signal, and the bit line B1 is selected.
At the same time as this switching, the select line SL4 goes to “H” level, and the bit line B2 is connected to the dummy amplifier 5.

Accordingly, since both bit lines B1 and B2 maintain a constant potential even when switched by select transistors 2 and 2, node A in this semiconductor memory device (see FIG. 2). In this case, discharge does not occur and the voltage does not drop to the level Vss as in the related art. After such bit line switching, a predetermined memory cell corresponding to the above-mentioned row address signal is read. In this case, data “1” is read. Then
Even in the transition to the period T3, the same operation as described above is performed, the node A in this decoder circuit becomes the "H" level, and the data "1" is read.

Thus, in the embodiment described above,
Since the bit line selected by the select transistors 4 and 4 is kept at a constant potential by the dummy amplifier 5, the level of the node A in the decoder circuit does not decrease due to discharge as in the related art. As a result, it is possible to prevent the occurrence of noise due to the reduction in the level, and to shorten the access time.

In the above description of the operation, the case where all the data to be read is "1" has been described as an example, but the same applies to the case where the data to be read is "0". That is, the potential pulled up by the dummy amplifier 5 is
1 higher than the level that the sensor amplifier 3 recognizes as “H” level
Since the potential is about 00 mV lower, even if other bit lines are pulled up when the data to be read is “0”, it is recognized as “L” level by the sensor amplifier 3.

[0020]

As described above, according to the present invention, the sensor amplifier is selected by the first selecting means.
A predetermined memory in the memory cell array connected to the bit line
The data of the recell is read out, the second selecting means selects all bit lines other than the bit lines selected by the first selecting means, and the voltage supply means has the same structure as the sensor amplifier.
Field production by supplying a constant voltage to all the bit line selected by the second selection means by forming the dummy amplifier
Since the bit line level drop that occurs at the time of bit line switching is prevented without being affected by fluctuations, the level drop due to the conventional discharge is eliminated.
It is possible to prevent erroneous data from occurring as noise and shorten the access time.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment according to the present invention.

FIG. 2 is a time chart for explaining the operation of the embodiment.

FIG. 3 is a circuit diagram illustrating an example of a conventional semiconductor memory device .

FIG. 4 is a circuit diagram showing a configuration of a sensor amplifier 3.

FIG. 5 is a time chart for explaining the operation of the conventional example.

FIG. 6 is a diagram illustrating a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... memory cell , 2 ... select transistor (1st selection means), 3 ... sensor amplifier (reading means), 4 ... select transistor (2nd selection means), 5 ... dummy amplifier (voltage supply means), B1, B2: Bit line.

Claims (1)

(57) [Claims] 1. A memory cell array memory cells are connected to respective bit lines are arranged in an array, any of the bit lines according to a column side address signal for designating a column of said memory cell array The first to choose
A driving transistor connected between a power supply and an input terminal;
An inverter for inputting an input signal from the input terminal and outputting the input signal to the gate of the drive transistor; connecting a memory cell specified by a row-side address and a column-side select signal from a connection point between the drive transistor and the inverter; A level shift circuit that outputs a level signal according to a situation to a sense line, a reference circuit that generates a predetermined reference level voltage from a power supply voltage and outputs the reference level voltage to a reference line, the sense line and the reference line And a differential amplifier that differentially amplifies and outputs each of the signals supplied to the memory cell array. The data of a predetermined memory cell in the memory cell array connected to the bit line selected by the first selecting means. And a sensor amplifier for reading the data , wherein the first selecting means A second selection means for selecting all bit lines other than the selected bit line; and a dummy amplifier having the same configuration as the sensor amplifier,
The all bit lines selected by the second selecting means;
Is pulled up and selected by the second selecting means.
Data held by the memory cells connected to all the bit lines.
And a voltage supply means for supplying a voltage corresponding to the data .