JPH0562471A - Column selector circuit - Google Patents

Abstract

PURPOSE: To improve the tolerance of a device against transient radiation by using a column decoder of multistage constitution which enhances a weak output from a precedent stage at a following stage. CONSTITUTION: There are 32 stages 20 present and four COLs are formed of one-of-four decoders 29 according to address values on lines A0 and A1 and connected to the 32 stages 20 respectively. A 2nd stage 30 makes a one-of-eight choice. When there are 4 2nd stages 30 and each stage receives outputs of eight stages 20, corresponding address lines appear on lines 34N respectively, and one is affirmed. A 3rd stage 40 receives corresponding address signals on lines 44N from one-of-four decoders formed of the values of address lines A5 and A6 . Thus, one line selected out of data lines communicate with a line OUT through a selected stage 20 among the 2nd stages 30. A signal from a deteriorating stage is restored by this multistage selection.

Description

Detailed Description of the Invention

(Field of Industrial Application) The present invention relates to the field of integrated circuits, and more particularly to a decoder circuit for an integrated memory circuit. This invention was made with Government support under Contract No. 001-86-C-0090 of the Department of Defense's Nuclear Defense. The government owns the rights to the invention. (Prior Art) A storage element array in a conventional random access storage device (RAM) is generally assembled into independently selectable rows and columns. The selected address signal appearing on the address terminals of the device selects the column of the storage element array which is decoded by the row decoder and leads to the sense amplifier. Other address signals are decoded by the column decoder to select one or more bits in the selected column to read or write data. Therefore, the column decoder in a conventional RAM will eventually perform a multiplex operation to select one of the many possible bits in the selected column. Turning to FIG. 1, a common column decoding and demultiplexing scheme is shown that illustrates one of the four choices. The signals A0 and A0- are logically complementary to each other and constitute the least significant bit of the two address signals, likewise the signals A1 and A1- represent the true and false states of the second least significant bit. Is connected to various combinations of the AND gate 10 ₀ 10 ₃ or four in the true and false address lines, creating a high logic-level in response to an appropriate combination of address signals at its input. For example, the output of the AND gate 10 ₂ is A0 and A1- address line goes high in response to a high (address A2). When the output from AND gate 10 goes high, its associated pass control transistors ₁₂₀ to 12 ₃ conduct and connect the corresponding data lines D ₀ to D ₃ to line OUT. For example, from the data lines for D ₀ to D ₃ are the data line to be driven by the four sense amplifiers in the RAM device, in the case of the circuit of FIG. 1 is adapted to select the application of line OUT. Alternatively, lines D ₀ through D ₃ may be the actual bitlines of the storage device or a storage device using a single sense amplifier for multiple columns before sensing. As shown in FIG. 1, tiger Njisuta 14 is connected between the line OUT and the power supply _{V dd,} the signal PC at the gate of transistor 14 is Purechi Yaji line OUT to _{V dd} when high. At that time, the line OUT is pulled down (pulled down to the ground potential) if the state of the data lines D ₀ to D ₃ is low, or remains high if the selected data line is high. Is. As is well known in the art, it is possible to directly drive (ie, discharge or maintain) the line OUT from the data lines D ₀ to D ₃ , and in the logic-low state, the discharge capacitors are sequentially gated to the line OUT. Can also be discharged. Many other realities of the column decoder shown in FIG. 1 can, of course, be realized using the domino control realization and other pass control gate concepts, including precharge and discharge schemes. In addition, a larger number of pass control gates are used to decode a larger number of address lines, and one or more of a larger number of data line groups (eg, 128 groups) than the four shown in FIG. You can also choose a bit. The exposure of a device containing a circuit such as that shown in Figure 1 to transient gamma radiation causes the pass control transistor 12, and also the precharge transistor 14, to conduct normally nonconductive due to photoconduction. Become. If these transistors conduct in a state that should be non-conducting, the selected data line D ₀ to D ₃ will have a logic state where the V _dd supply drives line OU T high by photoconduction of transistor 14. In addition, the unselected data lines D ₀ to D ₃ pull the line OUT to their logic level due to the photoconduction of the associated pass control transistor 12, so that the state of the line OUT becomes messy. There is a risk of becoming. If reaches the value of the current flowing through one of the passage control transistor 12 ₀ the sum is selected for light conduction current of the transistor 14 and the selected non passes control transistor 12 to 12 _3, you to occurrence of an error is there. In the worst case of this type of event in the circuit of FIG. 1, for example, the selected data line D ₀ will be at a low logic level and the unselected data lines D ₁ to D ₃ will be at a high level. Become a logic level. Four non-conductive and should Trang register, if reaches the value of the current flowing through the 12 ₀ sum was passage control transistor selected photoconductive current flowing from 14 and 12 ₁ to 12 _3, appear at the data line D ₀ Logic-low levels will not be detected. (Problem to be Solved by the Invention) Therefore, one object of the present invention is to improve the resistance of the control pass transistor to the photoconduction which occurs in a situation of gamma-ray emission which causes conduction when it should be non-conducting. To provide a larger column decoder circuit. Another object of the present invention is to provide a column decoder having a multi-stage structure so that the weakened output from the preceding stage can be strengthened in the subsequent stage, and further improve the resistance of the device to transient radiation. Still another object of the present invention is to provide a column decoder having a reduced number of fan-in and fan-out stages, thereby reducing switching time vs. temperature sensitivity. Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the drawings and reading the following specification. (Means for Solving the Problem) The present invention incorporates a multi-stage column decoder in which each stage receives a group of data lines and a group of decoded address signals from the storage element array of the first stage or the first stage. be able to. Within each stage, logic is provided to gate each of the data lines corresponding to its associated decoded address signal. If the decoded address line is used for a data line, the state of that data line drives the tri-state driver, and the unused address line drives the tri-state driver to a high impedance state. The unselected high-impedance state of the driver is due to the separation of those data lines from the decoder stage, causing the photoconduction due to transient radiation to pull to the output node towards the intermediate rail instead of high or low. Increase the radiation resistance of the circuit. The multistage design increases the output of each stage and restores the logic level from one stage degraded by transient radiation events. (Embodiment) The stage 20 of the column decoder according to the present invention will be described with reference to FIG. For purposes of explanation, stage 20 of FIG. 2 is described as the stage closest to the storage element array, and it will be further described below that this same design is equally applicable to subsequent stages of the multi-stage column decoder. The stage 20 receives signals on the data lines D ₀ to D _{3 as} in the decoder shown in FIG. Stage 20 receives the address input COL0 for selecting one of the data lines from _{D 0} that put the terminal _{OUT 20} to D3 to COL3. Address signal on line COL0~3 is one of the lines COL0 to COL3 but is positive (i.e. high - becomes logic level) to select one of up to D ₃ from 4 Tsunode Tarain D _0, 4 single address The other three of lines COL0-3 are address signals which have been decoded so that they are not asserted (i.e. go to a logic low level). Therefore, the lines COL0 to COL3 in FIG. 2 correspond to the outputs of the four AND gates 10 ₀ to 10 ₃ shown in FIG. Stage 20 four sub-stage, 20 ₀ to 20 ₃ Ki de be thought of as composed of up to one of each of which at D ₃ or from the data line D _0, and address lines corresponding thereto, Receives one of COL0 to COL3. As for substring stage 20 _0, NAND gate 220 receives the address line COL0 corresponding thereto data lines D0, with elements other input at one input. Output of NAND gate 22 ₀ is coupled to the gate of the p- channel transistor 24 ₀ gate and n- channel transistors 28 _0,. Address lines COL0 directly n - is connected to the gate of the channel transistor 26 _0. Transistors ₂₄ 0, 26 ₀ and 28 ₀ source connected in series between the ground and the power supply node _{V dd} - has a drain between paths, p- Chiyan'neruto transistor 24 ₀ three transistors ₂₄ 0, 26 ₀ and 28 ₀ to the role of the pull-up transistor of a push-pull driver constituted by, n- channel transistor 28 ₀ as a pull-down transistor, also the transistor 26 ₀ you serve as isolation transistors. The output of substage 20 ₀ is in the node between the transistors 24 ₀ and 28 ₀ of the drain, this node is connected directly to the line OU _{T 20} is the output of the stage 20. Operation when, if an affirmative to choose an address line COL0 is de Tarain D _0, NAND gate 22 ₀ is the logical complement of Logistics click state of the data line D _0. Line COL0 Gaha Lee - transistor 26 if a logic level ₀ corresponds to the logic state of the output of the NAND gate 22 ₀ conducting to serve as code conversion push-pull driver. Therefore, if chosen, will be (inverted twice) the logic state of the data lines _{D 0} appears at the node between the drain of the transistor 24 ₀ and 26 _0, meet at the output and line OUT ₂₀ of the stage 20 .. Line was Tsu Naka selected corresponding the address lines COL0 the COL3 of the data lines from D ₀ to D ₃ denotes a row - a logic level. The sub-stage 20 ₁ For example, the address line COL0 is high - line COL1 If the logic level is low. Thus the output of NAND gate 22 ₀ is independently of forcibly high level state of the data line _{D 1,} to turn off the transistor 24 _1. Furthermore, the line COL1 is low - by the logic-level, transistor capacitor 26 ₁ is connected between the transistors 24 ₁ and 28 ₁ of the drain is turned off, take the case where the data lines D ₀ is selected as an example For example, line OUT ₂₀ is isolated from the V _dd and ground nodes of the sub-stage because transistors 24 ₁ and 28 ₁ are off. In this example, the sub-stage 20 ₂ and 20 ₃ is similarly address lines COL2 and COL2 row - since the logic level, each of the transistors motor 24 and 26 substage 20 ₀ turned off to drive the line _{OUT 20} be able to. As is well known in the art, transient radiation events, above any other effect, cause source-drain photoconduction in MOS transistors, which should normally be off. As described above with respect to the circuit of FIG. 1, the effect of photoconduction on or from one logic state can mess up reading or writing of other logic states. The circuit of FIG. 2, 20 ₀ normal sub-stage that was not selected among the up or et 20 ₃ tends to become conductive the transistor 24 and 26 should be off. When this type of event occurs in the circuit of FIG. 2, line OUT ₂₀ will try to pull some voltage somewhere between V _dd and ground. The example shown in FIG. 3 is for a 128 column array which is decoded into a single output bit from the seven column address signals A0 through A6. As described with respect to FIG. 2, each of the stages 20 receives four of the data lines from D ₀ to D ₁₂₇ , so that in the embodiment of FIG. 3 there are 32 sets of stages 20. Four address lines, (in COL _n third FIG) COL3 from COL0, one according to the value of the line A ₀ and A ₁ on the address signals - of - Fore (one-of-four) decoder, it is formed by 29, Lead to each of the 32 Stage 2. The group of the second stage 30 has the same structure as the stage 20 of FIG. 2, but in this embodiment, one-of-eight (one in eight) selection is performed. Therefore, in the embodiment of FIG. 3, there are four second stages 30, 30. Each of the second stages, 30 receives the outputs of eight sets of stages 20 as data inputs. The corresponding address line appears on each of the four second stages, 30 by line 34 _n , one of which is one-of-eight corresponding to the value of the address signal on the address line at A ₂ to A _4. Affirmed by the decoder. Thus, each of the four sets of second stages, 30 selects and outputs one data state of its associated stage, 20. The third stage, 40, makes the final selection of the bits to be read. The third stage, 40, is also similar in construction to the stage 20, shown in FIG. 2, and receives the outputs from the four second stages, 30 as its data input. Third stage, one formed by the value on the address lines A5 and A6 - of - receiving a corresponding address signal on line 44 _n from Foadeko over da. The selected one of the data lines D ₀ to D ₁₂₇ thus communicates with line OUT through its stage 20, which is selected by the selected one of the second stage, 30. The multistage selection completed by the circuit of Figure 3 restores the degraded signal from the previous stage. Returning to FIG. 2, one of the data states selected from the data lines D ₀ to D ₃ has a high-level or a low-logic level by one of the corresponding NAND gates 22. Will be flipped to either. Regarding the second stage, the third stage, or the third stage, 40, the NAND gate that receives the output signal from the selected previous stage has its signal level deteriorated and its logic level has dropped to the intermediate value (because it becomes inaccurate). Unless otherwise noted, the same inversion process is performed. Since the transistors 24 and 28 in the selected substage, 20 _n , fully invert the output of the NAND gate 22 there, any degradation of the signal received from the previous stage will occur in the second stage constructed in accordance with the invention. 30 and the third stage, 40. Also, by using multi-step processing (reduction of fan-in and fan-out), the signal deteriorated by high temperature operation is also strengthened, which further stabilizes the circuit performance over a given temperature range. To do. It should be further noted that the embodiment of the stage shown in FIG. 2 should be used as a one-stage decoder in devices with a small number of data lines or where transient radiation immunity is not an issue. It means that you can As described above with respect to the embodiment of FIG. 1, either the data line itself selected from D ₀ to D ₃ or the sense amplifier is either the load capacitor of line OUT (and the stray capacitance of transistor 14). The driving ability of either one is often small considering the driven load. According to the design of FIG. 2, the voltage of the selected data line can be amplified and the communication speed to the output terminal of the selected storage element can be increased. Although the present invention has been described in detail with reference to examples, it should be understood that this description is given as an example only and is not intended to limit the scope. Also, it is clear that there are various changes in the details of realization of the invention, and that the above-mentioned realizations of the present invention exist, and those who have ordinary skill in the art will understand based on this explanation. Must understand that they can. Such modifications and their further implementations are within the spirit and true scope of the appended claims.

[Detailed Description of Drawings]

 FIG. 1 is a wiring diagram showing, in the form of a system diagram, a column decoder according to the prior art using the pass control gate method. FIG. 2 is a wiring diagram showing, in the form of a system diagram, the column decoding and selecting circuit constructed according to the present invention. FIG. 3 is a wiring diagram showing, in the form of a system diagram, a three-stage column decoding and selecting circuit constructed according to the present invention.

Claims (9)

[Claims] 1. A decoded column address selector for a memory device, each having a data signal input and a decoded address signal input, each of which has a decoded address signal indicating selection of a data signal. A plurality of gates each having an output representing a signal corresponding to a data signal responsive to the, and each being associated with said plurality of gates, each connected to its associated gate to direct its output to its associated gate's output. In response to the above-mentioned decoded address signal indicating the deselection of its data signal, each having a separating means connected to its corresponding decoded address signal. It consists of multiple drivers that put their outputs in a high-impedance state, and the outputs of the above-mentioned multiple drivers are combined and selected. Column selection circuit, characterized in that indicating the logic state corresponding to the logic state of the data signal. 2. The plurality of drivers each comprises a pull-down transistor having a gate connected to the output of an associated gate, and a pull-up load, wherein the isolation means comprises an associated decoded address. An isolation transistor having its gate connected to a signal, said isolation transistor being non-conductive in response to said decoded address signal indicating deselection of its data signal, 2. The column selection circuit according to claim 1, wherein the pull-up load of the pull-down transistor and the isolation transistor and the source-drain path are connected in series between the power supply node and the reference node. 3. The pull-up load is a transistor, having a gate coupled to receive the output of its associated gate, connected in series with the source-drain path of the pull-down transistor and the isolation transistor. The column selection circuit according to claim 2, further comprising a source-drain path that is present. 4. The column select circuit of claim 1, wherein each of said gates exhibits a first logic state in response to an associated decoded address signal indicating the deselection of a data signal. 5. A pull-down transistor having its gate coupled to the output of an associated gate, said plurality of drivers comprising an associated decoded signal receiving an output of an associated gate to indicate deselection of a data signal. A pull-up transistor having a gate coupled to render the pull-up transistor non-conductive in response to an address signal, the isolation means coupled to receive an associated decoded address signal. The isolation transistor has a gate, and the isolation transistor becomes non-conductive in response to the above-mentioned decoded address signal indicating the non-selection of the data signal, and the source-drain path of the pull-down transistor is the above-mentioned. Source-drain path and base of isolation transistor Connected in series between the quasi-nodes, the source-drain path of the pull-down transistor is connected in series between the source-drain path of the isolation transistor and the power node, and the output of the driver is The column selection circuit according to claim 4, wherein the column selection circuit is located at a junction of the up transistor and the isolation transistor. 6. A multi-stage column decoder for selecting a data line of a memory device corresponding to a column address signal, comprising: a first address signal decoder for decoding a predetermined number of bits of the column address signal; A second address signal decoder for decoding a predetermined number of bits of the column address signal other than the signal decoded by the first address signal decoder, each of the plurality of data lines of the storage device and the second data line of the storage device. A plurality of first selection stages connected to the output of one address signal decoder, each of which selects a corresponding data line of the output from them in response to the output of the first address signal decoder; Each of the above-mentioned first selection stages comprises a second selection stage, each receiving a data signal. And an input for receiving the decoded address signal from the first address signal decoder, each of which outputs a signal corresponding to the data responsive to the decoded address signal for instructing the selection of the data signal. A plurality of gates having outputs to represent, each of which is associated with one of the plurality of gates and is connected to the output of its associated gate in a logic state corresponding to the output of its associated gate. Isolation means driving the outputs and placing their outputs in a high impedance state in response to the above decoded address signals each connected to its corresponding decoded address signal to indicate deselection of its data signal. A plurality of drivers having a plurality of drivers, and the outputs of each of the plurality of drivers in the first selection stage are A second select stage connected to the outputs of the plurality of first select stages and to the output of the second address signal decoder to provide the decoded address from the second address signal decoder. A multi-stage column decoder configured to select one of a plurality of outputs of a first selection stage in response to a signal. 7. The second selection step comprises an input for receiving an associated output of the first selection step, and an input for receiving a decoded address signal from the second address signal decoder, respectively. A plurality of gates, each having an output for representing a signal corresponding to the output of its associated first selection stage in response to a decoded address signal directing its selection, and to each of said plurality of gates. Associated, each connected to the output of its associated gate to drive its output to a logic state corresponding to the output of its associated gate, and each connected to its corresponding decoded address signal. And a plurality of drivers for placing its output on the high impedance corresponding to the above decoded address signal indicating the deselection of its associated first selection stage. 7. An actuator, wherein each of said plurality of drivers of said second selection stage is connected together to represent one selected output of said first selection stage. Column decoder. 8. A set bit comprising a plurality of second selection stages, wherein said column address signal other than the address signals decoded by said first and second address signal decoders is defined. A third address signal decoder for decoding a number of address signals, and a plurality of outputs of the second selection stage and an output of the third address signal decoder from the third address signal decoder. 7. The column decoder according to claim 6, comprising a third selection stage for selecting one of the outputs of the plurality of second selection stages corresponding to the decoded address signal. 9. The third selection step has an input each receiving an associated output of the second selection step and an input receiving the output of the third address signal decoder, and each A plurality of gates having an output for representing a signal corresponding to the output of its associated second selection stage in response to a decoded address signal indicating the selection, and each associated with said plurality of gates, respectively. It has its input connected to the output of its associated gate and drives its output to a logic state corresponding to the output of the associated gate, and each is connected to its corresponding decoded address signal and its associated And a plurality of drivers which put their outputs in a high impedance state in response to a decoded address signal instructing selection in the second selection stage. A plurality of one of the column decoder of claim 8, wherein the adapted represent the output, respectively that which was both selected and is connected with the second selection stage driver selection round.