JPH04178011A - Selector - Google Patents

Abstract

PURPOSE:To attain output selection with a small propagation delay time by decoding a selection signal so as to form a control input of tri-state buffers except one tri-state buffer connecting to each input terminal into a high impedance state. CONSTITUTION:Three sets of selection signal inputs 31-33 are decoded by a decode circuit 7 provided with three sets of inverters 8, eight sets of NAND gates 6 and an 8-bit control input 2 controlling three-state buffers 21-28 corresponding to eight sets of data input terminals 11-17 respectively is generated. Only one bit of the input 2 is set to zero and the other bits are set to '0' and only one buffer is selected and outputted corresponding to the input '1' or '0' of the relating terminals 11-18. The selection output is a selection output with a small propagation delay time not through a gate or through a gate.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a selector, and more particularly to a selector that selects one input from a large number of inputs in a digital circuit.

[Conventional technology]

When configuring a digital circuit, it may be necessary to select one from a number of data signals.

In such cases, a circuit called a selector is used. Here, an example will be explained in which one of eight data inputs is selected. FIG. 2(a) is a block diagram showing the configuration of an 8:1 selector, and FIG. 2(b) is a logic circuit diagram showing the 2:1 selector 5 in FIG. 2(a).

The 2:1 selector 5 is composed of two NOR gates 6, and the output Q thereof is Q=A-8+B-th. In other words, when S=1, Q=A, and when S=0, Q
=B is output. This 2:1 selector is shown in Figure 2 (a).
When combined as shown below, an output as shown in the truth table shown in Table 2 is determined depending on the combination of S1 and 82°S3.

[Problem to be solved by the invention]

However, the selector configured according to the conventional example has the disadvantage that the signal propagation delay time is large because it has to pass through many logic gate circuits. For example, in the conventional example shown in FIG. 2, the number of logic gates passed through is six. This drawback becomes even greater as the number of input signals increases.If the delay time of a two-man NOR gate is tpd, and the number of input signals is N, where N is a power of 2, the propagation delay time of the selector is 2 tpd. -1ogzN, and as N increases, the propagation delay time increases.

The present invention solves the above problems and provides a selector that has a small propagation delay time and does not increase the delay time even when the number of input signals increases.

[Means to solve the problem]

The selector of the present invention includes a plurality of data input terminals, a selection signal input terminal for selecting one of the input terminals, and a selection signal input terminal for selecting one of the input terminals.
The number of 3-state circuits is the same as the number of data input terminals and can take on three types of states: no-level, low-level, and high-impedance. Only one of the 3-state circuits can be set to a state other than high-impedance by a selection signal, and the other It consists of a decoding circuit that generates a signal that puts the 3-state circuit into a high impedance state, and a d-power terminal.The inputs of the 3-state circuit are each connected to a data input terminal, and all outputs are connected to an output terminal. It is characterized in that the output of the decoding circuit is connected to the control terminal.

〔Example〕

Regarding the embodiment of the present invention, taking an 8:1 selector as an example,
The following will be explained using the drawings. FIG. 1 is a logic circuit diagram showing an embodiment of the present invention. 8 data input terminals 11
, 12, 13, 14, 15° 16. 17. 18 are 3-state buffers 21. 22, 23, 24, 25, respectively.
26, 27, and 28. Also, 3
The selection signal inputs 31, 32, 33 correspond to the eight three-manpower N
It is analyzed by the decoding circuit 7 consisting of AND game) 34, 35, and 36, and the 3-state buffer 21°2
2.23, 24, 25, 26, 27.28 control terminal 2
A signal is generated that is input to the As shown in Table 1, according to the combination of selection signals 31, 32, and 33, only one 3-state buffer control signal becomes "O" and the other control signals become "1". Become. The 3-state buffer takes a value of 111 y+ or "0" depending on the input data when the control input 2 is "0", and if a high impedance circuit is used when the control signal 2 is 1", only one 3-state buffer Only the output of the state buffer is output to the output terminal 3, and the signal of one data input terminal is selected.

In this embodiment, the only gate through which data is output is the 3-state buffer stage, so the delay time is smaller than in the conventional example. Furthermore, since this number of stages does not change even if the number of inputs increases, it has the characteristic that a small delay time is maintained even if the number of inputs increases.

In addition to the embodiments described above, it is also possible to configure the decoding circuit using other logic gates. Also,
In addition to the 3-state buffer of the above embodiment, it is also possible to use a 3-state inverter or a 3-state circuit that has a high impedance when the control signal is "0".

〔Effect of the invention〕

According to the present invention, it has become possible to configure a selector with a small propagation delay time. Since this circuit has excellent high-speed performance, it is extremely effective when applied to digital circuits that require high-speed processing such as optical communications.

[Brief explanation of drawings]

FIG. 1 is a logic circuit diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram and logic circuit diagram showing a conventional example. 1...3-state buffer data input, 2.
...3-state buffer control input, 5...
・・2:l selector, 6・・・・・・2-man power N0R11
1,12°13.14,15,16,17.18...
...Data input terminal, 21, 22, 23, 24, 25
,26゜27.28...3 state buffer, 7
...Decode circuit, 8...Inverter. Agent Patent Attorney Uchihara Otomo J Figure

Claims (1)

[Claims] A plurality of data input terminals, a selection signal input terminal for selecting one of the input terminals, and three states capable of assuming three types of states: high level, low level, and high impedance, the same number as the number of data input terminals. circuit, and a decoding circuit that generates a signal that changes only one of the three-state circuits to a state other than high impedance based on a selection signal and puts the other three-state circuit in a high impedance state, A selector characterized in that each input is connected to a data input terminal, all outputs are connected to an output terminal, and the output of a decoding circuit is connected to a control terminal.