JPS61157936A - Data shifting circuit - Google Patents

Abstract

PURPOSE:To make a data inversion circuit unnecessary and to shorten the execution time by employing three try state gates for the operation of one bit in order to shift or rotate data in right and left sides. CONSTITUTION:In terms of the data operating circuit 22 of two bits for executing the data shift and rotation, three try state gates 201-224 are provided with respect to each bit of input data of eight bits. Respective codes 202, 205, 208, 211, 214, 217 220 and 223 at every one bit in three gates input corresponding bits D10-D17. Other codes 201, 204, 207, 210, 213, 216, 219 and 220 in the remaining two gates input bits D16, D17, D10, D11, D12, D13, D14 and D15, which rotate in the left side by two bits from the corresponding bits, and the data operation of two bits is executed in the left side.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a data shift circuit that shifts or rotates multiple bits of data by an arbitrary number of focuses.

2. Description of the Related Art Conventional data shift circuits include, for example, the one disclosed in Japanese Patent Application Laid-Open No. 1986-
It is shown in the 91541 publication.

FIG. 3 is a diagram showing the block configuration of the conventional data shift circuit, in which 11 and 12 are latch circuits that hold data, and 32 and 36 are inputs for inputting data bit positions to perform right or left shift or rotation operations. In this data reversal circuit, data reversal means to set each bit of data D0 to Dn to DD . . . Do. 34i.

nl n-1 34...341.34° has a data shift number or rotation number of 2i and 2i-1, respectively.
, 21, 2° data manipulation circuit, each data manipulation circuit has a first and a second tri-state gate corresponding to each bit of multiple bits of data; The data of the corresponding bit is input to the input terminal of the first tri-state gate, data other than the above-mentioned bits is input to the input terminal of the second tri-state gate, and the output of the first and second tri-state gates is By connecting the ends in common, the number of data shifts or rotation bits can be reduced to 2.
It constitutes a 5-bit (however, 1 is an integer greater than or equal to 0) data manipulation circuit. Reference numeral 36 denotes a control means for selectively operating the first and second tristate gates in the data manipulation circuits of each stage in accordance with each digit of the binary data corresponding to the number of data shift/rotation bits. 33 is a control means for controlling whether or not the data inversion circuits 32 and 36 perform bit inversion.

In the conventional data shift circuit configured as described above, the latch circuit 11 holds data, and the control means 33
0 control signal causes the data inversion circuit 32 to invert the bits, and a control signal from the control means 36 causes the data manipulation circuit 34. . . . Determine whether to open the first or second tristate gate for each bit of 34°.

In other words, depending on the combination of how these gates are opened, the shift/
The number of rotation bits is determined. The bits of the shifted or rotated data are reversed by a data reversing circuit controlled by the control circuit 33, and the results of the operations designated by the control circuits 33 and 36 are stored in the launch circuit 12.

Problems to be Solved by the Invention However, in the above configuration, a data inversion circuit is required in order to shift or rotate in both left and right directions, so when the number of shift/rotation bits is small, data passing Since there are many stages to perform, the execution time will be long.
Furthermore, in order to configure the data inversion circuit in two stages, the number of tristate gates required is four times the number of data bits, resulting in a disadvantage that the circuit configuration becomes large.

In view of this, an object of the present invention is to provide a data shift circuit that has a short execution time and does not require a data inversion circuit in order to reduce the circuit configuration even when the number of shift/rotation bits is small. .

Means for Solving the Problems The present invention provides first .
Second. It has a third tri-state gate, the data of the corresponding bit is input to the input terminal of the first tri-state gate, and the second... Data other than the above-mentioned bits is input to the input terminal of the third tri-state gate. Second
and the output ends of the third tri-state gates are commonly connected to form a data manipulation means in which the number of data shifts or the number of data rotations is 2' (t is an integer greater than or equal to 0) bits in both left and right directions, and each data shift is different. A column structure in which a plurality of the above-mentioned data operations having a number or number of rotations are connected in cascade, and a number of data operations in the data operation means of each stage according to each digit of binary data representing the number of data shifts or the number of data rotations. 1. A data shift circuit is configured by a control means that selectively operates the second and third tristate gates.

Effect of the Invention With the above-described configuration, the present invention uses three tri-state gates for one bit operation in order to shift or rotate data in both left and right directions.
This eliminates the need for a data inversion circuit that performs bit inversion, which was required when using three tristate gates, resulting in a reduction in execution time.

Embodiment FIG. 1 is a block diagram of a data shift circuit according to a first embodiment of the present invention, and shows a case in which n-bit length data is shifted or rotated in both left and right directions. 1o is
Data D0-D before being manipulated (however, Do is MS
In B, Dn is LSB. ) is a latch circuit that holds
11i transfers the output data of the latch circuit to 2i in both left and right directions.
Bit shifting or rotating data manipulation circuit, 11t-1
・・・・・・11° is 2′ in both left and right directions like 111
-1...2 This is a data manipulation circuit that performs a bit shift or rotation. A latch circuit 12 holds the output of the data manipulation circuit 11°, and holds the output result of the data shift circuit. 13 is a control circuit which inputs the R0fi'R signal that determines the shift or rotation operation, the L E/R signal that determines the shift or rotation direction, and the C-C that specifies the number of shifts or number of rotations, and performs data operation. Circuit 11L~
It outputs a control signal 14 that controls the operation of the tri-state gate within 11 degrees.

The operation of the data shift circuit of this embodiment configured as described above will be explained below. Data is held in the latch circuit 10 and the input signal L E/ to the control circuit 13 is
When R, ,C0...-C, and R0/ are input, the control circuit 13 sends a control signal 14 to select a tristate gate to be opened for each bit in the data manipulation circuit 11.about.11°. Output. In the data manipulation circuit 11i,
Input the output of the latch circuit 10 and output it as is, or
Alternatively, the shift/rotation of 2' bits is performed in either the left or right direction and output based on the control signal 14, and the next stage data manipulation circuit 11. , output to. Data manipulation circuit 11. , the same selection as in the data manipulation circuit 11i is performed, and the data is output to the next stage data manipulation circuit 11t-2. Similar operations are sequentially performed on data in the data operation circuits 11i-2 to 11i-11. At the bottom 11° of the data manipulation circuit, it is selected whether to shift/rotate 2 bits, that is, 1 bit in either the left or right direction and output it, or to output the input data as it is, and the selected operation is performed. After performing this, it is output to the latch circuit 12. The number of shifts/rotations performed by this data shift circuit is determined by the combination of the data manipulation circuits 11i to 11°, that is, the sum of the number of shift/rotation bits of the data manipulation circuits that perform shift/rotation. In this case, data manipulation circuit 1
1. ~11° does not shift and rotate the data at the same time.

FIG. 2 is a circuit configuration diagram that embodies the plug diagram of FIG. 1 with a data length of 8 bits. In FIG. 2, the data manipulation circuits 21, 22, and 23 each have a tryout whose output terminal signal takes on three states: logic level 1, logic level 0, or high impedance state, depending on the signal state of the input terminal and control terminal. Consists of state gates.

The data manipulation circuit 21 that performs 4-bit data shifting or rotation is composed of two tri-state gates for each bit of 8-bit input data, and the tri-state gates 101, 1 of the data manipulation circuit 21
03, 105, 107.

Each input terminal of 109.111.113, 116 has a corresponding bit, that is, Do, Dl, D2 . D3゜D
4. D6. D6. D7 (D0=MSB, D7□LSB
) and the other dry state game) 102゜104.106,108,110,112,114,1
16° is bit D rotated by 4 bits from the corresponding bit.
4°D6. D6. D7. Do, Dl, D2. By inputting D3, 4-bit data manipulation is performed.

Output terminals of each bit, that is, tristate gates 1o1 and 102, 103 and 104, 105 and 10S,
107 and 108, 109 and 110゜111 and 112
, 113 and 114, and the output terminals of 115 and 116 are commonly connected. The output of each bit. , D44. D
12. D13. D14. D.6. D, 6°D, 7. shall be. Note that in order to shift/rotate in both left and right directions,
Three tri-state gates should be provided for each bit, but in this case (shift/rotation number is 4 bits), input is from the same bit regardless of whether it is shifted/rotated to the left or right, so each bit must be tri-stated. It is written with one gate omitted.

Data manipulation circuit 2 that performs 2-bit data shift/rotation
In No. 2, three tristate gates 201 to 224 are provided for each bit of 8-bit input data. 1 of 3 tri-state gates for each bit
pieces 202,205゜208.211.214,217,
220 and 223 are corresponding bits・DlosDl 1
tDl 2 tDl3 tDl 4 +D16. D16
．． Input D1□ respectively, and one of the remaining two tri-state gates of the three tri-state gates for each bit 201.204, 207° 210.213, 21
6,219,220 are bits rotated 2 bits to the left from the corresponding bits, that is, D16°DI7tDIQID1
1 Input eDj2PDj3fiDj4WD15 and perform 2-bit data manipulation to the left 〇Remaining tri-state gates for each bit 203゜206, 209
,212.21+5,218,221.

224 M Pit position rotated 2 bits to the right, that is, D12FD11D14PD151D161D171D1
(Input from ID1., and perform data manipulation of two right-pointed pits. In addition, three tri-state gates for each bit,
That is, 201, 202, 203, 204, 206, 206, 207, 208, 209, 210, 211, 2
12, 213 and 214 and 215, 216 and 217 and 21
8, 219 and 220 and 221, 222 and 223 and 224
The output terminals of the two are connected in common. Each signal is D2
0・D21・D22・D23・D24・D25・D26
．． D27 Data manipulation circuit 2 that performs 1-bit data shift/rotation
3 also has three tristate gates 301 to 324 for 8-bit input data. One of the three tri-state gates for each bit 302, 305
,308,311.314°317.320,323 are the corresponding bits, namely D201D21 ID221
D231D241D25 and FD261D27 are input in order. One of the remaining tristate gates for each bit, 301.304, 307° 310.313, 31
6,319,320,323. are bits shifted one bit to the left, that is, D2□, D2°.

Input D21, D22, D23, D24, D25, and D26 and perform 1-bit data manipulation to the left. The remaining tristate gates for each bit 303, 306° 309.312, 315, 318, 321.324 are
Right pit shifted by one bit to the right from the corresponding bit, that is, D21, D22, D23, D24, D26, D26, D
Input 27 and perform a 1-bit data operation to the right.

3 tri-state gates for each bit i.e. 301
and 302 and 303. 304 and 306 and 306° 307 and 308 and 309, 310 and 311 and 312° 313 and 3
The output terminals of 14, 315, 316, 317, 318°3'19, 320, 321, 322, 323, and 324 are commonly connected.

The control circuit 13 that controls the operation of the data manipulation circuits 21, 22, and 23 inverts the signals C2, C1, and C2, respectively, and
It is composed of inverters 24, 25, 26 that output to data manipulation circuits 21, 22, 23, NOR gates 27.28 and NAND gates 31 to 40 for signal coding, and when inverter 24 outputs logic 1, data manipulation Tri-state gate 102, 10S of circuit 21
, 108°111, 114, 117, 120, and 123 are selected, and the data manipulation circuit 21 outputs the input data without shifting/rotating it. Similarly, inverters 25.26 are input to data manipulation circuits 22.23, and 202.2
05,208,211.214,217°220.22
3 and 302, 305, 308, 311.

314, 317, 320, and 323 are selected, and when the above tristate gate is selected, the data manipulation circuits 22 and 23 output without shifting/rotating the data. 0 NAND gate 31 outputs logic 1 when shift/rotation number is 4 bits or more and left shift/rotation or right rotation, NAND gate 32 outputs logic 1 when shift/rotation is 4 bits or more and right Outputs logic 1 in case of shift/rotation or left rotation.

NAND33-36 has a shift/rotation speed of 2°3.6
．． In the case of 7 bits, NAND33 is used only for clockwise rotation, and NAND34 is used for leftward shift/rotation.
NDss is NANDs for rightward shift/rotation.
6 outputs logic 1 only in case of leftward rotation. NAN
D37 to 4o are for odd number of shifts/rotations, and NA
ND37 outputs a logic 1 only for clockwise rotation, NDND38 for leftward shift/rotation, NAND39 for leftward shift rotation, and NAND40 outputs a logic 1 only for leftward rotation. NAND33 and 34°NAND3
5 and 36. NAND37 and 38. NANDs 39 and 40 do not output logic 1 at the same time. The number of shifts/rotations is determined by the signals C0 to C2. For example, when shifting/rotating by 1 bit, only C0 is set to logic 1; when shifting/rotating by 4 bits, only C2 is set to logic 1. The signal R0/SH determines a shift or rotation operation; if the signal R0/SH is a logic 1, a rotation is performed, and if it is a logic 0, a shift operation is performed. Also signal LE/R.

determines whether it is a rightward or leftward operation, and the signal L E/R
When , is a logic 1, the operation is performed leftward, and when it is a logic 0, the operation is performed rightward.

Next, the operation shown in FIG. 2 will be explained. First, we will explain the case where input data is rotated 3 bits to the left and output. To perform this operation, the signals C0 and C1 must be set to logic 1, and the signal C2
is set to logical 0 to give the rotation speed, and the signal R0/
Set SH to logic 1, set the rotation operation, and send the signal LE/
R, is set to logic 1, and the signal C sets the leftward operation.
2 is a logic 0, the inverter 24 outputs a logic 1, NA
ND gates 31 and 32 output logic zeros. Therefore, the operation cycle 21 is a dry state game) 101, 103° 10
5.107, 109, 111.113, and 115 are selected, and the input data D0 to D7 are output as they are.

Also, since C1 is logic 1, inverter 26 is logic 0.
Since the signal LE/R, is logic 1, the NAND game) 34.35 outputs logic 1 and 0, respectively, and the signal R0
Since /SH is logic 1, NAND gates 33 and 36
output logic 0 and 1, respectively. Therefore, the data manipulation circuit 22 has tristate gates 203, 206.2.
09,212.

215.218, 221.224 are selected, bit o
II-i, D12, Hila) 1 is D13 k, bit 2 is D14, bit 3 is D16, bit 4 is D16, bit 6 is D1□, bit 6 is Dl.

, bit 7 outputs Dll. Therefore, the input data sequence was D0 to D7, but D2. D3. D4. D
, ,D6°D7. Do, D, and a rotation of 2 bits to the left is performed.

In the data manipulation circuit 23, the inverter 26 outputs logic 0, and the NAND gates 37 to 40 output logic 0 and 1, respectively.
．． Since it outputs 0.1, the tri-state gates 303, 306° 309, 312, 31 of the data manipulation circuit 23
5,318,321.324 is selected. The output of the data manipulation circuit 22 is Dlo"D21D11"D, respectively.
31D12"Dl 1D13"D51D14=D61
Dl 5”D71 Dl 8=DOI Dl 7”DI
Therefore, the output of the data manipulation circuit is D3. D
4°D5. D61D7. Do, D4. It becomes D2. The output of this data manipulation circuit 23 is input to the latch circuit 12 and held there. Note that data up to the latch 1o is held until the output of the data manipulation circuit 23 is determined. Next, a case of shifting 4 bits to the right will be explained. Set the signals C0 and C1 to logic 0, set C1 to logic 1, and set the signal L
Set E/Rl to logic zero.

In this case, in the data manipulation circuit 21, the inverter 24
outputs a logic 0, and NAND gates 31 and 32 each output a logic 0.1. Therefore, the tristate gate 110
, 112, 114, 116 are selected 'Dl 4''D
OI Dl 5=D11D16"D21DI?=D3. Since the outputs of inverters 26 and 26 output logic 1 in data manipulation circuits 22 and 23, tristate gates 202 and 205.

20ES, 211.214, 217, 220, 223 and 302.305, 308, 311.314, 317°320.323 are selected, and each bit is input from the corresponding bit, so the output of the data manipulation circuit 21 is The signal is input to the latch circuit 12 as is.

Note that in this case, since the signals C0 and C1 are logic 0, N
AND gates 33-40 all output logic level 0.

By the above operation, a shift of 4 bits to the right is performed.

Note that when performing a shift, there are bits in the data manipulation circuit for which no tristate gate is selected. For example, in the case of the above shift example, the data manipulation circuit bits o to bits 3 to dry state gates 101 to
108 is not selected. Therefore, the output of that bit will be in a floating state, but if an impedance element such as a resistor is installed between the output side and the reference point, the output will be 70%.
- It can be set to logic 0 even when the current state occurs.

As described above, according to this embodiment, a data manipulation circuit is configured using three tristate gates for each bit, and data manipulation circuits with different shift/rotation speeds are connected in series in multiple stages. If you perform similar gongyo by
It is possible to perform semantic pit shift/rotation operations in both left and right directions without using a bit reversal circuit that performs bit swapping, which was necessary in the past, and the execution speed can be increased.

As described in detail, the present invention eliminates the need for a bit reversal circuit that swaps bits, which was necessary for shifting/rotating in both left and right directions, thereby increasing the execution speed of the data shift circuit. This is particularly effective when the data length is short, and its practical effects are great.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data shift circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram embodying the same embodiment, and FIG. 3 is a block diagram of a conventional data shift circuit. 10.12...Latch circuit, 111-110.
...Data manipulation circuit, 13...Control circuit, 14...Control signal, 34i~34°...
...Data manipulation circuit, 32゜36...Data reversal circuit, 33,35...Control circuit, 101-1
16, 201-224, 301-324...
Tri-state gate, 24-26...Inverter, 27-28...NOR gate, 29-4
o...NAND gate. Name of agent: Patent attorney Toshio Nakao and 1 other person
1 Figure 2I71

Claims (1)

[Claims] For each bit of multi-bit data, the first and second
and a third tri-state gate, each of the first
The corresponding bits of data are provided as inputs to the tristate gates of The output terminals of the state gates are commonly connected for each bit, and the number of data shifts or data rotations constitutes a data manipulation means of 2^i bits (however, i is an integer greater than or equal to 0) in both left and right directions, and each has a different number of data shifts or rotations. A cascade structure in which a plurality of the above-mentioned data manipulation means having a data shift number or a data rotation number are connected in cascade, and a data manipulation means of each stage according to each digit of binary data corresponding to the data shift number or data rotation number. 1. A data shift circuit comprising control means for selectively operating first, second, and third tristate gates in the data shift circuit.