CN116760416A

CN116760416A - Double-configuration-mode high-precision oversampling analog-to-digital converter control module

Info

Publication number: CN116760416A
Application number: CN202311008543.3A
Authority: CN
Inventors: 李大刚; 李泽宏; 李威; 何弢; 杨绍澎
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2023-08-11
Filing date: 2023-08-11
Publication date: 2023-09-15
Anticipated expiration: 2043-08-11
Also published as: CN116760416B

Abstract

The invention relates to a control module of a double-configuration mode high-precision oversampling analog-to-digital converter, belonging to the field of analog integrated circuit design. Conventional high-precision oversampling ADCs all use a single mode to control the ADC functions, such as using a pin only mode or using a register configuration mode only, which can lead to inflexible register configuration. In order to solve the problem, the invention provides a circuit structure, and the selection of the function of the IO port and the selection of the input and output of the IO port are realized through control signals, so that the high-precision oversampling analog-to-digital converter in a double configuration mode is realized, and the configuration of the ADC is more flexible.

Description

Double-configuration-mode high-precision oversampling analog-to-digital converter control module

Technical Field

The invention belongs to the field of analog integrated circuit design, and particularly relates to a control module of a double-configuration-mode high-precision oversampling analog-to-digital converter.

Background

Analog-to-digital converters (ADCs) are an indispensable key element in the field of analog integrated circuit design and in the field of analog-to-digital hybrid processing, where high-precision oversampling ADCs are one branch of wide application.

Conventional high-precision oversampling ADCs all use a single mode to control the ADC function, such as pin only mode, as shown in fig. 1. The pin mode is to directly configure the functions of the chip by using pins of the chip. This is simple and reliable for simple applications. The PCB used on the periphery of the chip is relatively simplified without complex configuration design. But this has the disadvantage that the PCB design does not have the possibility to adjust and modify the configuration later on, resulting in inflexible chip usage environment.

Later, for high-precision oversampling ADCs, internal registers have been developed to control and configure the chip, such as the ADS1258 chip of TI corporation, and users can flexibly configure the high-precision oversampling ADC using complex register combinations inside the chip. The advantage of this is that when the ADC is controlled by the control chip such as FPGA or MCU, the function of the ADC chip can be modified on site by changing the configuration code of the FPGA or MCU, so that the use condition of the chip is improved obviously. However, this brings about the corresponding disadvantage that the configuration codes are generally stored in a memory chip, which is susceptible to external interference, and if the codes are stored without using a nonvolatile memory, the configuration information is lost when the entire system is powered down.

From the system design complexity, the peripheral circuits used in the pin mode are simple and reliable, and do not need to use a memory to store configuration codes, but are inconvenient to modify after design determination. The peripheral design of using the internal register to control and configure the ADC chip is complex, the control chip and the memory chip such as the FPGA or the MCU are used, the design difficulty is high, but the functions of the ADC are more flexibly changed, such as the field replacement of a sampling channel and the like, and more ADC peripheral functions are realized.

Disclosure of Invention

In order to optimize the mode control mode of the high-precision oversampling ADC and solve the defects of pin mode and control by using an internal register, the invention provides a novel internal design structure of the high-precision oversampling ADC, and the selection of the function of an IO port and the selection of input and output of the IO port are realized through control signals.

The working principle is as shown in figure 2:

the control module comprises a circuit signal gate Mux1, a circuit signal gate Mux2, an input buffer INBUF, an output buffer OUTBUF, an inverter and a digital module;

PINMOD generates Control signals PINMOD Control, PINM1 and PINM2 through a digital module, IO Pin is an ADC chip Pin, PINMOD Control is directly connected with the Control end of an input buffer INBUF and is connected with the Control end of an output buffer OUTBUF after passing through an inverter; the input end of the input buffer INBUF is connected with the IO Pin, and the output end of the input buffer INBUF is connected with the input end of the circuit signal gating device Mux 1; the input end of the output buffer OUTBUF is connected with the output of the circuit signal gate Mux2, and the output end of the output buffer OUTBUF is connected with the IO Pin; the output of the circuit signal gating device Mux1 is connected with the function 1 and the function 2 inside the ADC chip, and the selection is performed through PINM 1; the input of the circuit signal gating device Mux2 is connected with the function 1 and the function 2 inside the ADC chip, and the selection is performed through PINM 2;

the circuit signal gate Mux1 and the circuit signal gate Mux2 are composed of digital codes, and function 1 or function 2 is selected through PINMOD control signals PINM1 and PINM 2; the input buffer INBUF and the output buffer OUTBUF have the same structure and play a role in buffering signals.

The control of the chip port is realized through the module, so that the mode switching is realized. The configuration of the chip is more flexible.

Drawings

FIG. 1 is a conventional single mode control;

FIG. 2 is a schematic diagram of the IO PIN controlled by the PINMODE signal;

fig. 3 is a schematic diagram of a control chip configuration mode using a PINMODE.

Description of the embodiments

The embodiments will be described in detail below with reference to the accompanying drawings.

Fig. 2 is a schematic diagram of an IO Pin controlled by a PINMODE signal.

The PINMOD Control can Control whether the IO Pin is an input Pin or an output Pin, when the PINMOD Control is in a high level, the input buffer INBUF is started, the output buffer OUTBUF is closed, the IO Pin is an input Pin, and signals are input from the outside; when PINMOD Control is low level, the input buffer INBUF is closed, the output buffer OUTBUF is opened, IO Pin is an output Pin, and signals are output from the inside;

PINM1 controls whether a signal input from IO Pin is control function 1 or function 2, and connects function 1 when PINM1 is high level and connects function 2 when PINM1 is low level. PINM2 controls whether a signal output from IO Pin is from function 1 or function 2, and when PINM2 is at a high level, a signal of IO Pin is from function 1, and when PINM2 is at a low level, a signal of IO Pin is from function 2.

When a PINMODE pin is connected with a power supply, control signals PINM1 and PINM2 generated by a digital module are in high level, so that the pin is connected with a function 1, PINMOD Control is generated according to the input or output requirement of the pin, when the pin is an input pin, the generated PINMOD Control is in high level, when the pin is an output pin, the generated PINMOD Control is in low level, and at the moment, the chip is in a pin configuration mode;

when the PINMODE pin is grounded, the Control signals PINM1 and PINM2 generated by the digital module are in low level, so that the pin is connected with the function 2, PINMOD Control is generated according to the input or output requirement of the pin, when the pin is an input pin, the generated PINMOD Control is in high level, when the pin is an output pin, the generated PINMOD Control is in low level, and at the moment, the ADC chip is in a register configuration mode.

Fig. 3 is a schematic diagram of a chip configuration mode controlled by using PINMOD, in which typical IOs of chips are on the left and right sides, and configuration states of different chips IO Pin can be controlled by using independent PINMOD. Typically, an analog modulator and a digital filter are included in the high-precision oversampling ADC, and a series of control logic is added to the periphery of the digital filter to form a digital control module of the ADC. Each pin to be multiplexed uses the structure shown in fig. 2 to realize different pin functions in different modes.

SCLK for the left port is the SPI clock, DIN/MOD sharing one IO Pin. When the chip is in a register configuration mode, the PINMODE pin is grounded, under the control of a control signal generated by PINMOD, the DIN/MOD pin is set as an input terminal, and then the corresponding PINM1 sets the function as DIN, so that SPI data can enter from a DIN port. When the chip is in pin configuration mode, the PINMODE pin is powered up, and in a similar manner as described above, the port will be defined as MOD that can be used to accept either 0 or 1 to configure the ADC chip.

The M1 and M0 ports on the right output the SDM modulated data of the ADC when the chip is in pin configuration mode. The chip switching speed is configured as DR1 and DR0 when the chip is in register mode.

DOUT is the data serial output port of the chip from which the final processed data is transferred to an external FPGA or MCU chip to collect the ADC conversion results.

When the chip enters the pin configuration mode, SYNC will provide a synchronized signal input because there is no synchronized clock inside the chip, and this synchronized signal input can make the result of each sampling of the ADC chip in a mode that can be controlled by a user. The chip is in register configuration mode, SYNC need not provide a synchronization signal, since SCLK will become the synchronization clock in this mode. Register configuration mode the function of this pin will change from providing a synchronization signal input to a control signal that can control the on or off of the high pass filter inside the chip.

MCLK is the chip master clock output of the ADC chip in pin configuration mode, and users can use MCLK of the chip to drive other chips when the chip is used, so that other chips can be synchronized by the ADC chip. The PHS can select the size of the internal digital filter when the chip is in register configuration mode.

By controlling the PINMODE to be connected with a power supply or ground and combining control modules with different functions, the flexible conversion of a pin configuration mode and a register configuration mode is realized by corresponding different pin functions under different PINMODEs, and the defect that only one single mode exists is overcome.

Claims

1. The control module of the double-configuration mode high-precision oversampling analog-to-digital converter is characterized by comprising a circuit signal gating device Mux1, a circuit signal gating device Mux2, an input buffer INBUF, an output buffer OUTBUF, an inverter and a digital module;

PINMOD generates Control signals PINMOD Control, PINM1 and PINM2 through a digital module, IO Pin is an ADC chip Pin, PINMOD Control is directly connected with the Control end of an input buffer INBUF and is connected with the Control end of an output buffer OUTBUF after passing through an inverter; the input end of the input buffer INBUF is connected with the IO Pin, and the output end of the input buffer INBUF is connected with the input end of the circuit signal gating device Mux 1; the input end of the output buffer OUTBUF is connected with the output of the circuit signal gate Mux2, and the output end of the output buffer OUTBUF is connected with the IO Pin; the output of the circuit signal gating device Mux1 is connected with the function 1 and the function 2 inside the ADC chip, and is selected by the control signal PINM 1; the input of the circuit signal gating device Mux2 is connected with the function 1 and the function 2 inside the ADC chip, and is selected through the control signal PINM 2;

2. The control module of claim 1, wherein the ADC chip is in a pin configuration mode when the PINMOD is connected to the power supply, and is in a register configuration mode when the PINMOD is connected to the ground, specifically:

when the PINMOD pin is connected with a power supply, control signals PINM1 and PINM2 generated by the digital module are in high level, so that the pin is connected with the function 1, a Control signal PINMOD Control is generated according to the input or output requirement of the pin, when the pin is an input pin, the generated PINMOD Control is in high level, when the pin is an output pin, the generated PINMOD Control is in low level, and at the moment, the chip is in a pin configuration mode;

when the PINMOD pin is grounded, the Control signals PINM1 and PINM2 generated by the digital module are in low level, so that the pin is connected with the function 2, PINMOD Control is generated according to the input or output requirement of the pin, when the pin is an input pin, the generated PINMOD Control is in high level, when the pin is an output pin, the generated PINMOD Control is in low level, and at the moment, the ADC chip is in a register configuration mode.

3. The control module of claim 2, wherein function 1 is M1/M0 in a pin configuration mode and function 2 is DR1/DR0 in a register configuration mode.

4. The control module of claim 2, wherein function 1 is MOD in a pin configuration mode and function 2 is DIN in a register configuration mode.

5. The control module of claim 2, wherein function 1 is a control signal providing a synchronization signal input in a pin configuration mode, and function 2 is a high pass filter on or off inside a chip in a register configuration mode.

6. The control module of claim 2, wherein function 1 is MCLK in pin configuration mode and function 2 is PHS in register configuration mode.