CN110492887A - Analog-digital converter circuit - Google Patents
Analog-digital converter circuit Download PDFInfo
- Publication number
- CN110492887A CN110492887A CN201910770243.6A CN201910770243A CN110492887A CN 110492887 A CN110492887 A CN 110492887A CN 201910770243 A CN201910770243 A CN 201910770243A CN 110492887 A CN110492887 A CN 110492887A
- Authority
- CN
- China
- Prior art keywords
- chopping switch
- chopper circuit
- circuit
- clock signal
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000872 buffer Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000006243 chemical reaction Methods 0.000 claims abstract description 7
- 230000008569 process Effects 0.000 claims abstract description 7
- 230000005611 electricity Effects 0.000 claims description 6
- 230000003139 buffering effect Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 4
- 238000005070 sampling Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 239000000686 essence Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
A kind of analog-digital converter circuit, it further include being sequentially connected with input chopper circuit, input buffer, the first output chopper circuit, analog-to-digital conversion process circuit and the second output chopper circuit, wherein, it is multiplexed the input chopper circuit and the first output chopper circuit, the second output chopper circuit is mutually matched constitutes buffer chopper circuit and system chopper circuit respectively.It is improved on the basis of conventional chopper buffering type analog-to-digital converter, pass through the multiplexing of system chopping switch circuit and module chopping switch circuit, reduce one of chopping switch circuit, reduce the tandem tap number on input signal channel, avoids signal path tandem tap from limiting whole performance of analog-to-digital convertor, improve the linearity, the area of copped wave analog-digital converter can be reduced simultaneously, also power consumption is reduced, and circuit realizes that simply, implementation method is easy.
Description
Technical field
The application belongs to electronic circuit technology field more particularly to a kind of analog-digital converter circuit.
Background technique
In the design of analog-digital converter (Analog-to-Digital Converter, ADC), due in analog-digital converter
The sampling switch in portion has limited input impedance, and input impedance changes over time.Another aspect analog-digital converter internal sample
For circuit to the Charge injection effect of signal source, this will lead to the linearity decline of analog-digital converter, while also limiting modulus and turning
The external interface of parallel operation must be Low ESR input.In order to solve this problem, it needs to increase by one in analog-digital converter front end
Input buffer to isolation signals source and sampling switch circuit, while can also provide high input impedance.It is such with buffer
Analog-digital converter is known as buffering type analog-to-digital converter.
Since the circuit noise and DC maladjustment of input buffer will limit performance of analog-to-digital convertor, input buffer
Circuit needs to increase buffer stage chopper circuit, reduces flicker noise and DC maladjustment whereby.In addition, working as analog-digital converter application
In ultralow frequency and class direct current scene, the DC maladjustment and device flicker noise of analog-digital converter circuit will affect analog-digital converter
Performance.Therefore it needs to increase system-level chopper circuit in the front end of analog-digital converter, by periodically making input signal
Polarity reversion, to reduce the DC maladjustment and flicker noise of entire analog-digital converter.
However, system chopper circuit and buffer chopper circuit are directly superimposed upon input letter from the point of view of analog circuit realization
Number front end, is equivalent to two-stage switch series connection on input signal channel, switch subject clock signal control, and clock can be brought to burst logical effect
It answers, the non-linear performance that can all influence entire circuit of the limited conduction impedance of Simultaneous Switching and switch conduction resistance.For big
For most high-precisions, high-speed AD converter, the input switch in signal path can all become limitation performance of analog-to-digital convertor
Bottleneck.
Summary of the invention
The application's is designed to provide a kind of analog-digital converter circuit, it is intended to solve at present with the analog-digital converter of copped wave
Front end two-stage chopper circuit, which forms two-stage series connection switch, can bring the routed logical effect of clock, and also bringing along influences the linearity and power consumption
High problem.
The embodiment of the present application first aspect provides a kind of analog-digital converter circuit, further includes being sequentially connected with input copped wave electricity
Road, input buffer, the first output chopper circuit, analog-to-digital conversion process circuit and the second output chopper circuit, wherein described
Chopper circuit work is inputted in the case where being superimposed the clock signal of first frequency and second frequency, the first output chopper circuit work
Make under the clock signal of second frequency, the second output chopper circuit work is described under the clock signal of first frequency
Second frequency is twice or more of first frequency.
The input chopper circuit includes the first chopping switch, the second chopping switch, third in one of the embodiments,
Chopping switch and the 4th chopping switch；
The first end of first chopping switch and the first end of second chopping switch are connect altogether as analog-digital converter
The first end of the first input end of circuit, the first end of the third chopping switch and the 4th chopping switch is connect altogether as mould
The second end of second input terminal of number converter circuit, the second end of first chopping switch and the third chopping switch is total
Connect the first output end as analog-digital converter circuit, the second end of second chopping switch and the 4th chopping switch
Second end connects the second output terminal as analog-digital converter circuit altogether；
First chopping switch, the 4th chopping switch work in the first clock signal for being superimposed second frequency and
Under the second clock signal of first frequency, second chopping switch, third chopping switch work are being superimposed the second frequency
Under the third clock signal of rate and the 4th clock signal of first frequency, the first clock signal and third clock signal are that interlocking is closed
System, second clock signal and the 4th clock signal are interlocked relationship.
In one of the embodiments, it is described first output chopper circuit include the 5th chopping switch, the 6th chopping switch,
7th chopping switch and the 8th chopping switch；
The first end of 5th chopping switch and the first end of the 6th chopping switch connect altogether to be cut as the first output
The first input end of wave circuit, the first end of the 7th chopping switch and the first end of the 8th chopping switch connect conduct altogether
Second input terminal of the first output chopper circuit, the second of the second end of the 5th chopping switch and the 7th chopping switch
End connects the first output end as the first output chopper circuit, the second end and the 8th copped wave of the 6th chopping switch altogether
The second end of switch connects the second output terminal as the first output chopper circuit altogether；
5th chopping switch, the 8th chopping switch work are described under the second clock signal of second frequency
6th chopping switch, the 7th chopping switch work are under the 4th clock signal of second frequency.
The second output chopper circuit is digital chopper circuit in one of the embodiments,.
The embodiment of the present application second aspect provides another analog-digital converter circuit, including is sequentially connected with input copped wave electricity
Road, input buffer, the first output chopper circuit, analog-to-digital conversion process circuit and the second output chopper circuit, wherein multiplexing
The input chopper circuit and the first output chopper circuit, the second output chopper circuit are mutually matched composition respectively and delay
Rush device chopper circuit and system chopper circuit.
In one of the embodiments, the input chopper circuit work be superimposed first frequency and second frequency when
Under clock signal, the first output chopper circuit work is under the clock signal of second frequency, the second output chopper circuit
Under the clock signal of first frequency, the second frequency is twice or more of first frequency for work.
The input chopper circuit includes the first chopping switch, the second chopping switch, third in one of the embodiments,
Chopping switch and the 4th chopping switch；
The first end of first chopping switch and the first end of second chopping switch are connect altogether as analog-digital converter
The first end of the first input end of circuit, the first end of the third chopping switch and the 4th chopping switch is connect altogether as mould
The second end of second input terminal of number converter circuit, the second end of first chopping switch and the third chopping switch is total
Connect the first output end as input chopper circuit, the of the second end of second chopping switch and the 4th chopping switch
Two ends connect the second output terminal as input chopper circuit altogether；
First chopping switch, the 4th chopping switch work in the first clock signal for being superimposed second frequency and
Under the second clock signal of first frequency, second chopping switch, third chopping switch work are being superimposed the second frequency
Under the third clock signal of rate and the 4th clock signal of first frequency, the first clock signal and third clock signal are that interlocking is closed
System, second clock signal and the 4th clock signal are interlocked relationship.
In one of the embodiments, it is described first output chopper circuit include the 5th chopping switch, the 6th chopping switch,
7th chopping switch and the 8th chopping switch；
The first end of 5th chopping switch and the first end of the 6th chopping switch connect altogether to be cut as the first output
The first input end of wave circuit, the first end of the 7th chopping switch and the first end of the 8th chopping switch connect conduct altogether
Second input terminal of the first output chopper circuit, the second of the second end of the 5th chopping switch and the 7th chopping switch
End connects the first output end as the first output chopper circuit, the second end and the 8th copped wave of the 6th chopping switch altogether
The second end of switch connects the second output terminal as the first output chopper circuit altogether；
5th chopping switch, the 8th chopping switch work are described under the second clock signal of second frequency
6th chopping switch, the 7th chopping switch work are under the 4th clock signal of second frequency.
The second output chopper circuit is digital chopper circuit in one of the embodiments,.
Above-mentioned analog-digital converter circuit improves on the basis of conventional chopper buffers type analog-to-digital converter, passes through system
The multiplexing of chopping switch circuit and module chopping switch circuit reduces one of chopping switch circuit, to reduce input signal
Tandem tap number on channel avoids signal path tandem tap from limiting whole performance of analog-to-digital convertor, improves the linearity, together
When can reduce the area of copped wave analog-digital converter, also reduce power consumption, and circuit is realized simple, implementation method is easy.
Detailed description of the invention
It in order to more clearly explain the technical solutions in the embodiments of the present application, below will be to embodiment or description of the prior art
Needed in attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only some of the application
Embodiment for those of ordinary skill in the art without any creative labor, can also be according to these
Attached drawing obtains other attached drawings.
Fig. 1 is the circuit block diagram of analog-digital converter circuit provided by the embodiments of the present application；
Fig. 2 is the control clock timing diagram for the analog-digital converter circuit that embodiment provides；
Fig. 3 is the exemplary circuit figure that chopper circuit is inputted in analog-digital converter shown in fig. 1；
Fig. 4 is the exemplary circuit figure of the first output chopper circuit in analog-digital converter shown in fig. 1.
Specific embodiment
It is with reference to the accompanying drawings and embodiments, right in order to which the objects, technical solutions and advantages of the application are more clearly understood
The application is further elaborated.It should be appreciated that specific embodiment described herein is only used to explain the application, and
It is not used in restriction the application.
Referring to Fig. 1, analog-digital converter circuit provided by the embodiments of the present application includes being sequentially connected with input chopper circuit
110, input buffer 120, first exports chopper circuit 130, analog-to-digital conversion process circuit 140 and the second output chopper circuit
150, wherein multiplexing input chopper circuit 110 and the first output output chopper circuit 150 of chopper circuit 130, second are mutual respectively
Matching constitutes buffer chopper circuit and system chopper circuit.It is equivalent to, inputs chopper circuit 110 and the first output chopper circuit
130 constitute buffer chopper circuit, and input chopper circuit 110 also constitutes system chopper circuit with the second output chopper circuit 150,
It is switched and is connected come the two-stage of alternative system chopper circuit and buffer chopper circuit using level-one switch, avoid two-stage switch series connection
Bring clock, which is burst, leads to effect, and non-linear the influenced circuit performance of the limited conduction impedance of switch, resistance.
Fig. 1 and Fig. 2 are please referred to, as shown in Figure 1, input signal only passes through level-one chopper circuit and enters input buffer 120
Input terminal.The buffer chopper circuit of analog-digital converter front end and system copped wave electricity positioned at entire analog-digital converter head and the tail both ends
Road is respectively to work independently, the different timing control of each freedom.Assuming that buffer chopper circuit is with fch1Frequency periodically turn over
Turn, and analog-to-digital converter chopper circuit is with fch_sysFrequency carries out system punctuated turning over, in general circuit-level copped wave frequency
Rate fch1Not higher than analog-digital converter sampling rate fs/ 2, i.e. fch1≤fs/ 2, it in this way can be in the feelings for guaranteeing analog-digital converter function
Circuit direct imbalance and flicker noise are effectively reduced under condition.And system-level chopper circuit toggle frequency fch_sysFrequency is just lower,
Generally can software operated, therefore fch_sys< < fch1。
In work process, second frequency f can be setch1For first frequency fch_sysTwice or more, with fch_sys=fch1/
For 8.The input work of chopper circuit 110 is being superimposed first frequency fch1With second frequency fch_sysClock signalUnder, the first output work of chopper circuit 130 is in second frequency fch1Clock signal
Under, the second output work of chopper circuit 150 is in first frequency fch_sysClock signalUnder.
In Φch_sysBefore=1 terminates (t1 moment in Fig. 2), the input terminal of input buffer 120 is A1 (-), B1 (+),
A1, B1 two o'clock signal polarity and input signal are overturn.
In Φch_sysBefore=0 terminates (t2 moment in Fig. 2), the input terminal of input buffer 120 is A1 (+), B1 (-),
A1, B1 two o'clock signal polarity are consistent with input signal.
Also, it is understood that clock signalAnd clock signalRespectively it is
System chopper circuit and buffer chopper circuit be not multiplexed before work clock.From above-mentioned realization timing it can also be seen that this
The function that timing is realized be not multiplexed with system chopper circuit with buffer chopper circuit before timing function as, i.e. circuit-level
Copped wave carries out the overturning in 8 periods, and system-level chopper circuit carries out once inside out switching.This switch multiplexing technology, which is equivalent to, to be saved
The chopping switch circuit of original buffer input allows system-level chopping switch to realize circuit-level by reasonable timing
The function of chopping switch, or vice versa.
Please refer to Fig. 2 and Fig. 3, input chopper circuit 110 includes the first chopping switch 112, the second chopping switch 114, the
Three chopping switch 116 and the 4th chopping switch 118.
The first end of first chopping switch 112 and the first end of the second chopping switch 114 are connect altogether as analog-digital converter electricity
The first end of the first input end on road, the first end of third chopping switch 116 and the 4th chopping switch 118 connects altogether to be turned as modulus
Second input terminal of converter circuit, the second end of the first chopping switch 112 and the second end of third chopping switch 116 connect conduct altogether
Input the first output end of chopper circuit 110, the second end of the second chopping switch 114 and the second end of the 4th chopping switch 118
The second output terminal as input chopper circuit 110 is connect altogether；
First chopping switch 112, the work of the 4th chopping switch 118 are being superimposed second frequency fch1The first clock signal
Φch1With first frequency fch_sysSecond clock signal Phich_sysUnder, i.e. clock signal Phich1_sys；Second chopping switch 114,
The work of third chopping switch 116 is being superimposed second frequency fch1Third clock signalWith first frequency fch_sys
Four clock signalsUnder, i.e. clock signalFirst clock signal Φch1With third clock signalFor
Interlocked relationship, second clock signal Phich_sysWith the 4th clock signalFor interlocked relationship.
Fig. 2 and Fig. 4 are please referred to, the first output chopper circuit 130 includes the 5th chopping switch 132, the 6th chopping switch
134, the 7th chopping switch 136 and the 8th chopping switch 138；
The first end of 5th chopping switch 132 and the first end of the 6th chopping switch 134 are connect altogether as the first output copped wave
The first input end of circuit 130, the first end of the 7th chopping switch 136 and the first end of the 8th chopping switch 138 connect conduct altogether
Second input terminal of the first output chopper circuit 130, the of the second end of the 5th chopping switch 132 and the 7th chopping switch 136
Two ends connect the first output end as the first output chopper circuit 130, the second end and the 8th copped wave of the 6th chopping switch 134 altogether
The second end of switch 138 connects the second output terminal as the first output chopper circuit 130 altogether；
5th chopping switch 132, the work of the 8th chopping switch 138 are in second frequency fch1Second clock signal Phich1Under,
6th chopping switch 134, the work of the 7th chopping switch 136 are in second frequency fch1The 4th clock signalUnder.
Second output chopper circuit 150 is digital chopper circuit, is generally made of logic circuits such as phase inverter, NAND gates.
For very low frequencies and collimation stream application scene, the system that chopper circuit 110 and the second output chopper circuit 150 are constituted is inputted
Chopper circuit can generally be operated by software, be only used to input signal polarity on the contrary, so as to reducing entire analog-digital converter system
The DC maladjustment united on signal transmission path.Digital circuit can be used to realize in the timing of whole realization Fig. 2, can also pass through simulation
Circuit logic door realizes that implementation method is simple, and this will not be detailed here.
Above-mentioned analog-digital converter is multiplexed composition system chopping switch circuit and module chopping switch by single-stage input switch
Circuit reduces tandem tap number, avoids the non-ideal characteristic limitation overall circuit performance of switch, can reduce copped wave analog-to-digital conversion
The area of device, while power consumption is also reduced, and circuit realizes that simply, implementation method is easy.
The foregoing is merely the preferred embodiments of the application, not to limit the application, all essences in the application
Made any modifications, equivalent replacements, and improvements etc., should be included within the scope of protection of this application within mind and principle.
Claims (9)
1. a kind of analog-digital converter circuit, which is characterized in that including being sequentially connected with input chopper circuit, input buffer, first
Export chopper circuit, analog-to-digital conversion process circuit and the second output chopper circuit, wherein the input chopper circuit work exists
It has been superimposed under the clock signal of first frequency and second frequency, clock of the first output chopper circuit work in second frequency
Under signal, under the clock signal of first frequency, the second frequency is first frequency for the second output chopper circuit work
Twice or more.
2. analog-digital converter circuit as described in claim 1, which is characterized in that the input chopper circuit includes the first copped wave
Switch, the second chopping switch, third chopping switch and the 4th chopping switch；
The first end of first chopping switch and the first end of second chopping switch are connect altogether as analog-digital converter circuit
First input end, the first end of the first end of the third chopping switch and the 4th chopping switch connects altogether to be turned as modulus
The second end of second input terminal of parallel operation, the second end of first chopping switch and the third chopping switch is connect altogether as mould
The second end of first output end of number converter circuit, the second end of second chopping switch and the 4th chopping switch is total
Connect the second output terminal as analog-digital converter circuit；
First chopping switch, the 4th chopping switch work are in the first clock signal and first for being superimposed second frequency
Under the second clock signal of frequency, second chopping switch, third chopping switch work are being superimposed second frequency
Under third clock signal and the 4th clock signal of first frequency, the first clock signal and third clock signal are interlocked relationship,
Second clock signal and the 4th clock signal are interlocked relationship.
3. analog-digital converter circuit as claimed in claim 2, which is characterized in that the first output chopper circuit includes the 5th
Chopping switch, the 6th chopping switch, the 7th chopping switch and the 8th chopping switch；
The first end of 5th chopping switch and the first end of the 6th chopping switch are connect altogether as the first output copped wave electricity
The first input end on road, the first end of the 7th chopping switch and the first end of the 8th chopping switch are connect altogether as first
The second input terminal of chopper circuit is exported, the second end of the 5th chopping switch and the second end of the 7th chopping switch are total
Connect the first output end as the first output chopper circuit, the second end of the 6th chopping switch and the 8th chopping switch
Second end connect altogether as first output chopper circuit second output terminal；
5th chopping switch, the 8th chopping switch work are under the second clock signal of second frequency, and the described 6th
Chopping switch, the 7th chopping switch work are under the 4th clock signal of second frequency.
4. analog-digital converter circuit as claimed in claim 3, which is characterized in that the second output chopper circuit is cut for number
Wave circuit.
5. a kind of analog-digital converter circuit, which is characterized in that including being sequentially connected with input chopper circuit, input buffer, first
Export chopper circuit, analog-to-digital conversion process circuit and the second output chopper circuit, wherein the multiplexing input chopper circuit and
The first output chopper circuit, the second output chopper circuit are mutually matched constitute buffer chopper circuit and system respectively
Chopper circuit.
6. analog-digital converter circuit as claimed in claim 5, which is characterized in that the input chopper circuit work is being superimposed
Under the clock signal of first frequency and second frequency, clock signal of the first output chopper circuit work in second frequency
Under, under the clock signal of first frequency, the second frequency is the two of first frequency for the second output chopper circuit work
Times or more.
7. analog-digital converter circuit as claimed in claim 5, which is characterized in that the input chopper circuit includes the first copped wave
Switch, the second chopping switch, third chopping switch and the 4th chopping switch；
The first end of first chopping switch and the first end of second chopping switch are connect altogether as analog-digital converter circuit
First input end, the first end of the first end of the third chopping switch and the 4th chopping switch connects altogether to be turned as modulus
The second end of second input terminal of converter circuit, the second end of first chopping switch and the third chopping switch connects work altogether
For the first output end for inputting chopper circuit, the second end of the second end of second chopping switch and the 4th chopping switch
The second output terminal as input chopper circuit is connect altogether；
First chopping switch, the 4th chopping switch work are in the first clock signal and first for being superimposed second frequency
Under the second clock signal of frequency, second chopping switch, third chopping switch work are being superimposed second frequency
Under third clock signal and the 4th clock signal of first frequency, the first clock signal and third clock signal are interlocked relationship,
Second clock signal and the 4th clock signal are interlocked relationship.
8. analog-digital converter circuit as claimed in claim 7, which is characterized in that the first output chopper circuit includes the 5th
Chopping switch, the 6th chopping switch, the 7th chopping switch and the 8th chopping switch；
The first end of 5th chopping switch and the first end of the 6th chopping switch are connect altogether as the first output copped wave electricity
The first input end on road, the first end of the 7th chopping switch and the first end of the 8th chopping switch are connect altogether as first
The second input terminal of chopper circuit is exported, the second end of the 5th chopping switch and the second end of the 7th chopping switch are total
Connect the first output end as the first output chopper circuit, the second end of the 6th chopping switch and the 8th chopping switch
Second end connect altogether as first output chopper circuit second output terminal；
5th chopping switch, the 8th chopping switch work are under the second clock signal of second frequency, and the described 6th
Chopping switch, the 7th chopping switch work are under the 4th clock signal of second frequency.
9. analog-digital converter circuit as claimed in claim 5, which is characterized in that the second output chopper circuit is cut for number
Wave circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910770243.6A CN110492887A (en) | 2019-08-20 | 2019-08-20 | Analog-digital converter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910770243.6A CN110492887A (en) | 2019-08-20 | 2019-08-20 | Analog-digital converter circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110492887A true CN110492887A (en) | 2019-11-22 |
Family
ID=68552323
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910770243.6A Pending CN110492887A (en) | 2019-08-20 | 2019-08-20 | Analog-digital converter circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110492887A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090066318A1 (en) * | 2006-03-15 | 2009-03-12 | Koninklijke Philips Electronics N.V. | Sensor device with alternating excitation fields |
| CN103391100A (en) * | 2013-07-03 | 2013-11-13 | 江苏博纳雨田通信电子有限公司 | Novel high pass chopper Delta-Sigma analog-digital converter |
| CN105915219A (en) * | 2016-04-08 | 2016-08-31 | 中国科学院微电子研究所 | Analog-digital conversion circuit |
| CN106209110A (en) * | 2016-07-02 | 2016-12-07 | 成都育芽科技有限公司 | A kind of delta sigma analog-digital converter |
| KR20170015609A (en) * | 2015-07-29 | 2017-02-09 | 전자부품연구원 | Multi-stage Chopping Method for a High Gain and Area Compact and ROIC using the same |
| CN109586718A (en) * | 2018-11-06 | 2019-04-05 | 同方威视技术股份有限公司 | Reduce circuit, noise-reduction method and the equipment of A/D converter noise |
| CN210431392U (en) * | 2019-08-20 | 2020-04-28 | 深圳市锐能微科技有限公司 | Analog-to-digital converter circuit |
-
2019
- 2019-08-20 CN CN201910770243.6A patent/CN110492887A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090066318A1 (en) * | 2006-03-15 | 2009-03-12 | Koninklijke Philips Electronics N.V. | Sensor device with alternating excitation fields |
| CN103391100A (en) * | 2013-07-03 | 2013-11-13 | 江苏博纳雨田通信电子有限公司 | Novel high pass chopper Delta-Sigma analog-digital converter |
| KR20170015609A (en) * | 2015-07-29 | 2017-02-09 | 전자부품연구원 | Multi-stage Chopping Method for a High Gain and Area Compact and ROIC using the same |
| CN105915219A (en) * | 2016-04-08 | 2016-08-31 | 中国科学院微电子研究所 | Analog-digital conversion circuit |
| CN106209110A (en) * | 2016-07-02 | 2016-12-07 | 成都育芽科技有限公司 | A kind of delta sigma analog-digital converter |
| CN109586718A (en) * | 2018-11-06 | 2019-04-05 | 同方威视技术股份有限公司 | Reduce circuit, noise-reduction method and the equipment of A/D converter noise |
| CN210431392U (en) * | 2019-08-20 | 2020-04-28 | 深圳市锐能微科技有限公司 | Analog-to-digital converter circuit |
Non-Patent Citations (1)
| Title |
|---|
| 孙建辉等: "高精度微弱脑电检测数模混合控制芯片系统", 《仪器仪表学报》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3699764B2 (en) | Driver circuit device and interface | |
| CN104009736B (en) | Low-power consumption master-slave flip-flop | |
| EP3248290A1 (en) | Serializing transmitter | |
| CN107835021A (en) | A kind of asynchronous sequential control circuit of Variable delay and control method | |
| US5045714A (en) | Multiplexer with improved channel select circuitry | |
| CN109672444A (en) | A kind of ultrahigh speed digital analog converter that multichannel clock interweaves | |
| CN101800531B (en) | Switching device and current mode digital-to-analog converter with same | |
| US6762625B1 (en) | Programmable differential current mode line driver with multiple classes of circuit operation | |
| WO2009133658A1 (en) | Multiple signal switching circuit, current switching cell circuit, latch circuit, current addition type dac, semiconductor integrated circuit, video device, and communication device | |
| JP6880846B2 (en) | Multiplexer | |
| CN110492887A (en) | Analog-digital converter circuit | |
| US8749268B2 (en) | High-speed driver circuit | |
| CN110932705A (en) | Power rail switching circuit | |
| CN104660222B (en) | The d type flip flop and five frequency dividing circuits of a kind of current switching formula | |
| WO2004104820A3 (en) | A sum bit generation circuit | |
| US7098829B2 (en) | Digital to analog conversion | |
| CN109687846A (en) | A kind of Low phase noise broadband active single-chip integration broadband comb spectrum generator | |
| CN210431392U (en) | Analog-to-digital converter circuit | |
| CN1777032B (en) | Four-channel mismatch-free clock control circuit | |
| US8830101B1 (en) | Single phase clock D/A converter with built-in data combiner | |
| CN106788432A (en) | D/A converting circuit | |
| US8547134B1 (en) | Architecture for high speed serial transmitter | |
| CN107070447B (en) | Multi-input high-speed CMOS buffer circuit | |
| CN101465642B (en) | Change-over circuit from CMOS to MCML | |
| CN211184172U (en) | Digital array microphone clock circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |