CN115833821A - High-speed multiplexing circuit applied to Serdes system sending end - Google Patents

High-speed multiplexing circuit applied to Serdes system sending end Download PDF

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Publication number
CN115833821A
CN115833821A CN202211369806.9A CN202211369806A CN115833821A CN 115833821 A CN115833821 A CN 115833821A CN 202211369806 A CN202211369806 A CN 202211369806A CN 115833821 A CN115833821 A CN 115833821A
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China
Prior art keywords
multiplexing circuit
stage
circuit
speed
multiplexing
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CN202211369806.9A
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Chinese (zh)
Inventor
张春茗
徐阳臻
王浩
杜慧敏
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Xian University of Posts and Telecommunications
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Xian University of Posts and Telecommunications
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Priority to CN202211369806.9A priority Critical patent/CN115833821A/en
Publication of CN115833821A publication Critical patent/CN115833821A/en
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention provides a high-speed multiplexing circuit applied to a Serdes system transmitting end, which is used for solving the technical problem that the existing multiplexer is simple in structure, limited in speed or large in structure when power consumption is low. The invention comprises M groups of parallel circuit multiplexing units, which also comprise K-level multiplexing circuits; the first stage of multiplexing circuit comprises 2 K‑1 2 K‑i A 2; first stage of multiplexing circuits 2 K‑1 2 K The output end of the parallel data is connected with the next stage 2 K‑2 A 2; by analogy, the input end of the multiplexer 2 of the K-th stage is connected with the output end of the multiplexer 2 of the K-1 stage, and the output end of the multiplexer 2 of the K-th stage is used for outputting high-speed data; m groups of circuit multiplexing units are used for inputting 2 of external K And converting the parallel data of the XM paths into high-speed data of the M paths for output.

Description

High-speed multiplexing circuit applied to Serdes system sending end
Technical Field
The invention relates to a multiplexer, in particular to a high-speed multiplexing circuit applied to a transmitting end of a Serdes system.
Background
The multiplexer is one of the important components in SerDes systems, and functions to multiplex multiple low-speed signals into one high-speed signal, and the performance of the multiplexer is a key factor for determining the performance characteristics of the whole data transmission system.
There are three common architectures for multiplexers, namely serial, parallel, tree architectures. The serial structure has the characteristics of simple structure and easy realization of expected functions; the disadvantage is that its operating speed is easily limited. The multiplexer with the parallel structure is suitable for the case with a lower order, and is commonly seen in a 2. For the N:1 multiplexer, the number of the N:1 multiplexers cannot be too large due to the parallel connection mode, and the load capacitance of each input end is large due to the number of more input signals, so that the working speed of the circuit is influenced, and the application of the N:1 multiplexer with the parallel structure in a low-power-consumption high-speed analog circuit and a digital-analog mixed circuit is limited. The circuit with the tree-shaped structure, which works at the highest speed, is only the multiplexer of the circuit at the last stage, and other circuits all work at lower speeds, so that the power consumption of the circuit multiplexer with the tree-shaped structure is minimum, but the scale of the circuit multiplexer corresponding to the power consumption is maximum.
Disclosure of Invention
The invention aims to solve the technical problems of simple structure, limited speed or larger structure when the power consumption is smaller in the conventional multiplexer, and provides a high-speed multiplexing circuit applied to a Serdes system transmitting end, which can save the power consumption and the area of a circuit and meet the requirement of higher data transmission speed while realizing the expected circuit multiplexing function.
In order to achieve the above object, the technical solution of the present invention is as follows:
a high-speed multiplexing circuit applied to a transmitting end of a Serdes system is characterized by comprising M groups of parallel circuit multiplexing units;
the circuit multiplexing unit comprises K-level multiplexing circuits which are sequentially connected, and K is an integer greater than or equal to 4;
the first stage of the multiplexing circuit includes 2 K-1 2 K-i A 2,i =1, \8230;, K; the K-th stage multiplexing circuit comprises 1 2;
first stage of multiplexing circuits 2 K-1 The input end of the 2 K The output ends of the parallel data paths are respectively connected with 2 of the next-stage multiplexing circuit K-2 An input of a 2; by analogy, the input end of the 2-1 multiplexer of the K-th level multiplexing circuit is respectively connected with the output ends of the 2-1 multiplexers of the K-1 level multiplexing circuit, and the output end of the 2-1 multiplexer of the K-th level multiplexing circuit is used for outputting high-speed serial data;
m groups of circuit multiplexing units are used for inputting 2 of external K And converting the xM paths of parallel data into M paths of high-speed serial data for output.
Further, a 2;
the type-a 2;
the clock control port of the first flip-flop DFF1, the clock control port of the second flip-flop DFF2, the clock control port of the first LATCH LATCH1 and the clock control port of the first selector SEL1 are all used for connecting clock signals;
the data input ends of the first trigger DFF1 and the second trigger DFF2 are used for connecting 2 paths of externally input data; the output end of the first flip-flop DFF1 is connected with the input end of the first LATCH LATCH1, the output end of the first LATCH LATCH1 is connected with one input end of the first selector SEL1, and the output end of the second flip-flop DFF2 is connected with the other input end of the first selector SEL1; the output end of the first selector SEL1 is connected with the input end of the next-stage multiplexing circuit.
Further, the frequencies of the first flip-flop DFF1, the second flip-flop DFF2, the first LATCH1, and the first selector SEL1 are all the same as the frequency of the externally input parallel data signal.
Further, the first flip-flop DFF1, the second flip-flop DFF2, and the first LATCH1 are all CMOS structures for saving power consumption and circuit area.
Furthermore, the multiplexers from the second-level multiplexing circuit to the Kth-level multiplexing circuit in the K-level multiplexing circuit from 2;
the B-type 2;
the clock control port of the third flip-flop DFF3, the clock control port of the second LATCH LATCH2 and the clock control port of the second selector SEL2 are all used for connecting clock signals;
the data input ends of the third flip-flop DFF3 and the second LATCH2 are respectively used for connecting two output ends of the upper-stage multiplexing circuit and inputting 2-path data; the output end of the third flip-flop DFF3 is connected to one input end of the second selector SEL2, and the output end of the second LATCH2 is connected to the other input end of the second selector SEL2; the output end of a second selector SEL2 from the 2 nd stage to the K-1 th stage of the multiplexing circuit is connected with the input end of the next stage of the multiplexing circuit, and the output end of the second selector SEL2 of the K stage is used for outputting high-speed data.
Further, the frequency of the third flip-flop DFF3, the second LATCH2, and the second selector SEL2 is the same as the output signal frequency of the multiplexer of the previous stage 2.
Furthermore, a third trigger DFF3 and a second LATCH2 of a second-stage multiplexing circuit in the K-stage multiplexing circuit are both of CMOS structures, so as to save circuit area and power consumption;
the third flip-flop DFF3 and the second LATCH LATCH2 from the third-stage multiplexing circuit to the K-stage multiplexing circuit in the K-stage multiplexing circuit are both C 2 And the MOS structure is used for meeting the requirement of higher speed of a circuit.
Further, said M =4; the circuit multiplexing unit is a 16;
the K =4; the first-stage multiplexing circuit is a 16;
the 16.
Further, the type-A2.
The invention has the beneficial effects that:
1. the invention provides a high-speed multiplexing circuit applied to a Serdes system transmitting end, which belongs to a high-order and high-speed multiplexer, wherein a tree structure is adopted on the whole, M groups of parallel circuit multiplexing units are arranged, and the circuit multiplexing units are provided with K-level multiplexing circuits, so that the multiplexing circuit meets the requirement of higher data transmission speed while realizing the expected circuit multiplexing function, and in addition, the K-level multiplexing circuits are designed by adopting a plurality of parallel 2.
2. The high-speed multiplexing circuit applied to the Serdes system transmitting end can also correctly output high-speed data according to requirements under the condition of process, power supply voltage and temperature change, and meets the requirement of higher data transmission speed.
3. The invention provides a high-speed multiplexing circuit applied to a sending end of a Serdes system, wherein a multiplexer 2 2 The MOS structure and the CMOS structure are simultaneously applied to different multiplexing circuits, high-speed transmission is ensured, the circuit area and power consumption are further saved, and the design complexity is reduced.
4. The invention provides a high-speed multiplexing circuit applied to a sending end of a Serdes system, which takes a 64-way 4 high-speed multiplexing circuit as an example, and is provided with 4 parallel 16.
Drawings
Fig. 1 is a schematic structural diagram of an embodiment of a high-speed multiplexing circuit applied to a transmitting end of a Serdes system according to the present invention;
FIG. 2 is a circuit diagram of a type 2 circuit multiplexing structure in the embodiment of the present invention;
FIG. 3 is a circuit diagram of a type B2 circuit multiplexing structure according to an embodiment of the present invention;
FIG. 4 is a timing diagram of an input clock signal according to an embodiment of the present invention;
fig. 5 is a comparison graph of an output signal curve of the multiplexing circuit 64 according to the embodiment of the present invention and an output simulation curve of the multiplexing circuit 64 according to the embodiment of the present invention modeled by Verilog-a language.
Detailed Description
To further clarify the advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
As shown in fig. 1, a high-speed multiplexing circuit applied to a sending end of a Serdes system is used to convert 64 low-speed parallel data into 4 high-speed data, and includes 4 sets of parallel circuit multiplexing units, where the circuit multiplexing unit in this embodiment is a 16-way multiplexer. The 16. Wherein, 16. Preferably, the 8 sets 2 of multiplexers in the 16. The circuit multiplexing structure of the A type 2Specifically, the first flip-flop DFF1, the second flip-flop DFF2, the first LATCH1, and the first selector SEL1 are included. The operating frequencies of the first flip-flop DFF1, the second flip-flop DFF2, the first LATCH1, and the first selector SEL1 are the same as the frequency of the parallel data signal inputted from the outside, and therefore, the clock control port of the first flip-flop DFF1, the clock control port of the second flip-flop DFF2, the clock control port of the first LATCH1, and the clock control port of the first selector SEL1 are all connected to the same clock signal, which is CLK625M in the embodiment; the delay time of the first selector SEL1 is 1/4 of the current clock period. Preferably, the first flip-flop DFF1, the second flip-flop DFF2, and the first LATCH1 are all of a CMOS structure. The B-type 2; the delay time of the second selector SEL2 is 1/4 of the current clock period. In this embodiment, the clock signal of the 8. Preferably, the third flip-flop DFF3 and the second LATCH2 in the 8; 4 2 The MOS structure meets the requirement of higher speed of the circuit; c 2 The MOS structure and the CMOS structure are applied to different multiplexing circuits, high-speed transmission is guaranteed, meanwhile, the circuit area and power consumption are further saved, and the design complexity is reduced.
Taking one of 4 sets of parallel circuit multiplexing units as an example, the connection relationship is as follows: the data input ends of a first flip-flop DFF1 and a second flip-flop DFF2 of 8 2 multiplexers in the 8 multiplexing circuits are used for connecting 16 externally input data, and each 2; the output of the first flip-flop DFF1 is connected to the input of the first LATCH1, the output of the first LATCH1 is connected to one input of the first selector SEL1, the output of the second flip-flop DFF2 is connected to the other input of the first selector SEL1, the outputs of the first selector SEL1 of the 2: the output terminal of the second LATCH2 is connected to the other input terminal of the second selector SEL2, the output terminals of the second selector SEL2 of 2:1 data input terminals of the respective third flip-flop DFF3 and second LATCH2 in the multiplexing circuit, 2. The 4 sets of 16. In the embodiment, the multiplexing circuit is realized by adopting a UMC28nm process.
In operation, 4 input clock signals, namely CLK625M, clk1.25gd, clk2.5gd and CLK5GD, are respectively connected into the 16. When the system inputs 64 parallel 625Mbps low-speed data, the 64 parallel 625Mbps low-speed data is transmitted through 4 parallel 16. The 16 parallel 625Mbps low-speed data is input into 8 parallel 2; inputting 8 lines of parallel data with the speed of 1.25Gbps into 4 parallel 2-way multiplexers in a 4-way multiplexing circuit, and converting to generate 4 lines of parallel data with the speed of 2.5 Gbps; 4 lines of parallel data with the speed of 2.5Gbps are input into 2 parallel 2-way multiplexers in the 2 multiplexing circuits to be converted into 2 lines of parallel data with the speed of 5 Gbps; 2 lines of parallel data with the speed of 5Gbps are input into a 2; the 4 sets of parallel 16.
The output simulation curve of the 64 multiplexing circuit of the embodiment is compared with the output simulation curve of the 64 multiplexing circuit of the embodiment after modeling through a 64 multiplexing circuit of the embodiment and a Verilog-a language, so as to verify the implementation effect of the high-speed multiplexing circuit applied to the sending end of the Serdes system in the invention.
As shown in fig. 5, curve 1 is a simulation output curve of the multiplexing circuit 64 of this embodiment 4 modeled by Verilog-a language, and curve 2 is an output signal curve of the multiplexing circuit 64 of this embodiment 4. The results show that under the conditions of different process corners (process corners: TT, FF and SS) and the temperature range of 0-85 ℃, the 64. In other embodiments of the present invention, the values of M and K may be adjusted according to specific input data, so as to complete high-speed data transmission.
The invention belongs to a high-order and high-speed multiplexer, which generally adopts a tree structure and is provided with M groups of parallel circuit multiplexing units, and the circuit multiplexing units are provided with K-level multiplexing circuits, so that data transmission speed is improved while data is correctly transmitted; meanwhile, by combining the A-type 2.
The above description is only for the purpose of illustrating the technical solutions of the present invention and not for the purpose of limiting the same, and it will be apparent to those skilled in the art that modifications may be made to the specific technical solutions described in the above embodiments or equivalent substitutions for some technical features, and these modifications or substitutions may not make the essence of the corresponding technical solutions depart from the scope of the technical solutions protected by the present invention.

Claims (9)

1. A high-speed multiplexing circuit applied to a transmitting end of a Serdes system is characterized in that:
the circuit multiplexing unit comprises M groups of parallel circuit multiplexing units;
the circuit multiplexing unit comprises K-level multiplexing circuits which are sequentially connected, and K is an integer greater than or equal to 4;
the first stage of the multiplexing circuit includes 2 K-1 2 K-i A 2; the K-th stage multiplexing circuit comprises 1 2;
first stage of multiplexing circuits 2 K-1 The input end of the 2 K The output ends of the parallel data paths are respectively connected with 2 of the next-stage multiplexing circuit K-2 An input of a 2; by analogy, the input end of the 2-1 multiplexer of the K-th level multiplexing circuit is respectively connected with the output ends of the 2-1 multiplexers of the K-1 level multiplexing circuit, and the output end of the 2-1 multiplexer of the K-th level multiplexing circuit is used for outputting high-speed data;
m groups of circuit multiplexing units are used for inputting 2 of external K And converting the parallel data of the XM paths into high-speed data of the M paths for output.
2. The high-speed multiplexing circuit applied to a transmitting end of a Serdes system according to claim 1, wherein:
a 2;
the A-type 2;
the clock control port of the first flip-flop DFF1, the clock control port of the second flip-flop DFF2, the clock control port of the first LATCH LATCH1 and the clock control port of the first selector SEL1 are all used for connecting clock signals;
the data input ends of the first trigger DFF1 and the second trigger DFF2 are used for connecting 2 paths of externally input data; the output end of the first flip-flop DFF1 is connected with the input end of the first LATCH LATCH1, the output end of the first LATCH LATCH1 is connected with one input end of the first selector SEL1, and the output end of the second flip-flop DFF2 is connected with the other input end of the first selector SEL1; the output end of the first selector SEL1 is connected with the input end of the next-stage multiplexing circuit.
3. The high-speed multiplexing circuit applied to a transmitting end of a Serdes system according to claim 2, wherein:
the frequencies of the first flip-flop DFF1, the second flip-flop DFF2, the first LATCH1, and the first selector SEL1 are all the same as the frequency of the externally input parallel data signal.
4. The high-speed multiplexing circuit applied to a transmitting end of a Serdes system according to claim 3, wherein:
the first flip-flop DFF1, the second flip-flop DFF2, and the first LATCH1 are all of a CMOS structure.
5. A high-speed multiplexing circuit applied to a transmitting end of a Serdes system according to any one of claim 4, wherein:
the multiplexers from the second-level multiplexing circuit to the K-level multiplexing circuit in the K-level multiplexing circuit from 2;
the B-type 2;
the clock control port of the third flip-flop DFF3, the clock control port of the second LATCH LATCH2 and the clock control port of the second selector SEL2 are all used for connecting clock signals;
the data input ends of the third flip-flop DFF3 and the second LATCH2 are respectively connected with two output ends of the first-stage multiplexing circuit; the output end of the third flip-flop DFF3 is connected to one input end of the second selector SEL2, and the output end of the second LATCH2 is connected to the other input end of the second selector SEL2; the output end of the second selector SEL2 is connected with the input end of the next-stage multiplexing circuit or is used for outputting high-speed data.
6. The high-speed multiplexing circuit applied to a transmitting end of a Serdes system according to claim 5, wherein:
the third flip-flop DFF3, the second LATCH2 and the second selector SEL2 all have the same frequency as the output signal of the multiplexer of the previous stage 2.
7. The high-speed multiplexing circuit applied to a transmitting end of a Serdes system according to claim 6, wherein:
the third trigger DFF3 and the second LATCH LATCH2 of the second-stage multiplexing circuit in the K-stage multiplexing circuit are both of CMOS structures;
the third flip-flop DFF3 and the second LATCH LATCH2 from the third-stage multiplexing circuit to the K-stage multiplexing circuit in the K-stage multiplexing circuit are both C 2 And a MOS structure.
8. A high-speed multiplexing circuit applied to the transmitting end of a Serdes system according to any one of claims 1 to 7, wherein:
said M =4; the circuit multiplexing unit is a 16;
the K =4; the first-stage multiplexing circuit is a 16-stage multiplexing circuit, the second-stage multiplexing circuit is an 8-stage multiplexing circuit, the third-stage multiplexing circuit is a 4-stage 2-stage multiplexing circuit, and the fourth-stage multiplexing circuit is a 2-stage multiplexing circuit;
the 16.
9. The high-speed multiplexing circuit applied to a transmitting end of a Serdes system according to claim 8, wherein:
the A-type 2.
CN202211369806.9A 2022-11-03 2022-11-03 High-speed multiplexing circuit applied to Serdes system sending end Pending CN115833821A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211369806.9A CN115833821A (en) 2022-11-03 2022-11-03 High-speed multiplexing circuit applied to Serdes system sending end

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211369806.9A CN115833821A (en) 2022-11-03 2022-11-03 High-speed multiplexing circuit applied to Serdes system sending end

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CN115833821A true CN115833821A (en) 2023-03-21

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