WO2009155874A1

WO2009155874A1 - Parallel-serial converter and its implementation method

Info

Publication number: WO2009155874A1
Application number: PCT/CN2009/072463
Authority: WO
Inventors: 张学海; 易律凡; 丁学伟
Original assignee: 中兴通讯股份有限公司
Priority date: 2008-06-26
Filing date: 2009-06-26
Publication date: 2009-12-30
Also published as: CN101615912A; CN101615912B

Abstract

A parallel-serial converter is provided, and the parallel-serial converter comprises a low speed serializer module, a transmission module and a high speed serializer module. A parallel-serial conversion method is also provided, and the parallel-serial conversion method comprises determining a work mode and an output mode. In the first work mode, a low speed parallel input data of 2⁴ⁿ bits is serialized in a low speed to obtain a high speed parallel data of 2²ⁿ bits; and then the high speed parallel data of 2²ⁿ bits is serialized in a high speed to obtain a high speed serial output data of one bit; in the second work mode, the data of the lower 2²ⁿ bits in the low speed parallel input data of 2⁴ⁿ bits is parallel-serial converted, and after the obtained data of the lower 2²ⁿ bits are buffered, the data is serialized according to the determined output mode and the set high speed serializing proportion, to obtain a high speed serial output data of one bit.

Description

Parallel string converter and implementation method thereof

TECHNICAL FIELD The present invention relates to the field of integrated circuit design, and in particular, to a parallel-to-serial converter and a method for implementing the same. BACKGROUND OF THE INVENTION For more than two decades, with the rapid development and popularization of electronic communication products for data transmission such as telephone, fax, television, etc., the pressure of the line carrying the transmission signal is increasing. The subsequent optical fiber communication has become more and more popular because of its small size, large capacity and good stability. At the same time, the development and integration of laser technology, fiber technology, microelectronic technology and computer technology has also promoted the development of optical fiber communication technology. Nowadays, fiber optic networks have become the communication backbone of the information society, and high-speed fiber-optic communication systems have entered the stage of large-scale construction worldwide. At the same time, integrated circuits play an increasingly important role in communication systems, and converters are an integrated circuit. In the current domestic and foreign literature on converter circuits, more non-mainstream processes are used, such as metal semiconductor Schottky junction field effect transistors (MESFETs), bipolar junction transistors (Si-BJT), and bipolar Transistors (HBT), etc. At the same time, with the gradual maturity of complementary metal-oxide semiconductor semiconductor (CMOS, Complementary Metal-Oxide-Semiconductor Transistor) processes, single-ended CMOS signals are highly susceptible to crosstalk, coupling, and high-speed, low-voltage environments. Noise and other factors become unstable, so in most high-speed integrated circuits, important data signals use a double-ended CMOS differential structure. Currently, some CMOS-based converters are beginning to appear, which convert multiple bits of parallel input data into one bit of serial output data. The more commonly used CMOS-based converters in the communication field have the following functions: It is possible to parallel-convert 4-bit fast parallel input data into 1-bit high-speed serial output data, or convert 16-bit low-speed parallel input data into a string. 1-bit high-speed serial output data; In addition, some converters also have a reverse-sequence output function. However, these converters are not compatible with multiple operating modes, for example, they are not compatible with 4-bit parallel-to-serial conversion and 16-bit parallel-to-serial conversion, so they are not flexible; in addition, these converters have low-speed serialization modules and high-speed serialization modules. The circuit loss is large. SUMMARY OF THE INVENTION In view of the above, it is a primary object of the present invention to provide a parallel-to-serial converter capable of being compatible with a plurality of operating modes and having low circuit losses, and an implementation method thereof. To achieve the above objective, the technical solution of the present invention is implemented as follows: A parallel-to-serial converter includes a low-speed serialization module, a transmission module, and a high-speed serialization module, wherein: a transmission module is configured to determine a current operation according to a mode selection signal Mode, and determining an output mode according to the control signal. In the first working mode, the output mode is also provided to the low-speed serialization module and the high-speed serialization module; in the second working mode, the output mode is provided to the high-speed serialization module, and is turned off. The low-speed serialization module inputs the low 2 ²ⁿ -bit data of the 2 ⁴ⁿ -bit low-speed parallel input data into the buffer module according to the set high-speed serialization ratio; the low-speed serialization module, in the first working mode, is used according to the output mode, and Low-speed serialization of 2 ⁴ⁿ -bit low-speed parallel input data according to the set low-speed serialization ratio, to obtain 2 ²ⁿ -bit high-speed parallel data; High-speed serialization module, in the first working mode, according to the output mode, and according to the setting the ratio of the speed of the string 2 ^2n-bit parallel data for serial high speed, thereby obtaining a high-speed serial output data; second working When the formula 2 ²ⁿ bits for the low speed parallel output according to the ratio of the set and the high-speed serial input data string, thereby obtaining a high-speed serial data output; wherein, n-is a natural number. Preferably, the low-speed serialization module of the above parallel-to-serial converter comprises: a low-speed synchronous circuit, a low-speed serializer and a low-speed clock generating circuit, wherein: the low-speed synchronous circuit, in the first working mode, is used for 2 ⁴ⁿ -bit low-speed parallel input data After synchronization, the 2 ⁴ⁿ -bit low-speed synchronous parallel data is obtained; the low-speed serializer is used for the output mode, and the low-speed serialization of the 2 ⁴ⁿ -bit low-speed synchronous parallel data is performed according to the set low-speed serialization ratio, and 2 ^{2n is} obtained. Bit high speed parallel data; low speed clock generating circuit for supplying clock signals to the low speed synchronizing circuit and the low speed serializer, respectively. Preferably, the transmission module of the above parallel-to-serial converter includes a reverse sequence control circuit and mode selection Road, wherein: the reverse sequence control circuit, in the first working mode, is configured to receive 2 ⁴ⁿ bits of low-speed parallel input data, and determine an output mode according to its own control signal; a mode selection circuit for determining an output mode according to its own control signal, Receiving 2 ²ⁿ -bit low-speed parallel input data, and automatically turning off the low-speed serialization module when switching from the first working mode to the second working mode, or automatically turning on the low-speed serialization module when switching from the second working mode to the first working mode. Preferably, the high-speed serialization module of the above parallel-to-serial converter comprises: a high-speed synchronization circuit, a high-speed serializer and a high-speed clock generation circuit, wherein: a high-speed synchronization circuit is configured to synchronize the received 2 ²ⁿ -bit high-speed parallel data, Obtaining 2 ²ⁿ -bit high-speed synchronous parallel data; high-speed serializer for serializing 2 ²ⁿ -bit high-speed synchronous parallel data to obtain 1-bit high-speed serial output data; high-speed clock generation circuit for respectively respectively to high-speed synchronous circuit and The high speed serializer provides a clock signal. Preferably, the above-serial converter, and the module further comprises a buffer module connected to the high-speed train, when the second operating mode for low-speed parallel data bits 2 ^2N buffers, and low back cushion 2 ²ⁿ bits of data are input to the high speed serialization module. Preferably, the above low-speed serial converter module comprises a string of at least four basic units a low speed, when the first operating mode, for receiving each 2 ^4n-bit data from a set of four high to low speed parallel input data, respectively, After serialization, 2 ²ⁿ -bit high-speed parallel data is outputted to the high-speed serialization module; wherein each low-speed basic unit shares a reset signal and a clock signal; the low-speed basic unit includes four synchronous D flip-flops and three alternative ones, wherein : a synchronous D flip-flop for synchronizing each set of low-speed parallel data received; a first two-selection selector and a second two-selection selector for receiving the synchronized two-two sets of data, After selecting, the two-bit parallel data is outputted to the third two-selector; the third-two-selector is used to select the received parallel data and output one bit of data. Preferably, the high-speed serialization module of the above parallel-to-serial converter comprises: four synchronous D flip-flops, one high-speed synchronous D flip-flop, two two-selection selectors, one two-select high-speed selector, two zero-order slow a buffer and two latch modules; wherein: a synchronous D flip-flop for synchronizing the received 2 ²ⁿ -bit high-speed parallel data divided into groups of four bits of data; Receiving two or two sets of data after synchronization, and outputting two-bit parallel data after selection; a high-speed synchronous D flip-flop for synchronously outputting modules respectively through two zero-order buffers and two latch modules , get a high-speed serial data; where, each part shares the reset signal and the clock signal. Preferably, in the two latch modules of the parallel-to-serial converter, the first latch module and the second latch module are different by half a clock cycle, wherein: the first latch module includes at least three sequential An electrically coupled latch, the second latch module includes at least two latches that are electrically connected in sequence; each latch shares a clock signal. Preferably, the low-speed clock generating circuit of the above parallel-to-serial converter comprises: three synchronous D flip-flops, eight in-phase buffers, four inverting buffers, and one high-speed synchronous D flip-flop, wherein: each synchronous D trigger For generating clock signals of various stages; the same phase buffer is used for delay buffering each stage clock signal and converting into clock signals of the same phase; the inverting buffer is used for clock signals of various stages Delay buffering, converting to a clock signal with opposite phase; High-speed synchronous D flip-flop, used to divide the input clock signal and output it to the buffer and divider. Meanwhile, the present invention also provides a parallel-to-serial conversion method, including the steps of: a, determining a working mode and an output mode; b. in the first working mode, according to the determined output mode and the set low-speed serialization ratio, 2 ⁴ⁿ -bit low-speed parallel input data for low-speed serialization, obtaining 2 ²ⁿ -bit high-speed parallel data; and then according to the determined output mode and the set high-speed serialization ratio, high-speed serialization of 2 ²ⁿ high-speed parallel data, to obtain a Bit high-speed serial output data; In the second mode of operation, according to the determined output mode and the set high-speed serialization ratio, parallel and serial conversion of low 2 ²ⁿ -bit data of 2 ⁴ⁿ -bit low-speed parallel input data will result in low After 2 ²ⁿ bit data buffering, serialization is performed according to the determined output mode and the set high-speed serialization ratio, and 1-bit high-speed serial output data is obtained. The parallel-to-serial converter of the present invention comprises a low-speed serialization module, a transmission module and a high-speed serialization module, which is compatible with the first working mode and the second working mode, and has good flexibility; and automatically switches from the first working mode to the second working mode. Turning off the low-speed serialization module helps to reduce the circuit loss. At the same time, in the first working mode, the low-speed serialization module and the high-speed serialization module sequentially perform conversion of low-speed parallel input data, and will be suitable for low-speed single-ended signals and suitable for high-speed. The combination of double-ended signals also helps to reduce circuit losses. Specifically, in the first working mode, the 2 ^{4 n} -bit low-speed parallel input data is sequentially converted into a 1-bit high-speed serial output data by a low-speed serialization module and a high-speed serialization module, and the low-speed serial data is turned off in the second working mode. The module and the 2 ²ⁿ -bit data are serially converted by the high-speed serialization module to obtain 1-bit high-speed serial output data; wherein, the low-speed serialization module input form can be a single-ended CMOS signal, and the high-speed serialization module input form can be Double-ended differential CMOS signal. At the same time, the transmission module controls the reverse output of the input data and the automatic opening and closing of the low-speed serialization module when the working mode is switched when the first working mode/second working mode is controlled. In summary, the beneficial effects of the present invention are:

(1) Flexibility and compatibility with multiple working modes, such as compatibility with the first working mode and the second working mode;

(2) The circuit loss is small. In the first working mode, the low-speed serialization module and the high-speed serialization module sequentially perform the conversion of the low-speed parallel input data, and the second operation mode automatically turns off the low-speed serialization module, and simultaneously sets the low-speed serialization module. The combination of a single-ended signal structure and a high-speed serialization module's dual-ended signal structure is beneficial in reducing circuit losses. Since the differential signal is strong against noise and anti-interference, and is still unaffected in the low-voltage circuit, the high-speed circuit in the parallel-to-serial converter of the present invention can be implemented by using a differential circuit, and the high-speed signals are differential signals. Since the circuit is converted from a low speed step by step to a high speed circuit, in order to achieve high speed and low power For the purpose of consumption, the converter has adopted a differentiated design. The difference between the two can make the low-speed synchronization circuit achieve low power consumption while the high-speed synchronization circuit achieves high speed. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are set to illustrate,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the basic principle of a parallel-to-serial converter according to a preferred embodiment of the present invention; FIG. 2 is a block diagram showing the overall principle of a parallel-to-serial converter according to a preferred embodiment of the present invention; FIG. 3b is a schematic block diagram of a low-speed basic unit in a preferred embodiment of the present invention; FIG. 4 is a high-speed serialization module and a low-speed clock in a parallel-to-serial converter according to a preferred embodiment of the present invention; Schematic diagram of generating a circuit; FIG. 5 is a schematic diagram of a parallel-to-serial conversion method in a preferred embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict. The invention will be described in detail below with reference to the drawings in conjunction with the embodiments. The basic idea of the present invention is to use a low-speed serialization module suitable for a low-speed single-ended signal and a high-speed serialization module suitable for a high-speed double-ended signal to perform parallel-to-serial conversion on 24 ⁿ -bit low-speed parallel input data to obtain a 1-bit high-speed. Output data in parallel. A mode selection circuit located in the transmission module between the low-speed serialization module and the high-speed serialization module controls free switching of different operating modes, and automatically switches off the low-speed serialization module when switching from the first operating mode to the second operating mode. The addition of the transmission module can realize the multi-bit compatible working mode and the reverse order output function of the data through the control signal to enhance the adaptability of the circuit; in addition, the transmission module can also control the low-speed serialization module in the second while completing the conversion function. Power down in the operating mode, which can reduce the power consumption of the overall circuit. The first working mode is to convert the 2 ⁴ⁿ -bit low-speed parallel input data into a 1-bit high-speed string. The operation mode of the line output data, the second mode of operation is a parallel mode of converting the low 2 ²ⁿ bit data of the 2 ⁴ⁿ low-speed parallel input data into the 1-bit high-speed serial output data. In the following description, in the first mode of operation, the 2 ⁴ⁿ -bit low-speed parallel input data is converted into 1-bit high-speed serial output data block by block by the low-speed serialization module and the high-speed serialization module, and the output is controlled by the reverse-order control circuit in the transmission module. Mode; In the second working mode, 2 ²ⁿ bits of data are converted into 1-bit high-speed serial output data by the high-speed serialization module, and the output mode is controlled by the mode selection circuit in the transmission module. 1 is a basic principle block diagram of a parallel-to-serial converter of the present invention. As shown in FIG. 1, the parallel-to-serial converter of the present invention includes: a low-speed serialization module 101, a transmission module 102, a high-speed serialization module 103, and a buffer module 104; The serialization module 101, the transmission module 102 and the high-speed serialization module 103 are sequentially electrically connected, and the buffer module 104 is electrically connected to the high-speed serialization module 103. In the first working mode, the low-speed serialization module 101 and the high-speed serialization module 103 perform parallel-to-serial conversion on a block-by-block basis. The transmission module 102 determines that the current working mode is the first working mode according to the mode selection signal, and determines an output mode according to the control signal, and provides an output mode to the low-speed serialization module 101 and the high-speed serialization module 103 respectively; 2 ⁴ⁿ -bit low-speed parallel input data passes The low-speed serialization module 101 and the low-speed serialization module 101 perform low-speed serialization according to the output mode provided by the transmission module 102 and according to the set low-speed serialization ratio to obtain 2 ²ⁿ -bit high-speed parallel data; the above 2 ²ⁿ -bit high-speed parallel The data is input to the high-speed serialization module 103 through the transmission module 102, and the high-speed serialization module 103 performs high-speed serialization according to the output mode provided by the transmission module 102 and the set high-speed serialization ratio to obtain 1-bit high-speed serial output data. In the second working mode, the transmission module 102 determines that the current working mode is the second working mode according to the mode selection signal, and determines an output mode according to the control signal, provides an output mode to the high-speed serialization module 103, and automatically turns off the low-speed serialization module 101. Further, the low 2 ²ⁿ -bit data of the 24 ⁿ -bit low-speed parallel input data can be buffered by the buffer module 104 according to the set high-speed serialization ratio, and then input to the high-speed serialization module 103; the high-speed serialization module 103 can only The output mode provided by the transmission module 102 and the set high-speed serialization ratio serialize the buffered low-speed 2 ²ⁿ -bit high-speed parallel data to obtain 1-bit high-speed serial output data. According to the above description, the transmission module 102 controls the output mode of the 24 ⁿ -bit low-speed parallel input data, and controls the free switching of the working mode between the first working mode and the second working mode; and, when the working mode is switched from the second working mode to In the first mode of operation, the low speed serialization module 101 is automatically turned on. In addition, in the present invention, in order to reduce circuit loss, the low-speed serialization module 101 uses a single-ended signal structure, and the high-speed serialization module 103 uses a double-ended signal structure. The single-ended signal is a single-ended CMOS signal, and the double-ended signal is a double-ended CMOS differential signal. 2 is a schematic diagram of a preferred embodiment of a parallel-to-serial converter of the present invention. In the present embodiment, n=l is taken. In the preferred embodiment shown in FIG. 2, the parallel-to-serial converter includes: a reverse sequence control circuit 201, a low speed synchronization circuit 202, a low speed serializer 203, a mode selection circuit 204, a buffer 205, a high speed synchronization circuit 206, and a high speed string. The controller 207, the high-speed 4f generating circuit 208, and the fast-speed 4f generating circuit 209. In this embodiment, corresponding to FIG. 1, the low-speed serialization module 101 includes a low-speed synchronization circuit 202, a low-speed serializer 203, and a low-speed clock generation circuit 209; the transmission module 102 includes a reverse-order control circuit 201 and a mode selection circuit 204; The pass-through module 103 includes a high-speed sync circuit 206, a high-speed serializer 207, and a high-speed clock generation circuit 208; the buffer module 104 is a buffer 205; and the high-speed clock generation circuit 208 and the low-speed clock generation circuit 209 constitute a clock generation circuit. The reverse sequence control circuit 201, the low speed synchronization circuit 202, the low speed serializer 203, the mode selection circuit 204, the high speed synchronization circuit 206 and the high speed string converter 207 are sequentially electrically connected, and the buffer 205 is electrically connected to the mode selection circuit 204. The high speed clock circuit 209 is electrically connected to the low speed clock circuit 208. Meanwhile, the low speed clock generating circuit 209 is electrically connected to the low speed synchronizing circuit 202 and the low speed serializer 203, respectively, and the high speed clock generating circuit 208 and the high speed synchronizing circuit 206 and the high speed serializing circuit, respectively. The device 207 is electrically connected. In this embodiment, in the first mode of operation, the idle parallel input data with a 16-bit rate not exceeding 155 Mbps is synchronized by the low-speed synchronization circuit 202, and then subjected to 16:4 serialization by the low-speed serializer 203 to obtain a 4-bit rate. The parallel data of 622 Mbps; the parallel data of the 4-bit rate of 622 Mbps is input to the high-speed synchronization circuit 206 through the mode selection circuit 204, and after being synchronized by the high-speed synchronization circuit 206, the high-speed serializer 207 performs 4:1 serialization to obtain 1 bit. Serial output data at a rate of 2.5 Gbps. Synchronization of low speed parallel input data by low speed synchronization circuit 202 means synchronizing each bit of low speed parallel input data. In the second mode of operation, the lower 4-bit data of the low-speed parallel input data whose 16-bit rate does not exceed 155 Mbps is buffered by the buffer 205, and the buffered lower 4-bit data is input to the high-speed synchronous circuit through the mode selection circuit 204. 206 performs synchronization, and then performs 4:1 serialization via the high speed serializer 207 to obtain serial output data with a 1-bit rate of 2.5 Gbps. High speed synchronization circuit 206 for the lower 4 bits Synchronization of data refers to synchronizing each bit of parallel 4-bit data. Since the differential signal has the advantages of suppressing common mode interference, reducing noise, etc., the high speed serializer 207 can employ a differential structure to ensure output performance. The selection signals of the high speed serializer 207 are the clock signals CLK1 and CLK2, both of which are differential signals. The low-speed synchronization circuit 202 and the high-speed synchronization circuit 206 have the same structural principle, but the circuit parameters of the two are slightly different due to different environments. The differentiation between the two can ensure that the low speed synchronization circuit 202 achieves low power consumption while the high speed synchronization circuit 206 achieves high speed. The low-speed serializer 203 and the high-speed serializer 207 basically adopt a tree structure, and the tree structure is composed of a plurality of alternately multiplexed two-choice structures, and a two-to-one structure is used as a basic unit to realize 2n: The parallel conversion, it can be seen that the low-speed serializer 203 can realize the 16:4 parallel-to-serial conversion by using four 4:1 basic structures. The advantages of the tree structure are: low power consumption, easy clock acquisition, and highly symmetrical data channels. In this embodiment, the mode selection circuit 204 controls the free switching between the first working mode and the second working mode of the parallel-to-serial converter, and automatically turns off the low-speed serializing module when switching from the first working mode to the second working mode. 101, the low speed synchronization circuit 202, the low speed serializer 203 and the low speed clock generation circuit 209 are turned off; and when the second operation mode is switched to the first operation mode, the low speed serialization module 101 is automatically turned on. In addition, in the second operation mode, the mode selection circuit 204 controls the output mode of the input data, that is, the control of the output mode is completed by supplying the determined output mode to the high-speed serializer 207. In the present embodiment, in the first operation mode, the reverse sequence control circuit 201 controls the output mode of the input data, that is, by providing the determined output mode to the low-speed serializer 203 and the high-speed serializer 207, the output mode is completed. control. In this embodiment, the output mode includes a sequential output and a reverse output. The sequential output means that the input order of the input data is kept unchanged, and the reverse output means that the input data is output in reverse order of the input data byte, that is, the input data is taken in reverse order. In this embodiment, the buffer 205 is used to reduce the parasitic effect of the lower 4-bit data in the 16-bit low-speed parallel input data brought by the switching operation mode, thereby improving the conversion precision of the parallel-to-serial converter. The shutdown signal PDC is the switching signal of the parallel-to-serial converter. When the parallel-to-serial converter needs to perform data When the parallel-serial conversion is performed, the shutdown signal PDC is set to a valid value; when the parallel-to-serial converter does not need to perform parallel-to-serial conversion of data, the shutdown signal is set to an invalid value to save power. In this embodiment, the clock generation circuit provides clock signals of the respective stages for the above circuits. Specifically, the clock input signal CLK0 is input to the high speed clock generating circuit 208; the high speed clock generating circuit 208 supplies the clock signals CLK1 and CLK2 to the high speed serializer 207, and supplies the clock signal CLK2 to the high speed synchronizing circuit 206, and simultaneously generates the clock CLK2 for the low speed clock. The clock input signal CLK2 is provided; the low speed clock generating circuit 209 supplies the clock signals CLK3 and CLK4 to the low speed serializer 203 according to the clock signal CLK2 supplied from the high speed clock generating circuit 208, and supplies the clock signal CLK4 to the low speed synchronizing circuit 202 for each part. The included trigger provides a clock signal. The high speed clock generating circuit 208 and the low speed clock generating circuit 209 will input the high speed clock signal.

CLK0 is divided step by step to generate the clock signals required by each module of the system. Due to the difference in the operating environment of the high-speed clock generating circuit 208 and the low-speed clock generating circuit 209, the specific structure of the two is different. The high-speed clock generating circuit 208 can be a differential structure suitable for high speed; and the low-speed clock generating circuit 209 can be used. It can be an ordinary single-ended structure. For the relatively low-speed low-speed clock generating circuit 209, the mode selecting circuit 204 controls whether or not it generates an output signal, so that the low-speed circuit such as the low-speed synchronizing circuit 202 and the low-speed serializer 203 operates or stops working, thereby achieving effective system power reduction. The purpose of consumption. In this embodiment, the control signal of the reverse sequence control circuit 201 is MSB-SEL1, which can be active high, indicating sequential output in the first mode of operation; the reset signal of the low speed synchronization circuit 202 is RB 1 , and the output is clear when the level is 氐Zero; the control signal of the mode selection circuit 204 is MSB-SEL2, which can be active high, indicating that the current working mode is the first working mode; the selection signal is MODE-SEL, which can be active high, indicating the second working mode The lower order output is output; the reset signal of the high speed synchronizing circuit 206 is RB2, and the output is cleared when the level is low; the selection signal of the low speed clock generating circuit 209 is MODE-SEL, and the high level is valid. The initialization of the parallel-to-serial converter is completed by resetting, so that the parts of the parallel-to-serial converter are in an initial state and do not contain interference information. The parallel input data of the low-speed serializer 203 needs to be arranged, so that the output result is a high-to-low order of the parallel data. The two-stage selection signals used by the low-speed serializer 203 are the clock signals CLK3 and CLK4, CLK4, respectively. For the divided signal of CLK3, both duty cycles are 1. As can be seen from the above description, the data is converted from serial to serial in parallel from left to right, and the rate is from low to high; while 4f is stepped down from right to left. The following is an example of the idle parallel data "1011 0101 1001 1010" with a 16-bit rate of 155 Mbps as an example to illustrate the working principle of the parallel-to-serial converter in the first working mode and the second working mode: The first case: In the first work In mode, the output is sequential. The control signal MSB-SEL1=0 of the reverse sequence control circuit 201 is 氐 level, and is sequentially output; the selection signal MODE-SEL=1 of the mode selection circuit 204 is high level, and the low-speed clock generation circuit 209 operates normally, low-speed serialization The module 101 obtains the clock signal supplied from the low speed clock generating circuit 209, which also works normally and does not turn off.

The 16-bit parallel input data is passed through the reverse sequence control circuit 201, and is synchronized by the low-speed synchronization circuit 202 and the low-speed serializer 203 to perform 16:4 serialization to obtain parallel data of 4 bits at a rate of 622 Mbps; the above-mentioned 4-bit rate is 622 Mbps of parallel data passing. The mode selection circuit 204 performs 4:1 serialization by the high-speed synchronization circuit 206 and the high-speed serializer 207 to obtain serial output data with a 1-bit rate of 2.5 Gbps, which are: T, "0", "1", Τ, "0", Τ, "0", Τ, Τ, "0", "0", "1", "1", "0", ", "0". Meanwhile, the high-speed 4f generation circuit 208 The clock signal is also provided for the high speed serialization module 103. The second case: in the first operation mode, the reverse output is output. The control signal MSB-SEL1=1 of the reverse sequence control circuit 201 is high level, reverse order output; mode selection circuit The selection signal MODE-SEL=l of 204 is high level. Similarly, the low-speed serialization module 101 is not turned off.

The 16-bit parallel input data is passed through the reverse-sequence control circuit 201, and is synchronized by the low-speed synchronization circuit 202 and the low-speed serializer 203 to perform 16:4 serialization to obtain parallel data with a 4-bit rate of 622 Mbps; the above-mentioned 4-bit rate is 622 Mps of parallel data passing. The mode selection circuit 204 performs 4:1 serialization by the high-speed synchronization circuit 206 and the high-speed serializer 207 to obtain serial output data with a 1-bit rate of 2.5 Gbps, which are: "0", "1", "0. ", "1", "1", "0", "0", "1", "1", "0", "1", "0", "1", "1", "0", "1". At the same time, the high speed 4f generation circuit 208 also provides a clock signal to the high speed serialization module 103. The third case: In the second working mode, the output is sequential. The selection signal MODE-SEL=0 of the mode selection circuit 204 is low level, and the low-speed clock generation circuit 209 is controlled by the mode selection circuit 204 so that the selection signal is inactive, so that the low-speed serialization module 101 cannot obtain the operation clock signal. And off; control of the mode selection circuit 204 The signal MSB-SEL2=0, which is 氐 level, and is output sequentially.

The lower 4 bits "1010" of the 16-bit parallel input data are 4:1 serialized by the high speed synchronizing circuit 206 and the high speed serializer 207 through the buffer 205 and the mode selecting circuit 204, resulting in a 1-bit rate of 2.5 Gbps. Serial output data, in order: "1", "0", "1", "0". At the same time, the high speed clock generation circuit 208 provides clock signals for the high speed synchronization circuit 206 and the high speed serializer 207. The fourth case: In the second working mode, the output is reversed. The selection signal of the mode selection circuit 204 is MODE-SEL=0, which is low level. Similarly, the low-speed serialization module 101 is turned off; the control signal MSB-SEL2=1 of the mode selection circuit 204 is high level, and is output in reverse order. The lower 4 bits of the 16-bit parallel input data "1010" pass through the buffer 205 and the mode selection circuit

204, through the high-speed synchronization circuit 206 synchronization and high-speed serializer 207 for 4: 1 serialization, to obtain a 1-bit rate of 2.5Gbps serial output data, in order: "0", "1", "0", "1". At the same time, the high speed clock generation circuit 208 provides a clock signal to the high speed synchronization circuit 206 and the high speed serializer 207. 3a and 3b are circuit schematic diagrams of the low speed synchronization circuit 202 and the low speed serializer 203 in the low speed serialization module 101 of the present embodiment. In FIG. 3a, the low speed synchronizing circuit 202 and the low speed serializer 203 include: a first low speed basic unit 301, a second low speed basic unit 302, a third low speed basic unit 303, a fourth low speed basic unit 304, and a buffer 8, each of which The low speed base unit is electrically connected in parallel by the reset signal RB 1 and the clock signal CLK4 supplied from the low speed clock circuit 209. Among them, the 16-bit Din<15>~Din<0> parallel input data with a rate not higher than 155 Mbps is arranged and combined according to the setting principle according to the setting principle, and four sets of low-speed parallel data are obtained, for example, the adjacent two-bit difference is 8: The first group is Din<15>, Din<7>, Din<ll>, Din<3>, and the second group is Din<14>, Din<6>, Din<10>, Din<2>, The third group is Din<13>, Din<5>, Din<9>, Din<l>, and the fourth group is Din<12>, Din<4>, Din<8>, Din<0>; The group data is parallel-converted by the fourth low-speed base unit 304 to obtain 1-bit serial output data; the second group data is parallel-converted by the third low-speed base unit 303 to obtain 1-bit serial output data; The second low-speed base unit 302 performs parallel-serial conversion to obtain 1-bit serial output data, and the fourth group data is parallel-converted by the first low-speed base unit 301 to obtain 1-bit serial output data. After the parallel-serial conversion, parallel data of a 4-bit rate of 622 Mbps is output from the fourth low-speed base unit 304 to the first low-speed base unit 301, for example, four low-speed basic units output from high to low after the first parallel-to-serial conversion. Bit and Row data Din<15>, Din<13>, Din<14>, Din<12>; four sets of transformed parallel data are sequentially output through four parallel-to-serial conversions. In FIG. 3b, the first low speed basic unit 301 includes: an 11th synchronous D flip-flop 1, a 12th synchronous D flip-flop 2, a 13th synchronous D flip-flop 3, a 14th synchronous D flip-flop 4, and an 11th selector 5 The twelfth selector 6 and the thirteenth selector 7. The fourth group of data Din<12>, Din<4>, Din<8>, and Din<0> are input to the 11th to 14th synchronous D flip-flops respectively, Din<12> and Din<4>, Din<8>, and Din. <0> is divided into ¹ by the 11th selector 5 and the 12th selector 6 to perform the selection of 2, 1 and the first round selects 1 bit of data Din<12> and Din<8>, respectively, by the 11th selector The two bits of data obtained by the 5th and 12th selectors 6 are further selected by the 13th selector 7 to obtain the data Din<12> having a 1-bit rate of 622 Mbps. The lower 4 bits of data are sequentially output after four rounds of selection. In sequential output, the selector selects the output from high to clamp; in the reverse output, the selector selects the output from low to high. The clock signal of the 11th to 14th synchronous D flip-flops is CLK4, and the reset signal is RB1; the clock signals of the 11th selector 5 and the 12th selector 6 are the clock signal CLK4D buffered by the buffer 8 by the CLK4; The clock signal of the 13th selector is CLK3. It can be seen that the four low-speed basic units perform the same operation separately, and finally obtain 4-bit parallel output data. The clock signal of each synchronous D flip-flop is the 16-divided clock signal CLK4 generated by the low-speed clock generating circuit 209, and the CLK4 is buffer-buffered by the buffer 8 to obtain the clock signal CLK4D as the 11th selector 5 and the 12th selection. The selection signal of the device 6; the clock signal CLK3 divided by 8 is used as the selection signal of the thirteenth selector. In addition, among the four low-speed basic units, 16 parallel synchronous D flip-flops need to consider the driving ability of the clock signal, and a buffer 9 can be added to the clock input end of each synchronous D flip-flop to improve the clock signal CLK4. Drive capability. During initialization, the reset signal RB1 is set to a valid value, and each synchronous D flip-flop output is cleared. In normal operation, the reset signal RB 1 is set to an invalid value. 4 is a circuit schematic diagram of the high speed serialization module 103 and the low speed clock generation circuit 209 of the present embodiment. In this embodiment, the high speed serialization module 103 includes a high speed synchronization circuit 206, a high speed serializer 207, and a high speed clock generation circuit 208. . The high speed synchronization circuit 206 includes a 51st synchronous D flip-flop 501 and a 52nd synchronous D flip-flop 507. The 53rd synchronous D flip-flop 508 and the 54th synchronous D flip-flop 515. The high speed serializer 207 includes a 51st selector 502, a 52nd selector 511, a 51st zeroth stage buffer BUF0 503, a 52nd BUFO 512, a 1st latch 504, a 2nd latch 505, and a 3rd lock. The memory 506, the fourth latch 513, the fifth latch 514, the high speed selector 509, and the first high speed synchronous D flip-flop 510. The low-speed clock generating circuit 209 includes a 55th synchronous D flip-flop 527, a 56th synchronous D flip-flop 526, a 57th synchronous D flip-flop 524, a 51st buffer BUF 522, a 52nd BUF 521, a 53rd BUF 518, and a 54th. BUF 520, 55th BUF 525, 56th BUF 523, 57th BUF 517 and 58th BUF 531. The high speed clock generation circuit 208 includes a first cache Fast BUF 530, a second high speed synchronous D flip-flop 529, a second Fast BUF 516, a third Fast BUF 519, and a first stage buffer BUF1 528. Wherein, in the 4f circuit 209 during the idle synchronization, the time word CLKDIV4 sequentially passes through the 52nd BUF 521 and the 54th BUF 520 to obtain the synchronization time word CLKDIV4SYN; meanwhile, the time word CLKDIV4 passes through the 52nd BUF 521 and the 53rd BUF. 518 gets control word CLKDIV4SEL, the 51st to 54th synchronous D flip-flops under the control of the synchronous clock signal CLKDIV4SYN, the 2 ²ⁿ -bit high-speed parallel data is synchronized, divided into a group of four bits of data, each group of data is input separately Four synchronous D flip-flops are synchronized, and then the data processed by the synchronous D flip-flop is set in pairs, and each group is input into a 2-to-1 selector, for example, the highest-order data and the next-highest data are input to the 51st selector. 502, input the second lower data and the lowermost data into the 52nd selector 511. Under the control of the control clock signal CLKDIV4SEL, the 51st selector and the 52nd selector respectively select the output data DS0 and DS1; DS0 and DS1 are respectively input. 51st BUF0 503 and 52nd BUF0 512, convert single-ended CMOS signals into double-ended CMOS differential signal pairs, respectively output DD0P and DD0N, DD1P and DD1N two pairs of differential signals; pass differential signals to DD0P and DD0N The first to third latch, and the differential signal pairs DD1P DD1N 4-5 by the second latch, and are input to the selector 509 a high speed. The latch enables the clock signal to arrive first and the data signal to arrive later to ensure an orderly output of the data. Wherein, the first to third latches are electrically connected in sequence, and the fourth to fifth latches are electrically connected. In the high speed clock generating circuit 208, the second high speed synchronous D flip-flop 529 outputs the differential clock signal pair CLKDIV2P and CLKDIV2N, The first to fifth latches provide a selection signal, and the clocks of the adjacent two latches are opposite in phase, so that the two input channels of the high speed selector 509 can be separated by a half cycle, so that the selected clock of the high speed selector 509 can have The large phase margin avoids glitch in the high speed environment due to the difference in glitch width and data width. Although the 1st to 5th latches increase the circuit scale and power consumption, they ensure that the system operates at a higher frequency. In addition, the first high The fast synchronous D flip-flop 510 is a high speed synchronous output circuit that receives the differential signal output by the high speed selector 509, and then synchronously outputs the differential signal according to the clock signal output by the second Fast BUF 516, which is a high speed differential clock signal. Obtained after CLKDIP and CLKDIN are buffered by the 2nd Fast BUF. The low-speed clock generating circuit 209 and the high-speed clock generating circuit 208 have the same principle, and each of the clock signals is divided by a flip-flop to obtain clock signals of the respective stages. In FIG. 4, a pair of high-speed differential time-to-speech pairs CLKIP and CLKIN correspond to the time word CLK0 in FIG. 2, and the first fast BUF 530 is input to obtain a differential-time word pair CLKDIP and CLKDIN, corresponding to the time number in FIG. CLK1. The differential time word pair CLKDIP and CLKDIN are output through the second Fast BUF 516 to the first high speed synchronous D flip-flop 510 as the synchronous clock signal of the first high speed synchronous D flip-flop 510; and the CLKDIP and CLKDIN outputs to the second high speed synchronous D The flip-flop 529, the inverting output terminal of the second high-speed synchronous D flip-flop 529 is short-circuited with the input terminal to form a T flip-flop, that is, when the clock edge of CLKDIP and CLKDIN comes, the differential clock output by the second high-speed synchronous D flip-flop 529 The signal pair will flip on CLKDIV2P and CLKDIV2N. Similarly, the differential clock signal outputted by the second high-speed synchronous D flip-flop 529 supplies clock signals to the first to fifth latches through the third Fast BUF 519 to the CLKDIV2P and CLKDIV2N; on the other hand, the high-speed differential clock signal is transmitted through the BUF1 528. After being converted into a single-ended clock signal, it is input to the 55th synchronous D flip-flop 527; and is input to the 56th synchronous D flip-flop 526 via the 51st BUF 522; the 56th synchronous D flip-flop 526 outputs the clock signal CLKDIV8 via the 55th The BUF 520 is input to the 57th synchronous D flip-flop 524, and the 55th to 57th synchronous D flip-flops constitute a frequency divider, and the respective stages of the words CLKDIV4, CLKDIV8, and CLKDIV16 are generated, which correspond to CLK2, CLK3, and CLK4 in FIG. 2, respectively. Among them, in order to enhance the driving ability of the clock signal and improve the accuracy of the clock sample, the 51st to 58th BUF is added to the clock signal generation path, and the 51st to 58th BUFs can be referred to as the in-phase buffer. The 1st to 3th Fast BUF and the 1st BUF1 are called inverting buffers. Each buffer does not perform any operation on its input value. Its output value is the same as the input value. It simply delays the input value to push the current of the circuit to a higher level. The same phase buffer is used for delay buffering each stage clock signal and converting into clock signals of the same phase; the inverting buffer is used for delay buffering each stage clock signal and converting into opposite phases. Clock signal. In this embodiment, RB2 is a reset signal of the 51st to 57th synchronous D flip-flops, and when RB2 is a valid signal, each synchronous D flip-flop output is cleared. The high-speed serialization module 103 operates at a high rate, which imposes a high requirement on the anti-jamming capability of the internal signal. Because the double-ended differential structure has low linearity requirements on the input, small amplitude, and strong anti-interference ability, the differential structure is used in the high-speed circuit structure. As shown in Fig. 4, the circuit structure of the first to fifth latches is shown. The circuit configuration of the high speed selector 509, the circuit configuration of the first high speed synchronous D flip-flop 510 and the second high speed synchronous D flip-flop 529, the circuit configuration of the first to third Fast BUF, and the first and second ends for mutual conversion The 51-53 BUF circuit structure uses a differential structure. In the present embodiment, the reset signal RB1 of the idle synchronizing circuit 202 and the reset signal RB2 of the high speed synchronizing circuit 206 may be the same set signal, or may be different set signals. FIG. 5 is a schematic diagram of the parallel-to-serial conversion method of the embodiment. In FIG. 5, the parallel-to-serial conversion method includes the following steps: Step 601: Determine an operation mode and an output mode of the parallel-to-serial converter, and perform step 602 or step 605 according to the selected working mode and output mode; : The parallel-to-serial converter works in the first working mode, and according to the determined output mode and the set low-speed serialization ratio, low-speed serialization of the 2 ⁴ⁿ -bit low-speed parallel input data is performed, and 2 ²ⁿ -bit high-speed parallel data is obtained; And performing high-speed serialization on the 2 ²ⁿ high-speed parallel data according to the determined output mode and the set high-speed serialization ratio to obtain one high-speed serial output data; Step 603: The parallel-serial converter operates in the second working mode According to the determined output mode and the set high-speed serialization ratio, the 2 ²ⁿ -bit data of the 2 ⁴ⁿ -bit low-speed parallel input data is parallel-serial converted, and the obtained low 2 ²ⁿ -bit data is buffered, and then according to The determined output mode and the set high-speed serialization ratio are serialized to obtain one high-speed serial output data. The above output modes include sequential output and reverse output. The sequential output means that the input order of the input data is kept unchanged, and the reverse output means that the input data is output in reverse order of the input data byte, that is, the input data is taken in reverse order. In this embodiment, the parallel-to-serial converter uses a 0.13 um CMOS process with a supply voltage of 1.2V. In addition, the power supply voltage of IV may be used in a 90 nm CMOS process, but attention should be paid to the low voltage design in the high speed differential structure. According to an embodiment of the present invention, there is also provided a computer readable medium having stored thereon instructions for causing a processor to perform the above-described operation as shown in FIG. 5 when the instructions are executed by a processor Processing, regarding the details of the processor and its instructions, can refer to the above description of Figure 5 To understand and implement. Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device, such that they may be stored in the storage device by the computing device, or they may be separately fabricated into individual integrated circuit modules, or they may be Multiple modules or steps are made into a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software. The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention. For those skilled in the art, the present invention can be variously modified and modified. Any modifications, equivalent substitutions, improvements, etc. made therein are intended to be included within the scope of the present invention.

Claims

Claim

A parallel-to-serial converter, comprising: a low-speed serialization module, a transmission module, and a high-speed serialization module, wherein:

The transmission module is configured to determine a current working mode according to the mode selection signal, and determine an output mode according to the control signal, where the first working mode is further configured to provide the output mode to the low-speed serialization module and the high-speed serialization module; In the second working mode, the output mode is provided to the high-speed serialization module, and the low-speed serialization module is turned off, and the low 2 ²ⁿ -bit data of the 2 ⁴ⁿ -bit low-speed parallel input data is input into the buffer module according to the set high-speed serialization ratio;

The low-speed serializer module, the first mode of operation, according to the output, and the proportion of the low-speed serial set of 2 ^4n-bit low-speed parallel data string of input, to provide the high-speed parallel data bits 2 ²ⁿ ;

The high-speed serialization module, in the first working mode, is configured to serialize the 2 ²ⁿ -bit high-speed parallel data according to the output mode and according to the set high-speed serialization ratio, to obtain a 1-bit high-speed string. Line output data; in the second working mode, for serializing the low 2 ²ⁿ bit low speed parallel input data according to the output mode and the set high speed serialization ratio, to obtain 1 bit high speed serial output data;

Where n is a natural number.

2. The parallel-to-serial converter according to claim 1, wherein the low-speed serialization module comprises: a low-speed synchronization circuit, a low-speed serializer, and a low-speed clock generation circuit, wherein:

The low-speed synchronous circuit, the first operation mode, a low speed for 2 ^4n-bit parallel input data is synchronized, synchronizing low to give 2 ^4n-bit parallel data;

The low-speed serializer, according to the output, and high speed in accordance with 2 ^2n-bit parallel data string of the low-speed ratio is set to the synchronous parallel data 2 ^4n-bit string of the low-speed low speed, to give;

The low speed clock generating circuit is configured to provide a clock signal to the low speed synchronizing circuit and the low speed serializer, respectively.

3. The parallel-to-serial converter according to claim 1, wherein the transmission module comprises a reverse sequence control circuit and a mode selection circuit, wherein:

The reverse sequence control circuit is configured to receive 2 ⁴ⁿ bits of low-speed parallel input data in a first working mode, and determine an output mode according to a control signal thereof; the mode selection circuit is configured to determine an output mode according to a control signal of the same, Receiving 2 ²ⁿ -bit low-speed parallel input data, and automatically turning off the low-speed serialization module when switching from the first working mode to the second working mode, or automatically turning on the low-speed serialization module when switching from the second working mode to the first working mode.

4. The parallel-to-serial converter according to claim 1, wherein the high speed serialization module comprises: a high speed synchronization circuit, a high speed serializer, and a high speed time 4f generation circuit, wherein:

The high-speed synchronization circuit is configured to synchronize the received 2 ²ⁿ -bit high-speed parallel data to obtain 2 ²ⁿ -bit high-speed synchronous parallel data;

The high-speed serializer is configured to serialize the 2 ²ⁿ -bit high-speed synchronous parallel data to obtain 1-bit high-speed serial output data;

The high speed clock generating circuit is configured to provide a clock signal to the high speed synchronous circuit and the high speed serializer, respectively.

5. The parallel-to-serial converter according to claim 1, further comprising a buffer module connected to the high-speed serialization module, in the second operation mode, for the low 2 ²ⁿ bits High-speed parallel data is buffered, and the buffered low 2 ²ⁿ bits of data are input to the high-speed serialization module.

The parallel-to-serial converter according to claim 1, wherein the low-speed serialization module includes at least four low-speed basic units, and in the first working mode, respectively, for receiving 2 ⁴ⁿ -bit low-speed parallel input data respectively The high-to-low-bit data of each group of 4 bits is serialized to output 2 ²ⁿ -bit high-speed parallel data to the high-speed serialization module; wherein each low-speed basic unit shares a reset signal and a clock signal;

The low-speed basic unit includes four synchronous D flip-flops and three two-selective selectors,

The synchronous D flip-flop is configured to synchronize each received low-speed parallel data; the first two-selection selector and the second two-selection selector are configured to receive the synchronized two-two sets of data, After selecting, output two-digit parallel data to the third two-selector;

The third two-selection selector is configured to select the received parallel data, and output one Bit data.

The parallel-to-serial converter according to claim 1, wherein the high-speed serialization module comprises: four synchronous D flip-flops, one high-speed synchronous D flip-flop, two two-selection selectors, and one second Select a high speed selector, two zero level buffers and two latch modules;

The synchronous D flip-flop is configured to synchronize the received 2 ²ⁿ -bit high-speed parallel data divided into a group of four bits of data;

The two-selection selector is configured to receive two or two sets of data after synchronization, and output two-bit parallel data after being selected;

A high-speed synchronous D flip-flop for synchronously outputting modules respectively through two zero-order buffers and two latch modules to obtain one high-speed serial data;

Wherein, each part shares a reset signal and a clock signal.

The parallel-to-serial converter according to claim 7, wherein, in the two latch modules, the first latch module and the second latch module are different by half a clock cycle, wherein The first latch module includes at least three latches that are electrically connected in sequence, and the second latch module includes at least two latches that are electrically connected in sequence; each latch shares a clock signal.

9. The parallel-to-serial converter according to claim 2, wherein the low-speed clock generating circuit comprises: three synchronous D flip-flops, eight in-phase buffers, four inverting buffers, and a high speed synchronous D flip-flop, where

Each of the synchronous D flip-flops is configured to generate clock signals of each stage;

The non-inverting buffer is configured to delay buffering each stage clock signal into a clock signal of the same level and phase;

The inverting buffer is configured to delay buffering each stage clock signal into a clock signal with opposite phases;

The high speed synchronous D flip-flop is used for dividing the input clock signal and outputting it to the buffer and the frequency divider.

10. A parallel-to-serial conversion method, comprising:

Determine the working mode and output mode; In the first working mode, according to the determined output mode and the set low-speed serialization ratio, low-speed serialization of the 2 ⁴ⁿ -bit low-speed parallel input data is performed, and 2 ²ⁿ -bit high-speed parallel data is obtained; and then according to the determined output mode and setting a high-speed serialization ratio, high-speed serialization of the 2 ²ⁿ high-speed parallel data, to obtain a high-speed serial output data;

In the second working mode, according to the determined output mode and the set high-speed serialization ratio, the low 2 ²ⁿ -bit data of the 2 ⁴ⁿ -bit low-speed parallel input data is parallel-serial converted, and the obtained low 2 ²ⁿ -bit data buffer is obtained. After that, serialization is performed according to the determined output mode and the set high-speed serialization ratio, and 1-bit high-speed serial output data is obtained.