CN110401343B - Dual charge pump parallel boost circuit - Google Patents
Dual charge pump parallel boost circuit Download PDFInfo
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- CN110401343B CN110401343B CN201910601897.6A CN201910601897A CN110401343B CN 110401343 B CN110401343 B CN 110401343B CN 201910601897 A CN201910601897 A CN 201910601897A CN 110401343 B CN110401343 B CN 110401343B
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- 239000003990 capacitor Substances 0.000 claims abstract description 98
- 230000000087 stabilizing effect Effects 0.000 claims abstract description 37
- 101150070727 CSNK2B gene Proteins 0.000 claims description 10
- 102100027992 Casein kinase II subunit beta Human genes 0.000 claims description 10
- 238000010586 diagram Methods 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/077—Charge pumps of the Schenkel-type with parallel connected charge pump stages
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention discloses a dual-charge pump parallel boost circuit, which comprises two cascaded first charge pump circuits, wherein the input end of each first charge pump circuit is provided with a second charge pump circuit, each second charge pump circuit comprises four switching tubes M5-M8, each switching tube M5 is connected with a switching tube M6 through a capacitor C2P, the common end of each switching tube M5 and the capacitor C2P is connected with a switching tube M7, the common end of each switching tube M6 and the capacitor C2P is connected with a switching tube M8, each switching tube M6 and each switching tube M7 is connected with a level VCI, each switching tube M5 is connected with a level VSSA, the output end of each switching tube M8 is connected with a voltage stabilizing capacitor C2, and the voltage stabilizing capacitor C2 outputs boost voltage to one first charge pump circuit. The invention adopts a parallel structure of double charge pumps, and can be raised to higher voltage without cascading more charge pump circuits.
Description
Technical Field
The invention relates to the field of charge pump circuits, in particular to a dual-charge pump parallel boost circuit.
Background
The charge pump circuit is widely applied to a driving circuit of a liquid crystal display because of the characteristics of voltage boosting and voltage reducing. In order to save the cost of the chip, the chip is only externally connected with a main power supply of about 3 v. In the driving circuit of the display screen, since the gate electrode of the TFT (thin film transistor) is driven and data transmission is performed, a gate driving circuit (gate circuit) and a source driving circuit (source and gamma circuits) are required, and in order to ensure a good display screen, the range of data is generally relatively wide, and a 3v power supply is insufficient. Therefore, a charge pump circuit is required to supply a power supply voltage of about + -12V to the gate circuit, and a power supply voltage of about + -6V to the source and gamma circuits. In order to continue to reduce the cost, even a charge-discharge capacitor (fly cap) and a voltage stabilizing capacitor of the charge pump are built in the chip.
For the above application environment, for the charge pump with built-in capacitor, because the fly cap capacitor and the voltage stabilizing capacitor cannot be made very large, and meanwhile, in order to further save area, for the high-voltage charge pump structure, a high-voltage tube is generally not used, so that the efficiency of the charge pump is improved, and how to process the power supply range of the clock control signal, the level conversion without high voltage can be avoided, and the method becomes very important.
The main architecture of the conventional charge pump is shown in fig. 1: this charge pump is a structure of N stages of CELL1 cascade. A circuit diagram of three-level cascading boost to 4 times VCI is shown. The clock-controlled output signals CK1P and CK1N in CELL1 are a pair of inverted signals, as shown in fig. 2. The level of the signal is switched between 0 and 3v (VCI level), and is a square wave. The capacitors C1P and C1N are charge-discharge capacitors, and the capacitor C1 is a voltage stabilizing capacitor. NMOS transistors M1 and M2, and PMOS transistors M3 and M4 are switching transistors. When CK1P is at VCI level and CK1N is at 0 level, the voltage at point B is VCI and the voltage at point a is 2×vci. At this time M3 is on and V1 output is 2 vci. At the next moment, when CK1P is at 0 level and CK1N is at VCI level, the voltage at point B is 2×vci and the voltage at point a is VCI due to the characteristic that the charges on both sides of the capacitor remain unchanged. At this time, M4 is turned on, V1 has an output of 2×vci, and the operation principle of each CELL is the same, so more CELL1 cascade is required to raise to a higher voltage.
The main disadvantages of this circuit are: if the voltage is increased to a higher voltage, more CELL1 cascade is needed, so the efficiency is lower and the occupied area is larger.
Disclosure of Invention
The invention provides a dual charge pump parallel booster circuit, which solves the problems that in the prior art, if the voltage is required to be increased to a higher voltage, more CELL1 stages are required to be connected, so that the efficiency is lower and the occupied area is larger.
The technical scheme of the invention is realized as follows:
the utility model provides a parallel boost circuit of two charge pumps, includes two cascaded first charge pump circuits, the input of first charge pump circuit is equipped with the second charge pump circuit, the second charge pump circuit includes four switch tube M5-M8, switch tube M5 is connected switch tube M6 through electric capacity C2P, switch tube M7 is connected with electric capacity C2P's common end to switch tube M5, switch tube M8 is connected to the common end of switch tube M6 and electric capacity C2P, level VCI is all connected to switch tube M6 and M7, level VSSA is connected to switch tube M5, voltage stabilizing capacitor C2 is connected to switch tube M8 output, and voltage stabilizing capacitor C2 outputs the boost voltage to one first charge pump circuit.
As a preferred embodiment of the present invention, the number of the second charge pump circuits is 2, the two second charge pump circuits adopt a mirror symmetry structure, and the output ends of the two second charge pump circuits are both connected with the stabilizing capacitor C2.
As a preferred embodiment of the present invention, the first charge pump circuit includes a switching tube M1-M4, the voltage stabilizing capacitor C2 is connected to the switching tube M1 and the switching tube M2, the switching tube M1 is connected to the switching tube M4 and the capacitor C1P, the switching tube M2 is connected to the switching tube M3 and the capacitor C1N, the switching tube M3 is connected to the capacitor C1N, the switching tube M4 is connected to the capacitor C1P, an input end of the capacitor C1P is connected to the control timing CK2P, an input end of the capacitor C1N is connected to the control timing CK2N, and an output end of the switching tube M3-M4 is connected to the voltage stabilizing capacitor to output a stable boost voltage.
As a preferred embodiment of the present invention, the control timings CK2N and CK2P are two-phase square waves.
The double-charge pump parallel boost circuit comprises a first charge pump circuit and two second charge pump circuits, wherein one second charge pump circuit comprises switching tubes M1-M4, the other second charge pump circuit comprises switching tubes M5-M8, the switching tube M1 is connected with a switching tube M2 through a capacitor C1, the common end of the switching tube M1 and the capacitor C1 is connected with a switching tube M3, the common end of the switching tube M2 and the capacitor C1 is connected with the switching tube M4, the switching tubes M2 and M3 are both connected with a level VCI, the switching tube M1 is connected with a level VSSA, the output end of the switching tube M4 is connected with a voltage stabilizing capacitor C11, and the voltage stabilizing capacitor C11 is connected with a switching tube M7; the switch tube M7 is connected with the switch tube M8 through the capacitor C2, the common end of the switch tube M7 and the capacitor C2 is connected with the switch tube M5, the switch tube M5 is connected with the level VSSA, the common end of the switch tube M8 and the capacitor C2 is connected with the switch tube M6, the output end of the switch tube M8 is connected with the voltage stabilizing capacitor C22, the output end of the voltage stabilizing capacitor C22 is connected with the first charge pump circuit, and the first charge pump circuit outputs the boosting level.
As a preferred embodiment of the present invention, a first charge pump circuit for providing a gate control signal to the switching transistor M6/M8 is further included.
As a preferred embodiment of the present invention, the first charge pump circuit is a medium voltage MOS transistor boost charge pump.
The invention has the beneficial effects that: the parallel structure of the double charge pumps is adopted, and the voltage can be increased to a relatively high voltage without cascading more charge pump circuits.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is a schematic diagram of a prior art charge pump boost circuit;
FIG. 2 is a signal timing diagram of a charge pump boost circuit;
FIG. 3 is a circuit diagram of a dual charge pump parallel boost circuit according to one embodiment of the present invention;
FIG. 4 is a circuit diagram of a second embodiment of a dual charge pump parallel boost circuit according to the present invention; a step of
FIG. 5 is a circuit diagram of a third embodiment of a dual charge pump parallel boost circuit according to the present invention;
fig. 6 is a circuit diagram of a first charge pump circuit providing a gate control signal.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
As shown in fig. 3, the invention provides a dual-charge pump parallel boost circuit, which comprises two cascaded first charge pump circuits (CELL 1), wherein the input end of each first charge pump circuit is provided with a second charge pump circuit (CELL 2), each second charge pump circuit comprises four switching tubes M5-M8, each switching tube M5 is connected with a switching tube M6 through a capacitor C2P, the common end of each switching tube M5 and the capacitor C2P is connected with a switching tube M7, the common ends of each switching tube M6 and the capacitor C2P are connected with a switching tube M8, the switching tubes M6 and M7 are both connected with a voltage level VCI, the switching tube M5 is connected with a voltage stabilizing capacitor C2, and the output end of each switching tube M8 is connected with a voltage boosting voltage to one first charge pump circuit.
The clock control signals C2P/C2N are identical to those in FIG. 2 in time sequence, except that the ranges of levels are different: assume that at time TI, M5 and M6 in the CELL2 CELL are turned on, and the voltage across capacitor C2P is VSSA (0V)/VCI (3V), respectively. At time T2, switching transistors M7 and M8 are turned on, and M5 and M6 are turned off. The voltage to the left of C2P is switched from VSSA to VCI, and the voltage to the right of C2P is boosted from VCI to 2 times VCI due to the characteristic that the charge on both sides of the capacitor remains unchanged. When M8 is on, the voltage at VH1 point is 2 vci. Because the voltage stabilizing capacitor C2 exists, the voltage of the VH1 can not be pulled very low when the CELL1 works, and the whole charge pump can be ensured to work normally as long as the CELL2 can timely supplement charges to the voltage stabilizing capacitor C2. In order to improve the load capacity of the whole charge pump, CELL2 can be parallel, and the clock is two-phase, namely, the switch is always conducted to charge the voltage stabilizing capacitor C2 when T1 or T2 is ensured.
Example two
The number of the second charge pump circuits is 2, the two second charge pump circuits adopt mirror symmetry structures (ping-pong structures), and the output ends of the two second charge pump circuits are both connected with a voltage stabilizing capacitor C2.
In the above two embodiments, the circuit structures of the first charge pump are the same, the first charge pump circuit includes switching transistors M1-M4, a voltage stabilizing capacitor C2 is connected to the switching transistor M1 and the switching transistor M2, the switching transistor M1 is connected to the switching transistor M4 and the capacitor C1P, the switching transistor M2 is connected to the switching transistor M3 and the capacitor C1N, the switching transistor M3 is connected to the capacitor C1N, the switching transistor M4 is connected to the capacitor C1P, an input end of the capacitor C1P is connected to the control timing sequence CK2P, an input end of the capacitor C1N is connected to the control timing sequence CK2N, and an output end of the switching transistors M3-M4 is connected to the voltage stabilizing capacitor to output a stable boost voltage. The control timings CK2N and CK2P are two-phase square waves.
When M5/M6 is on, M11 and M12 are on, and the charge on capacitor C3P is transferred to C2. When M7/M8 is on, M9 and M10 are on to charge C3P. At this point the charge on C2P is transferred onto C2. The ping-pong structure of the CELL2 can ensure that the charge of the voltage stabilizing capacitor C2 is timely supplemented, so that the input voltage of the following CELL1 is as high as possible, the output voltage value of the charge pump can be close to a theoretical value, and the charge loss is reduced as much as possible. Since the input voltage VH1 of CELL1 can theoretically reach 2×vci, and the clocks CK2P and CK2N in fig. 3 and 4 can be changed to clock signals in the voltage range of 0 to VH1 through level shift (level_shift), the output voltage VH2 of CELL1 can theoretically reach 4×vci, and the output voltage VH3 of the second stage CELL1 can reach 6×vci. Compared to the charge pump structure of fig. 1, with three stages of CELL1 cascades, the output voltage can only reach 4 vci. In fig. 3 and fig. 4, due to the parallel structure of CELL1 and CELL2, the voltage can be raised to 6 vci by three stages, and the efficiency is improved by 30%.
Example III
As shown in fig. 5, the invention further provides a dual-charge pump parallel boost circuit, which comprises a first charge pump circuit and two second charge pump circuits, wherein one second charge pump circuit comprises switching tubes M1-M4, the other second charge pump circuit comprises switching tubes M5-M8, the switching tube M1 is connected with a switching tube M2 through a capacitor C1, the switching tube M1 is connected with a switching tube M3 at the common end of the capacitor C1, the switching tube M2 is connected with a switching tube M4 at the common end of the capacitor C1, the switching tubes M2 and M3 are both connected with a voltage level VCI, the switching tube M1 is connected with a voltage stabilizing capacitor C11, and the voltage stabilizing capacitor C11 is connected with a switching tube M7; the switch tube M7 is connected with the switch tube M8 through the capacitor C2, the common end of the switch tube M7 and the capacitor C2 is connected with the switch tube M5, the switch tube M5 is connected with the level VSSA, the common end of the switch tube M8 and the capacitor C2 is connected with the switch tube M6, the output end of the switch tube M8 is connected with the voltage stabilizing capacitor C22, the output end of the voltage stabilizing capacitor C22 is connected with the first charge pump circuit, and the first charge pump circuit outputs the boosting level. A first charge pump circuit for providing a gate control signal to the switching transistor M6/M8 is also included. The first charge pump circuit is a medium-voltage MOS tube boosting charge pump.
In this embodiment, the circuit is composed of one CELL1 unit and two CELL2 units, wherein the voltage of VH1 is equal to 2×vci, the voltage of vh2 is equal to 4×vci, and when the signal levels of CK2P and CK2N in fig. 5 are in the range of 0 to VH1, the voltage of VH3 is equal to 6×vci. The same effect is achieved as in fig. 3 and 4. In fig. 5, the gate voltages of the switching transistors M1/M2/M3 range from 0 to VCI, and the gate voltages of the switching transistors M4/M5/M7 range from 0 to VH 1. The gate voltage ranges of M6 and M8 can only be controlled between VH1 to VH2 in order not to cause an overvoltage problem, so the gate control signal of the switching transistor M6/M8 cannot be realized by level_shift. CELL1 units may act as level_shift, VH1 and VH2 in fig. 6, connected to VH1 and VH2 in fig. 5. The CK2P and CK2N are signals with the level of 0 to VH1 after level_shift conversion, so that the level ranges of the gate control signals ck2p_vh1_vh2 and ck2n_vh1_vh2 of the switching transistors M6/M8 are VH1 to VH2, the difference is only 2×vci, and the overvoltage problem does not occur.
The common technical feature of the first to third embodiments is that the charge pump circuits are parallel, in the first to second embodiments, the first charge pump circuit is cascaded, and in the third embodiment, the second charge pump circuit is cascaded.
The invention adopts a parallel structure of double charge pumps, and can be raised to higher voltage without cascading more charge pump circuits.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.
Claims (6)
1. The utility model provides a parallel boost circuit of two charge pumps which characterized in that: the voltage boosting circuit comprises two cascaded first charge pump circuits, wherein the input end of a first charge pump circuit is provided with a second charge pump circuit, the second charge pump circuit comprises four switching tubes M5-M8, the switching tube M5 is connected with a switching tube M6 through a capacitor C2P, the common end of the switching tube M5 and the capacitor C2P is connected with a switching tube M7, the common end of the switching tube M6 and the capacitor C2P is connected with a switching tube M8, the switching tubes M6 and M7 are both connected with a level VCI, the switching tube M5 is connected with a level VSSA, the output end of the switching tube M8 is connected with a voltage stabilizing capacitor C2, and the voltage stabilizing capacitor C2 outputs a voltage boosting voltage to one first charge pump circuit;
the first charge pump circuit comprises switching tubes M1-M4, the voltage stabilizing capacitor C2 is respectively connected with the switching tubes M1 and M2, the switching tubes M1 are connected with the switching tubes M4 and the capacitor C1P, the switching tubes M2 are connected with the switching tubes M3 and the capacitor C1N, the switching tubes M3 are connected with the capacitor C1N, the switching tubes M4 are connected with the capacitor C1P, the input end of the capacitor C1P is connected with the control time sequence CK2P, the input end of the capacitor C1N is connected with the control time sequence CK2N, and the output ends of the switching tubes M3-M4 are connected with the voltage stabilizing capacitor to output stable boosting voltage.
2. The dual charge pump parallel boost circuit of claim 1, wherein: the number of the second charge pump circuits is 2, the two second charge pump circuits adopt mirror symmetry structures, and the output ends of the two second charge pump circuits are both connected with a voltage stabilizing capacitor C2.
3. The dual charge pump parallel boost circuit of claim 1, wherein: the control timings CK2N and CK2P are two-phase square waves.
4. The utility model provides a parallel boost circuit of two charge pumps which characterized in that: the charge pump circuit comprises a first charge pump circuit and two second charge pump circuits, wherein one second charge pump circuit comprises switching tubes M1-M4, the other second charge pump circuit comprises switching tubes M5-M8, the switching tube M1 is connected with a switching tube M2 through a capacitor C1, the common end of the switching tube M1 and the capacitor C1 is connected with a switching tube M3, the common end of the switching tube M2 and the capacitor C1 is connected with a switching tube M4, the switching tubes M2 and M3 are both connected with a level VCI, the switching tube M1 is connected with a level VSSA, the output end of the switching tube M4 is connected with a voltage stabilizing capacitor C11, and the voltage stabilizing capacitor C11 is connected with a switching tube M7; the switching tube M7 is connected with the switching tube M8 through the capacitor C2, the public end of the switching tube M7 and the capacitor C2 is connected with the switching tube M5, the switching tube M5 is connected with the level VSSA, the public end of the switching tube M8 and the capacitor C2 is connected with the switching tube M6, the output end of the switching tube M8 is connected with the voltage stabilizing capacitor C22, the output end of the voltage stabilizing capacitor C22 is connected with the first charge pump circuit, and the first charge pump circuit outputs the boosting level;
the first charge pump circuit comprises switching tubes M1-M4, the voltage stabilizing capacitor C2 is respectively connected with the switching tubes M1 and M2, the switching tubes M1 are connected with the switching tubes M4 and the capacitor C1P, the switching tubes M2 are connected with the switching tubes M3 and the capacitor C1N, the switching tubes M3 are connected with the capacitor C1N, the switching tubes M4 are connected with the capacitor C1P, the input end of the capacitor C1P is connected with the control time sequence CK2P, the input end of the capacitor C1N is connected with the control time sequence CK2N, and the output ends of the switching tubes M3-M4 are connected with the voltage stabilizing capacitor to output stable boosting voltage.
5. The dual charge pump parallel boost circuit of claim 4, wherein: a first charge pump circuit for providing a gate control signal to the switching transistor M6/M8 is also included.
6. The dual charge pump parallel boost circuit of claim 5, wherein: the first charge pump circuit is a medium-voltage MOS tube boost voltage charge pump.
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| CN201910601897.6A CN110401343B (en) | 2019-07-05 | 2019-07-05 | Dual charge pump parallel boost circuit |
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| CN201910601897.6A CN110401343B (en) | 2019-07-05 | 2019-07-05 | Dual charge pump parallel boost circuit |
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| CN110401343B true CN110401343B (en) | 2024-04-02 |
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