CN113763862B - GOA circuit and display device - Google Patents
GOA circuit and display device Download PDFInfo
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- CN113763862B CN113763862B CN202111120672.2A CN202111120672A CN113763862B CN 113763862 B CN113763862 B CN 113763862B CN 202111120672 A CN202111120672 A CN 202111120672A CN 113763862 B CN113763862 B CN 113763862B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The invention discloses a GOA circuit and a display device. According to the invention, the input end of the inverting module, the control end of the eleventh switching tube and the first end of the thirteenth switching tube are connected to the second node (Q), the second end of the first storage capacitor is connected to the output end of the GOA unit circuit, when the potential of the second node (Q) rises, the level transmission signal output by the output end of the GOA unit circuit is high level and is inverted with the level transmission signal of the next GOA unit circuit, and the design can solve the problems that the inverter in the prior art has a high-low level direct current channel in a specific working time and affects the stability of the GOA unit circuit.
Description
Technical Field
The invention relates to the technical field of display panels, in particular to a GOA circuit and a display device.
Background
With the increasing tastes of people, high requirements are also put on the specifications of the panel, such as high refresh rate, high resolution, long service life, etc. The gate drive (Gate Driveron Array, abbreviated as GOA) technology of the array substrate has great advantages in cost and functionality compared with the Chip On Film (COF), so that the technology becomes an important direction for development of various panel factories, such as panel giant LG, samsung and the like. The existing mainstream GOA technologies all use inverter modules, such as darlington inverters and pandas inverters, and both inverters have high and low level dc channels at specific working time, so that stability of the GOA circuit is affected.
In view of the foregoing, it is desirable to provide a GOA circuit to solve the above-mentioned problems.
Disclosure of Invention
The embodiment of the invention provides a GOA circuit and a display device, which effectively solve the problems that inverters in the prior art have high-low level direct current channels in specific working time and influence the stability of the GOA circuit.
According to an aspect of the present invention, there is provided a GOA circuit including a plurality of GOA unit circuits connected in cascade, n being an integer, and an nth stage GOA unit circuit including: the device comprises a pull-up module, a second pull-down module, a first pull-down module, a pull-up control module, an inversion module, a first storage capacitor, an eleventh switching tube, a twelfth switching tube and a thirteenth switching tube; the pull-up module is used for accessing a clock signal and is connected with the first end and the second end of the first capacitor; the second pull-down module is connected with the pull-up module; the first pull-down module is connected with the phase inversion module and is used for receiving a level transmission signal of a next-level GOA unit circuit; the inversion module and the second pull-down module are connected to a third node (QB), and the inversion module is used for receiving the first level signal, the second level signal and the level transmission signal of the next-level GOA unit circuit; the pull-up control module is used for receiving a level transmission signal of a circuit of a GOA unit of a previous stage except for the first GOA unit of the first stage, and the pull-up control module, the second end of the eleventh switching tube, the first end of the twelfth switching tube and the first pull-down module are all connected to a first node (N); the control end of the twelve switching tubes and the inverting module are connected to a fourth node (K), and the input end of the inverting module, the control end of the eleventh switching tube and the first end of the thirteenth switching tube are connected to a second node (Q); the second end of the first storage capacitor is connected with the output end of the GOA unit circuit; when the potential of the second node (Q) is raised, the level transmission signal output by the output end of the GOA unit circuit is high level, and the level transmission signal of the GOA unit circuit at the next stage is opposite to that of the level transmission signal of the GOA unit circuit at the next stage.
Further, the pull-up control module includes: a first switching tube and a second switching tube; wherein the second end of the first switching tube and the first end of the second switching tube are connected to the first node (N); the second end of the second switching tube, the control end of the eleventh switching tube and the first end of the thirteenth switching tube are connected; the control ends of the first switching tube and the second switching tube both receive the level transmission signal of the upper-stage GOA unit circuit, and the first end of the first switching tube receives the level transmission signal of the upper-stage GOA unit circuit.
Further, the pull-up module comprises a third switching tube; the first end of the third switching tube receives a clock signal, the second end of the third switching tube, the second end of the first storage capacitor and the output end of the GOA unit circuit are connected, and the control end of the third switching tube and the first end of the first storage capacitor are connected to a second node (Q).
Further, the first pull-down module comprises a fifth switching tube and a sixth switching tube; the control ends of the fifth switching tube and the sixth switching tube receive the level transmission signal of the next-stage GOA unit circuit, the first end of the fifth switching tube and the second end of the sixth switching tube are connected to the first node (N), and the first end of the sixth switching tube receives the first level signal.
Further, the second pull-down module includes: a fourth switching tube; the first end of the fourth switching tube is connected with the output end of the GOA unit circuit, the second end of the fourth switching tube and the second end of the second storage capacitor receive a first level signal, and the control end of the fourth switching tube and the first end of the second storage capacitor are connected to a third node (QB).
Further, the inverting module includes: a seventh switching tube, an eighth switching tube, a ninth switching tube and a tenth switching tube; the first end of the seventh switching tube and the first end of the eighth switching tube receive a second level signal, the second end of the seventh switching tube, the control end of the eighth switching tube and the second end of the tenth switching tube are all connected to a third node (QB), and the control end of the seventh switching tube receives a level transmission signal of a next-stage GOA unit circuit; the second end of the eighth switching tube, the first end of the ninth switching tube and the first end of the tenth switching tube are all connected to a fourth node (K).
Further, in the first stage, the level transmission signal of the upper-stage GOA unit circuit, the level transmission signal output by the output end of the GOA unit circuit and the level transmission signal of the lower-stage GOA unit circuit are all low levels; in the second stage, the level transmission signal of the upper-stage GOA unit circuit is high level, so that the first node (N) and the second node (Q) are high level, and the third node (QB) and the fourth node (K) are low level; in the third stage, the clock signal and the level transmission signal output by the output end of the GOA unit circuit are high level, and the voltage value of the second node (Q) is larger than that of the second node (Q) in the second stage; in the fourth stage, the level signal of the next-stage GOA unit circuit is at a high level, so that the third node (QB) and the fourth node (K) are at a high level, the first node (N) and the second node (Q) are at a low level, and the level signal output by the output end of the GOA unit circuit becomes at a low level.
Further, the duty cycle of the clock signal is 50%.
Further, the first to thirteenth switching transistors are N-type MOS transistors or P-type MOS transistors.
According to another aspect of the present invention, an embodiment of the present invention provides a display device, including a GOA circuit according to any one of the embodiments of the present invention.
The invention has the advantages that the input end of the inverting module, the control end of the eleventh switching tube and the first end of the thirteenth switching tube are connected to the second node (Q), the second end of the first storage capacitor is connected with the output end of the GOA unit circuit, when the potential of the second node (Q) rises, the level transmission signal output by the output end of the GOA unit circuit is high level and is opposite to the level transmission signal of the next GOA unit circuit, and the design can solve the problems that the inverter in the prior art has a direct current channel with high and low levels in specific working time and has influence on the stability of the GOA unit circuit.
Drawings
The technical solution and other advantageous effects of the present invention will be made apparent by the following detailed description of the specific embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a GOA circuit according to an embodiment of the present invention.
Fig. 2 is a timing diagram of a GOA circuit according to a first embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a display device according to a second embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
Fig. 1 is a schematic diagram of a GOA circuit according to a first embodiment of the present invention. Setting n as a positive integer. The nth stage GOA cell circuit includes: the pull-up control module 10, the pull-up module 20, the first pull-down module 30, the second pull-down module 40, the inverting module 50, the first storage capacitor C1, the eleventh switching tube T61, the twelfth switching tube T62, and the thirteenth switching tube T71.
The pull-up module 20 is used for accessing a clock signal, and is connected to a first end and a second end of the first capacitor C1.
The second pull-down module 40 is connected to the pull-up module 20.
The first pull-down module 30 is connected to the inverting module 50, and the first pull-down module 30 is configured to receive the level transmission signal sn+1 of the next-stage GOA unit circuit.
The inverting module 50 and the second pull-down module 40 are connected to a third node (QB). The inverting module 50 is configured to receive the first level signal, the second level signal, and the level signal sn+1 of the next GOA unit circuit.
The pull-up control module 10 is configured to receive the cascade signal Sn-1 of the previous stage GOA unit circuit, except for the first stage GOA unit. The pull-up control module 10, the second end of the eleventh switching tube T61, the first end of the twelfth switching tube T62, and the first pull-down module 30 are all connected to a first node (N).
The control terminal of the twelve switching tube T62 and the inverting module 50 are connected to a fourth node (K), and the input terminal of the inverting module 50, the control terminal of the eleventh switching tube T61 and the first terminal of the thirteenth switching tube T71 are connected to a second node (Q). The second end of the first storage capacitor C1 is connected with the output end of the GOA unit circuit; when the potential of the second node (Q) is raised, the level transmission signal Sn output by the output end of the GOA unit circuit is high level, and is opposite to the level transmission signal Sn+1 of the next GOA unit circuit.
When the level signal Sn output from the output terminal of the GOA unit circuit is at a high level, the level signal sn+1 of the next GOA unit circuit is at a low level. After this stage, when the level signal Sn output from the output terminal of the GOA unit circuit becomes low level, the level signal sn+1 of the next GOA unit circuit becomes high level.
The GOA unit circuit will be further described below.
Illustratively, the pull-up control module 10 includes: a first switching tube T11 and a second switching tube T12. The second end of the first switching tube T11 and the first end of the second switching tube T12 are connected to the first node (N). The second end of the second switching tube T12, the control end of the eleventh switching tube T61, and the first end of the thirteenth switching tube T71 are connected. Since the control terminal of the thirteenth switching tube T71 receives the second level signal (VGH here), the control terminal of the eleventh switching tube T61 and the first terminal of the thirteenth switching tube T71 are connected to the second node (Q). The control ends of the first switching tube T11 and the second switching tube T12 both receive the level transmission signal Sn-1 of the upper-stage GOA unit circuit, and the first end of the first switching tube T11 receives the level transmission signal Sn-1 of the upper-stage GOA unit circuit. The pull-up control module 10 is configured to charge a first node (N).
Illustratively, the pull-up module 20 includes a third switching tube T21. The first end of the third switching tube T21 receives a clock signal. The second end of the third switching tube T21, the second end of the first storage capacitor C1 and the output end of the GOA unit circuit are connected. The output end of the GOA unit circuit outputs a stage signal Sn. The control terminal of the third switching tube T21 and the first terminal of the first storage capacitor C1 are connected to a second node (Q). The pull-up module 20 is configured to change the level of the output signal of the output terminal of the GOA unit circuit to a high level in the third stage. The third stage will be explained further below.
Illustratively, the first pull-down module 30 includes a fifth switching tube T41 and a sixth switching tube T42. And the control ends of the fifth switching tube T41 and the sixth switching tube T42 receive a level transmission signal Sn+1 of the next-stage GOA unit circuit. The first end of the fifth switching tube T41 and the second end of the sixth switching tube T42 are connected to a first node (N). The first terminal of the sixth switching tube T42 receives the first level signal. In this embodiment, the first level signal is VGL (i.e., low level). The first pull-down module 30 is configured to pull the first node (N) low.
Illustratively, the second pulldown module 40 comprises: fourth switching tube T31. And a first end of the fourth switching tube T31 is connected with the output end of the GOA unit circuit. The second end of the fourth switching tube T31 and the second end of the second storage capacitor C2 receive the first level signal. In this embodiment, the first level signal is VGL (i.e., low level). The control terminal of the fourth switching tube T31 and the first terminal of the second storage capacitor C2 are connected to a third node (QB). The second pull-down module 40 is for pulling the third node (QB) to a low level.
Illustratively, the inverting module 50 includes: a seventh switching tube T43, an eighth switching tube T44, a ninth switching tube T51, and a tenth switching tube T52. The first terminal of the seventh switching tube T43 and the first terminal of the eighth switching tube T44 receive the second level signal. In this embodiment, the second level signal is VGH (i.e., high level). The second end of the seventh switching tube T43, the control end of the eighth switching tube T44, and the second end of the tenth switching tube T52 are all connected to a third node (QB). The control end of the seventh switching tube T43 receives the level transmission signal Sn+1 of the next-level GOA unit circuit. The second end of the eighth switching tube T44, the first end of the ninth switching tube T51 and the first end of the tenth switching tube T52 are all connected to a fourth node (K).
Referring to fig. 2 in combination, based on the GOA circuit described above, the operation of the GOA circuit will be further described below. In the first stage, the level transmission signal Sn-1 of the upper-stage GOA unit circuit, the level transmission signal Sn output by the output end of the GOA unit circuit and the level transmission signal Sn+1 of the lower-stage GOA unit circuit are all low levels.
In the second stage, the level transmission signal Sn-1 of the upper GOA unit circuit is high level, so that the first node (N) and the second node (Q) are high level, and the third node (QB) and the fourth node (K) are low level. Further, in the second stage, when the level of the pass signal Sn-1 of the upper GOA unit circuit is high, the first switching tube T11 and the second switching tube T12 are turned on. Then, the second node (Q) writes a high level, so that the eleventh, ninth, and tenth switching transistors T61, T51, and T52 are turned on, and the potentials of the third and fourth nodes (QB, K) are pulled down, and the potential of the first node (N) is pulled up to a high level. Thus, the third switching tube T21 is turned on, and the twelfth switching tube T62 and the fourth switching tube T31 are turned off. Then, when the potential of the gradation signal Sn-1 of the upper-stage GOA unit circuit is pulled down, the first and second switching transistors T11 and T12 are turned off, and at this stage, the first and second nodes (N) and (Q) remain high, and the third and sixth switching transistors T21 and T42 are completely turned off.
In the third stage, the clock signal and the level transmission signal Sn output by the output end of the GOA unit circuit are at high level, and the voltage value of the second node (Q) is greater than the voltage value of the second node (Q) in the second stage. Further, in the third stage, the clock signal is at a high level, the output terminal of the GOA unit circuit is at a high level (it is to be noted that the high level of the output terminal refers to the high level of the level signal outputted by the output terminal), and after the high level is outputted, the level signal of the GOA unit circuit is pulled down to a low level by the clock signal. At this stage, due to the coupling action of the first capacitor (i.e., the voltage across the first capacitor C1 cannot be suddenly changed), the potential of the second node (Q) will rise to a higher level, and the third switching tube T21 is fully turned on.
In the fourth stage, the level transmission signal sn+1 of the next-stage GOA unit circuit is at a high level, so that the third node (QB) and the fourth node (K) are at a high level, the first node (N) and the second node (Q) are at a low level, and the level transmission signal output by the output end of the GOA unit circuit becomes at a low level. Further, in the fourth stage, the gradation signal sn+1 of the next-stage GOA unit circuit is at a high level, and thus the fifth switching tube T41, the sixth switching tube T42, and the seventh switching tube T43 are made conductive, the potentials of the second node (Q) and the first node (N) are pulled down, and the third switching tube T21, the ninth switching tube T51, the tenth switching tube T52, and the eleventh switching tube T61 are made conductive. When the potential of the third node (QB) is raised, the eighth switching transistor T44 is turned on, and the potential of the fourth node (K) is pulled up, the twelfth switching transistor T62 is turned on, and the first node (N) is kept at a low level. Therefore, the level of the gradation signal Sn outputted from the output terminal of the GOA unit circuit remains low until the output of the next frame signal.
In the above embodiment, the duty ratio of the clock signal is 50%.
Note that the first switching tube T11, the second switching tube T12, the third switching tube T21, the fourth switching tube T31, the fifth switching tube T41, the sixth switching tube T42, the seventh switching tube T43, the eighth switching tube T44, the ninth switching tube T51, the tenth switching tube T52, the eleventh switching tube T61, the twelfth switching tube T62, and the thirteenth switching tube T71 may be N-type MOS tubes or P-type MOS tubes.
In the first embodiment of the invention, the input end of the inverting module, the control end of the eleventh switching tube and the first end of the thirteenth switching tube are connected to the second node (Q), and the second end of the first storage capacitor is connected to the output end of the GOA unit circuit, so that when the potential of the second node (Q) rises, the level signal output by the output end of the GOA unit circuit is high level and is inverted to the level signal of the next GOA unit circuit.
Fig. 3 is a schematic structural diagram of a display device according to a second embodiment of the present invention, and the display device 200 includes the GOA circuit 100 according to the embodiment of the present invention. The display device 200 may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
In summary, although the present invention has been described in terms of the preferred embodiments, the preferred embodiments are not limited to the above embodiments, and various modifications and changes can be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention is defined by the appended claims.
Claims (10)
1. A GOA circuit comprising a plurality of GOA unit circuits in cascade, wherein n is a positive integer, and the nth stage GOA unit circuit comprises: the device comprises a pull-up module, a second pull-down module, a first pull-down module, a pull-up control module, an inversion module, a first storage capacitor, an eleventh switching tube, a twelfth switching tube and a thirteenth switching tube;
the pull-up module is used for accessing a clock signal and is connected with a first end and a second end of the first storage capacitor;
the second pull-down module is connected with the pull-up module;
the first pull-down module is connected with the phase inversion module and is used for receiving a level transmission signal of a next-level GOA unit circuit;
the inversion module and the second pull-down module are connected to a third node (QB), and the inversion module is used for receiving the first level signal, the second level signal and the level transmission signal of the next-level GOA unit circuit;
the pull-up control module is used for receiving a level transmission signal of a circuit of a GOA unit of a previous stage except for the first GOA unit of the first stage, and the pull-up control module, the second end of the eleventh switching tube, the first end of the twelfth switching tube and the first pull-down module are all connected to a first node (N);
the control end of the twelve switching tubes and the inverting module are connected to a fourth node (K), and the input end of the inverting module, the control end of the eleventh switching tube and the first end of the thirteenth switching tube are connected to a second node (Q); the second end of the first storage capacitor is connected with the output end of the GOA unit circuit; when the potential of the second node (Q) is raised, the level transmission signal output by the output end of the GOA unit circuit is high level, and the level transmission signal of the GOA unit circuit at the next stage is opposite to that of the level transmission signal of the GOA unit circuit at the next stage.
2. The GOA circuit of claim 1, wherein the pull-up control module comprises: a first switching tube and a second switching tube;
wherein the second end of the first switching tube and the first end of the second switching tube are connected to the first node (N);
the second end of the second switching tube, the control end of the eleventh switching tube and the first end of the thirteenth switching tube are connected;
the control ends of the first switching tube and the second switching tube both receive the level transmission signal of the upper-stage GOA unit circuit, and the first end of the first switching tube receives the level transmission signal of the upper-stage GOA unit circuit.
3. The GOA circuit of claim 1, wherein the pull-up module comprises a third switching tube;
the first end of the third switching tube receives a clock signal, the second end of the third switching tube, the second end of the first storage capacitor and the output end of the GOA unit circuit are connected, and the control end of the third switching tube and the first end of the first storage capacitor are connected to a second node (Q).
4. The GOA circuit of claim 1, wherein the first pull-down module comprises a fifth switching tube and a sixth switching tube;
the control ends of the fifth switching tube and the sixth switching tube receive the level transmission signal of the next-stage GOA unit circuit, the first end of the fifth switching tube and the second end of the sixth switching tube are connected to the first node (N), and the first end of the sixth switching tube receives the first level signal.
5. The GOA circuit of claim 1, wherein the second pull-down module comprises: a fourth switching tube; the GOA circuit further comprises a second storage capacitor;
the first end of the fourth switching tube is connected with the output end of the GOA unit circuit, the second end of the fourth switching tube and the second end of the second storage capacitor receive a first level signal, and the control end of the fourth switching tube and the first end of the second storage capacitor are connected to a third node (QB).
6. The GOA circuit of claim 1, wherein the inverting module comprises: a seventh switching tube, an eighth switching tube, a ninth switching tube and a tenth switching tube;
the first end of the seventh switching tube and the first end of the eighth switching tube receive a second level signal, the second end of the seventh switching tube, the control end of the eighth switching tube and the second end of the tenth switching tube are all connected to a third node (QB), and the control end of the seventh switching tube receives a level transmission signal of a next-stage GOA unit circuit;
the second end of the eighth switching tube, the first end of the ninth switching tube and the first end of the tenth switching tube are all connected to a fourth node (K).
7. The GOA circuit as claimed in claim 1, wherein in the first stage, the level signal of the previous GOA unit circuit, the level signal output from the output terminal of the GOA unit circuit, and the level signal of the next GOA unit circuit are all low levels;
in the second stage, the level transmission signal of the upper-stage GOA unit circuit is high level, so that the first node (N) and the second node (Q) are high level, and the third node (QB) and the fourth node (K) are low level;
in the third stage, the clock signal and the level transmission signal output by the output end of the GOA unit circuit are high level, and the voltage value of the second node (Q) is larger than that of the second node (Q) in the second stage;
in the fourth stage, the level signal of the next-stage GOA unit circuit is at a high level, so that the third node (QB) and the fourth node (K) are at a high level, the first node (N) and the second node (Q) are at a low level, and the level signal output by the output end of the GOA unit circuit becomes at a low level.
8. The GOA circuit of claim 1, wherein the duty cycle of the clock signal is 50%.
9. The GOA circuit of any of claims 1-8, wherein the first through thirteenth switching transistors are N-type MOS transistors or P-type MOS transistors.
10. A display device comprising a GOA circuit as claimed in any one of claims 1 to 9.
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| CN202111120672.2A CN113763862B (en) | 2021-09-24 | 2021-09-24 | GOA circuit and display device |
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| CN202111120672.2A CN113763862B (en) | 2021-09-24 | 2021-09-24 | GOA circuit and display device |
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| CN113763862B true CN113763862B (en) | 2023-09-26 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102779479A (en) * | 2012-08-17 | 2012-11-14 | 开源集成电路(苏州)有限公司 | LED (light-emitting diode) display system |
| CN104409056A (en) * | 2014-11-14 | 2015-03-11 | 深圳市华星光电技术有限公司 | Scanning drive circuit |
| CN106601208A (en) * | 2017-03-01 | 2017-04-26 | 北京京东方光电科技有限公司 | Shift register unit, driving method thereof, grid drive circuit and display device |
| CN108122529A (en) * | 2018-01-25 | 2018-06-05 | 京东方科技集团股份有限公司 | Drive element of the grid and its driving method and gate driving circuit |
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2021
- 2021-09-24 CN CN202111120672.2A patent/CN113763862B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102779479A (en) * | 2012-08-17 | 2012-11-14 | 开源集成电路(苏州)有限公司 | LED (light-emitting diode) display system |
| CN104409056A (en) * | 2014-11-14 | 2015-03-11 | 深圳市华星光电技术有限公司 | Scanning drive circuit |
| CN106601208A (en) * | 2017-03-01 | 2017-04-26 | 北京京东方光电科技有限公司 | Shift register unit, driving method thereof, grid drive circuit and display device |
| CN108122529A (en) * | 2018-01-25 | 2018-06-05 | 京东方科技集团股份有限公司 | Drive element of the grid and its driving method and gate driving circuit |
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