CN113380172B - Gate drive circuit, drive method and GOA circuit - Google Patents
Gate drive circuit, drive method and GOA circuit Download PDFInfo
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- CN113380172B CN113380172B CN202110632363.7A CN202110632363A CN113380172B CN 113380172 B CN113380172 B CN 113380172B CN 202110632363 A CN202110632363 A CN 202110632363A CN 113380172 B CN113380172 B CN 113380172B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
Abstract
The invention discloses a gate driving circuit, a driving method and a GOA circuit, which are used for reducing the number of control signals and reducing power consumption. The grid driving circuit comprises a forward signal generating unit and a reverse signal generating unit which are electrically connected; the forward signal generating unit outputs a forward signal having a first level, and the reverse signal generating unit outputs a reverse signal having a second level. The forward signal generating unit outputs a forward signal having a second level, and the reverse signal generating unit outputs a reverse signal having a first level and a second level distributed in time series. The forward signal generating unit outputs a forward signal having a first level, and the reverse signal generating unit outputs a reverse signal having a second level. The forward signal generating unit outputs a forward signal having a first level, and the reverse signal generating unit outputs a reverse signal having a second level. The driving method applies a gate driving circuit. The GOA circuit comprises a gate driving circuit.
Description
Technical Field
The invention relates to the technical field of display, in particular to a gate driving circuit, a driving method and a GOA circuit.
Background
In the pixel unit driving circuit, due to the instability of the low-temperature polysilicon transistor device (e.g. voltage drift, etc.), the pixel unit driving circuit needs to be compensated internally. However, in the pixel unit driving circuit, the control signal required by the pixel unit driving circuit is inverted to the light emission control signal in the compensation stage and the light emission stage. Therefore, in practical applications, two GOA circuits are required to generate the inverted control signal and the light-emitting control signal, respectively, so as to control the pixel unit driving circuit. However, the two GOA circuits consume large power and cause the display device to be unstable and easily receive crosstalk between signals.
Disclosure of Invention
The invention aims to provide a gate driving circuit, a driving method and a GOA circuit, which are used for solving the technical problems that two GOA circuits in the prior art are large in power consumption, unstable in circuit and prone to crosstalk between adjacent signals.
In a first aspect, the present invention provides a gate driving circuit, including: and the forward signal generating unit and the reverse signal generating unit are electrically connected. The forward signal generating unit is used for outputting a forward signal, and the reverse signal generating unit is used for outputting a reverse signal. The pulse width of the forward signal is not equal to the pulse width of the reverse signal.
In a signal input stage, the forward signal generation unit outputs a forward signal having a first level, and the reverse signal generation unit outputs a reverse signal having a second level.
In a level bootstrap stage, the forward signal generation unit outputs a forward signal having a second level, and the reverse signal generation unit outputs a reverse signal having a first level and a second level distributed in time sequence.
In the signal reset phase, the forward signal generation unit outputs a forward signal having a first level, and the reverse signal generation unit outputs a reverse signal having a second level.
In the level holding stage, the forward signal generating unit outputs a forward signal having a first level, and the reverse signal generating unit outputs a reverse signal having a second level.
Compared with the prior art, the gate driving circuit provided by the invention comprises a forward signal generating unit and a reverse signal generating unit, wherein the forward signal generating unit is used for generating a forward signal, and the reverse signal generating unit is used for generating a reverse signal. Therefore, the gate driving circuit provided by the invention can completely meet the control signals of each driving tube and each light-emitting control tube in the display pixel unit driving circuit, and is favorable for realizing the design of a display driving panel with a narrow frame compared with two GOA circuits in the prior art. Meanwhile, the pulse width of the forward signal is not equal to that of the reverse signal, and in the practical application process, two gate driving circuits provided by the present invention can be adopted, and the control signal generated by one of the gate driving circuits and the light-emitting control signal opposite to the control signal are utilized to control the pixel unit driving circuit so as to drive the odd-numbered rows of the display device, and the control signal generated by the other gate driving circuit and the light-emitting control signal opposite to the control signal are utilized to control the pixel unit driving circuit to drive the even-numbered rows of the display device. Based on this, the driving signals for driving the odd lines and the even lines of the display device are not interfered with each other, and the display device can be further stabilized.
In a second aspect, the present invention provides a GOA circuit, which includes the gate driving circuit described in the first aspect.
Compared with the prior art, the beneficial effects of the GOA circuit provided by the invention are the same as those of the gate driving circuit described in the first aspect, and are not described herein again.
In a third aspect, the present invention further provides a driving method of a gate driving circuit, which applies the gate driving circuit described in the first aspect. The driving method of the gate driving circuit comprises the following steps:
and in the signal input stage, the forward signal generation unit is controlled to output a forward signal with a first level, and the reverse signal generation unit is controlled to output a reverse signal with a second level.
And in the level bootstrap stage, the forward signal generation unit is controlled to output a forward signal with a second level, and the reverse signal generation unit is controlled to sequentially output reverse signals with a first level and a second level.
And in the signal resetting stage, the forward signal generation unit is controlled to output a forward signal with a first level, and the reverse signal generation unit is controlled to output a reverse signal with a second level.
And in the level holding stage, the forward signal generation unit is controlled to output a forward signal with a first level, and the reverse signal generation unit is controlled to output a reverse signal with a second level.
Compared with the prior art, the beneficial effects of the driving method of the gate driving circuit provided by the invention are the same as those of the gate driving circuit described in the first aspect, and are not repeated here.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a circuit diagram of a gate driving circuit in the prior art;
FIG. 2 is a timing diagram of a gate driving circuit in the prior art;
fig. 3 is a circuit structure diagram of a gate driving circuit according to an embodiment of the invention;
fig. 4 is a timing diagram of a gate driving circuit according to an embodiment of the invention.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Fig. 1 illustrates a circuit configuration diagram of a gate driving circuit in the related art, and fig. 2 illustrates a timing diagram of the gate driving circuit in the related art. Referring to fig. 1, a gate driving circuit in the related art may be composed of 18N-type transistors. The signals for controlling the gate driving circuit include: 2 clock signals, 1 input signal and 5 control signals. Wherein, the 5 control signals are VGH, VGH1, VGL2 and VGL3 respectively.
Referring to fig. 1, a gate driving circuit in the related art may include 6 parts, which are a pull-up holding unit, a pull-up unit, a pull-down unit, an inverter unit, a pull-down holding unit, and a feedback unit, respectively. The pull-up holding unit is composed of transistors T11 to T1 and T41. The pull-up holding unit functions to operate the GOA circuit and make it output a signal having a low level. The pull-up unit is composed of transistors T22 and T23. The pull-up unit is used for level bootstrap and driving. The pull-down unit is composed of transistors T21 and T31 to T33. The pull-down unit functions to cut off the forward signal and output the reverse signal. The inverter unit is composed of transistors T51 to T54. The inverter unit functions to generate a voltage opposite to the node Q to control the pull-down unit. The pull-down holding unit is composed of transistors T42 to T45. The pull-down holding unit functions to make its output signal have a low level. The feedback unit is composed of a transistor T6. The feedback unit is used for providing a feedback signal so as to cut off a leakage path.
The gate driving circuit in the prior art has the following two problems:
1. the control signal quantity is more, and the whole panel consumption is great.
2. The circuit speed is slow, and the reverse signal rising edge is very big, influences the drive effect.
3. The display device is unstable and is susceptible to crosstalk between signals.
In order to solve the above technical problem, an embodiment of the present invention provides a gate driving circuit. Fig. 3 illustrates a circuit structure diagram of a gate driving circuit according to an embodiment of the present invention, and referring to fig. 3, the gate driving circuit according to the embodiment of the present invention includes: and the forward signal generating unit and the reverse signal generating unit are electrically connected. The forward signal generating unit is used for outputting a forward signal, the reverse signal generating unit is used for outputting a reverse signal, and the pulse width of the forward signal is not equal to that of the reverse signal. The output end of the forward signal generating unit and the output end of the reverse signal generating unit are electrically connected with the pixel unit driving circuit so as to provide a forward control signal and a reverse light-emitting control signal for the pixel unit driving circuit.
In a signal input stage, the forward signal generation unit outputs a forward signal having a first level, and the reverse signal generation unit outputs a reverse signal having a second level. In a level bootstrap stage, the forward signal generation unit outputs a forward signal having a second level, and the reverse signal generation unit outputs a reverse signal having a first level and a second level distributed in time sequence. In the signal reset phase, the forward signal generation unit outputs a forward signal having a first level, and the reverse signal generation unit outputs a reverse signal having a second level. In the level holding stage, the forward signal generating unit outputs a forward signal having a first level, and the reverse signal generating unit outputs a reverse signal having a second level.
It should be understood that the first level may be a high level or a low level, and the second level may be a low level or a high level. That is, when the first level is a high level, the second level is a low level. Similarly, when the first level is a low level, the second level is a high level.
Compared with the prior art, the gate driving circuit provided by the invention comprises a forward signal generating unit and a reverse signal generating unit, wherein the forward signal generating unit is used for generating a forward signal, and the reverse signal generating unit is used for generating a reverse signal. Therefore, the gate driving circuit provided by the invention can completely meet the control signals of each driving tube and light-emitting control tube in the unit driving circuit of the display pixel, and is beneficial to realizing the design of a display driving panel with a narrow frame compared with two GOA circuits in the prior art. Meanwhile, the pulse width of the forward signal is not equal to that of the backward signal, and in practical application, two gate driving circuits provided by the present invention may be used, wherein one gate driving circuit may generate a control signal and a light-emitting control signal opposite to the control signal, so as to control the pixel unit driving circuit to drive the odd-numbered rows of the display device, and the other gate driving circuit may also generate a control signal and a light-emitting control signal opposite to the control signal, so as to control the pixel unit driving circuit to drive the even-numbered rows of the display device. Based on this, the driving signals for driving the odd lines and the even lines of the display device are not interfered with each other, and the display device can be further stabilized.
Referring to fig. 3, the forward signal generating unit may include: the circuit comprises a forward input circuit, a first inverter circuit, a first level holding circuit, a first output circuit and a first capacitor C1. The control end of the forward input circuit is electrically connected with the first clock signal end, the input end of the forward input circuit is electrically connected with the input signal end, the output end of the forward input circuit, the control end of the first output circuit and one end of the first capacitor C1 are electrically connected with the first node Q, and the output end of the forward input circuit is electrically connected with the first inverter circuit. The output terminal of the first inverter circuit and the first level holding circuit are electrically connected to the second node QB. The first level holding circuit is electrically connected with the output end of the forward input circuit, the output end of the first output circuit and the other end of the first capacitor C1 respectively, and the input end of the first level holding circuit is electrically connected with the first control signal end. The input end of the first output circuit is electrically connected with the third clock signal end.
Referring to fig. 3, the first inverter circuit may include: a first switch circuit and a second switch circuit. The control end of the first switch circuit is electrically connected with the first clock signal end, the input end of the first switch circuit is electrically connected with the second control signal end, and the output end of the first switch circuit is electrically connected with the second node QB. The control end of the second switch circuit is electrically connected with the output end of the positive input circuit, the input end of the second switch circuit is electrically connected with the first clock signal end, and the output end of the second switch circuit is electrically connected with the second node QB.
Referring to fig. 3, the first level holding circuit may include: a third switch circuit, a fourth switch circuit and a fifth switch circuit. The control end of the third switching circuit is electrically connected with the third clock signal end, the input end of the third switching circuit is electrically connected with the output end of the forward input circuit, and the output end of the third switching circuit is electrically connected with the output end of the fourth switching circuit. A control terminal of the fourth switching circuit is electrically connected to the second node QB, and an input terminal of the fourth switching circuit is electrically connected to the first control signal terminal. The control end of the fifth switch circuit is electrically connected to the second node QB, the input end of the fifth switch circuit is electrically connected to the first control signal end, and the output end of the fifth switch circuit is electrically connected to the other end of the first capacitor C1 and the output end of the first output circuit, respectively.
Referring to fig. 3, the forward signal generating unit may further include: an electric leakage protection circuit. The input end of the leakage protection circuit is electrically connected with the output end of the forward input circuit, the output end of the leakage protection circuit is electrically connected with the first node Q, and the control end of the leakage protection circuit is electrically connected with the second control signal end.
Referring to fig. 3, the inverse signal generating unit may include: the circuit comprises an inverting input circuit, a reset circuit, a second inverting circuit, a second level holding circuit and a second output circuit. The control end of the reverse input circuit is electrically connected with the output end of the first output circuit, the input end of the reverse input circuit is electrically connected with the second control signal end, and the output end of the reverse input circuit is electrically connected with the control end of the second output circuit and the output end of the reset circuit respectively. The control end of the reset circuit is electrically connected with the first clock signal end, and the input end of the reset circuit is electrically connected with the first control signal end. The control end of the second level holding circuit is electrically connected with the second inverter circuit, the input end of the second level holding circuit is electrically connected with the second control signal end, and the output end of the second level holding circuit is electrically connected with the output end of the second output circuit. The input end of the second output circuit is electrically connected with the fourth clock signal end.
Referring to fig. 3, the second inverter circuit includes: a sixth switching circuit, a seventh switching circuit, an eighth switching circuit, and a ninth switching circuit. The control end and the input end of the sixth switching circuit are both electrically connected with the third control signal end, and the output end of the sixth switching circuit is electrically connected with the control end of the seventh switching circuit. The input end of the seventh switching circuit is electrically connected with the third control signal end, and the output end of the seventh switching circuit is electrically connected with the output end of the eighth switching circuit and the output end of the ninth switching circuit. The input end of the eighth switching circuit is electrically connected with the first control signal end, and the control end of the eighth switching circuit is electrically connected with the output end of the first output circuit. The input end of the ninth switching circuit is electrically connected with the first control signal end, and the control end of the ninth switching circuit is electrically connected with the output end of the first output circuit.
Referring to fig. 3, the above-described reverse signal generating unit may further include a second capacitor C2. One end of the second capacitor C2 is electrically connected to the output end of the eighth switch circuit, and the other end of the second capacitor is electrically connected to the control end of the second output circuit. The second capacitor C2 may make the reverse signal generating unit more stable.
It should be understood that the forward input circuit, the first inverter circuit, the first level holding circuit, the first output circuit, the leakage protection circuit, the reverse input circuit, the reset circuit, the second inverter circuit, the second level holding circuit, and the second output circuit may be formed of transistors. All transistors can be N-type transistors or P-type transistors. That is, the gate driving circuit provided by the embodiment of the present invention is composed of a single-type transistor. The following description will be given taking as an example that all the transistors are P-type transistors.
Referring to fig. 3, the gate driving circuit according to the embodiment of the present invention may include 2 capacitors and 16P-type tfts. The whole circuit can be divided into two parts, wherein the first part is a traditional GOA part, namely a forward signal generating unit; the second part is a reverse gate driving signal generating part, i.e., a reverse signal generating unit. The first portion may be composed of 8 tfts and a capacitor C1, and the second portion may be composed of 8 tfts and a capacitor C2. The thin film transistor can be a TFT transistor or an IGZO transistor or an OTFT transistor, etc. Wherein the content of the first and second substances,
the forward input circuit includes a thin film transistor T1, the first switch circuit includes a thin film transistor T2, the second switch circuit includes a thin film transistor T3, the third switch circuit includes a thin film transistor T4, the fourth switch circuit includes a thin film transistor T5, the fifth switch circuit includes a thin film transistor T8, the leakage protection circuit includes a thin film transistor T6, the first output circuit includes a thin film transistor T7, the reverse input circuit includes a thin film transistor T9, the reset circuit includes a thin film transistor T10, the sixth switch circuit includes a thin film transistor T11, the seventh switch circuit includes a thin film transistor T12, the eighth switch circuit includes a thin film transistor T13, the ninth switch circuit includes a thin film transistor T14, the second level holding circuit includes a thin film transistor T16, and the second output circuit includes a thin film transistor T15.
Referring to fig. 3, the gate driving circuit according to the embodiment of the present invention may include 4 clock signals, 3 control signals, and 1 input signal. Wherein, 4 clock signals are respectively: CK1, CK2, CK3 and CK4. The 3 control signals are respectively: VGH, VGL, and VGL1. The first clock signal terminal is configured to output a first clock signal CK1, the second clock signal terminal is configured to output a second clock signal CK2, the third clock signal terminal is configured to output a third clock signal CK3, and the fourth clock signal terminal is configured to output a fourth clock signal CK4. The first control signal terminal is configured to output a first control signal VGH, the second control signal terminal is configured to output a second control signal VGL, and the third control signal terminal is configured to output a third control signal VGL1.
Fig. 4 illustrates a timing diagram of a gate driving circuit according to an embodiment of the present invention. Referring to fig. 4, the first control signal terminal always outputs the first control signal VGH having a high level, the second control signal terminal always outputs the second control signal VGL having a low level, and the third control signal terminal always outputs the third control signal VGL1 having a low level.
Referring to fig. 4, in the signal input stage, the first clock signal terminal has a low level, the second clock signal terminal has a high level and a low level distributed according to a timing, the third clock signal terminal has a high level, the fourth clock signal terminal has a high level, and the input signal terminal has a low level. In the level bootstrap stage, the first clock signal terminal has a high level, the second clock signal terminal has a low level and a high level distributed according to a timing sequence, the third clock signal terminal has a low level, the fourth clock signal terminal has a high level and a low level distributed according to a timing sequence, and the input signal terminal has a high level. In the signal resetting stage, the first clock signal terminal has a low level, the second clock signal terminal has a high level and a low level distributed according to a time sequence, the third clock signal terminal has a high level, the fourth clock signal terminal has a low level and a high level distributed according to a time sequence, and the input signal terminal has a high level. In the level holding stage, the first clock signal terminal has a high level, the second clock signal terminal has a low level and a high level distributed according to a timing, the third clock signal terminal has a low level, the fourth clock signal terminal has a high level and a low level distributed according to a timing, and the input signal terminal has a high level.
Referring to fig. 4, the operation mode of the gate driving circuit provided by the embodiment of the present invention can be divided into the following 4 stages:
1. signal input stage
For the forward direction signal generating unit, the input signal has a low level, and the thin film transistor T1 is turned on, so that the level at the first node Q is a low level. Based on the level at the first node Q being low, the thin film transistor T3 and the thin film transistor T7 are turned on. When the thin film transistor T3 is turned on and the first clock signal CK1 is at a high level, the level at the second node QB is at a high level, so that the thin film transistors T5 and T8 are turned off. When the thin film transistor T7 is turned on and the third clock signal is at a high level, the level of the output node N of the first output circuit is at a high level.
As for the inversion signal generating unit, since the first clock signal CK1 is low level, the thin film transistor T10 is turned on, thereby turning off the thin film transistor T15. The second inverter circuit outputs a low level to turn on the thin film transistor T16, and the level of the output point R _ N of the second output circuit is at a low level.
As can be seen from the above description, in the signal input stage, the forward signal generating unit of the gate driving circuit provided by the present invention outputs the forward signal with high level, and the reverse signal generating unit outputs the reverse signal with low level.
2. Level bootstrapping phase
For the forward signal generating unit, the first node Q, i.e. the gate point of the thin film transistor T7, jumps to a lower voltage due to the capacitive coupling effect of the capacitor C1 to achieve better driving and a sufficiently fast speed. At this time, since the level of the third clock signal CK3 is low level, the level of the output point N of the first output circuit is low level.
For the inversion signal generating unit, since the first clock signal CK1 is changed from a low level to a high level and the level of the output point N of the first output circuit is a low level, the thin film transistors T9, T15, T13, and T14 are turned on, and the thin film transistors T10 and T16 are turned off. At this time, the level of the fourth clock signal CK4 is high, so that the level of the output point R _ N of the second output circuit is high and a low signal of a small section later.
The bootstrap change in the level bootstrap phase can be changed by increasing the number of clock signals without changing the circuit configuration.
As can be seen from the above description, in the signal input stage, the forward signal generating unit of the gate driving circuit provided in the present invention outputs the forward signal having the low level, and the reverse signal generating unit outputs the reverse signal having the high level and the low level distributed in time series.
3. Level reset phase
For the forward signal generating unit, the level of the first clock signal CK1 is low, the thin film transistors T1 and T2 are turned on, and the level of the input signal is high, so that the thin film transistors T7, T5, and T8 are turned on, at which time the level of the output point N of the first output circuit is high.
In the inversion signal generation unit, since the level of the output point N of the first output circuit is high, the thin film transistor T9 is turned off, the thin film transistor T10 is turned on, and the thin film transistor T16 is turned on, the level of the output point R _ N of the second output circuit is low.
As can be seen from the above description, in the signal input stage, the forward signal generating unit of the gate driving circuit provided by the present invention outputs the forward signal with high level, and the reverse signal generating unit outputs the reverse signal with low level.
4. Level holding phase
For the forward signal generating unit, the level of the first clock signal CK1 is at a high level, and the thin film transistors T1, T2, and T3 are turned off, thereby maintaining the level of the second node QB at a low level. The second node QB is low to turn on the thin film transistor T8, and the first control signal is high to make the output point N of the first output circuit high.
In the inversion signal generation unit, since the level of the output point N of the first output circuit is high, the thin film transistors T13 and T14 are turned off, and at this time, the second inverter circuit always outputs a level, so that the thin film transistor T16 is normally on and operates in a linear region, so that the level of the output point R _ N of the second output circuit is low.
As can be seen from the above description, in the signal input stage, the forward signal generating unit of the gate driving circuit provided by the present invention outputs the forward signal with high level, and the reverse signal generating unit outputs the reverse signal with low level.
In summary, the gate driving circuit provided by the embodiment of the invention can effectively solve the problems of speed limitation and incomplete high and low levels of a single-type device circuit. The high and low levels output by the forward signal generating unit and the reverse signal generating unit can reach full high and low level voltages, the rising and falling edges are all 500n seconds, and the whole circuit framework works stably and at high speed.
The control signal of the gate driving circuit provided by the embodiment of the invention only has one high-level signal, and the stable output of positive and negative signals can be realized by two low-level signals. In addition, the small number of signals can enable the display screen to meet the requirement of high resolution, and the power consumption caused by signal increase can be greatly reduced; meanwhile, the invention has simple signal waveform and is easy to realize narrow frames.
The embodiment of the invention also provides a GOA circuit which comprises the gate driving circuit in the technical scheme.
Compared with the prior art, the beneficial effects of the GOA circuit provided by the invention are the same as those of the gate driving circuit in the above technical scheme, and are not repeated here.
The embodiment of the invention also provides a driving method of the gate driving circuit, and the gate driving circuit is applied to the technical scheme. The driving method of the gate driving circuit comprises the following steps:
and in the signal input stage, the forward signal generation unit is controlled to output a forward signal with a first level, and the reverse signal generation unit is controlled to output a reverse signal with a second level.
And in a level bootstrap stage, the forward signal generation unit is controlled to output a forward signal with a second level, and the reverse signal generation unit is controlled to sequentially output reverse signals with a first level and a second level.
And in the signal resetting stage, the forward signal generation unit is controlled to output a forward signal with a first level, and the reverse signal generation unit is controlled to output a reverse signal with a second level.
And in the level holding stage, the forward signal generation unit is controlled to output a forward signal with a first level, and the reverse signal generation unit is controlled to output a reverse signal with a second level.
Compared with the prior art, the beneficial effects of the driving method of the gate driving circuit provided by the invention are the same as those of the gate driving circuit in the technical scheme, and the description is omitted here.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present invention, and shall cover the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (8)
1. A gate drive circuit, comprising: a forward signal generating unit and a reverse signal generating unit which are electrically connected; the forward signal generating unit is used for outputting a forward signal, the backward signal generating unit is used for outputting a backward signal, and the pulse width of the forward signal is different from that of the backward signal;
in a signal input stage, the forward signal generation unit outputs a forward signal with a first level, and the reverse signal generation unit outputs a reverse signal with a second level;
in a level bootstrap stage, the forward signal generation unit outputs a forward signal with a second level, and the reverse signal generation unit outputs a reverse signal with a first level and a second level distributed according to a time sequence;
in a signal resetting phase, the forward signal generating unit outputs a forward signal with a first level, and the reverse signal generating unit outputs a reverse signal with a second level;
in a level holding stage, the forward signal generation unit outputs a forward signal having a first level, and the reverse signal generation unit outputs a reverse signal having a second level;
the forward signal generating unit includes: the circuit comprises a forward input circuit, a first inverter circuit, a first level holding circuit, a first output circuit and a first capacitor;
the control end of the forward input circuit is electrically connected with a first clock signal end, the input end of the forward input circuit is electrically connected with an input signal end, the output end of the forward input circuit, the control end of the first output circuit and one end of the first capacitor are electrically connected to a first node, and the output end of the forward input circuit is electrically connected with the first inverter circuit;
the output end of the first inverting circuit and the first level holding circuit are electrically connected to a second node;
the first level holding circuit is electrically connected with the output end of the forward input circuit, the output end of the first output circuit and the other end of the first capacitor respectively; the first level holding circuit is electrically connected with a first control signal end;
the input end of the first output circuit is electrically connected with a third clock signal end;
the reverse signal generating unit includes: the circuit comprises an inverted input circuit, a reset circuit, a second inverting circuit, a second level holding circuit and a second output circuit;
the control end of the reverse input circuit is electrically connected with the output end of the first output circuit, the input end of the reverse input circuit is electrically connected with the second control signal end, and the output end of the reverse input circuit is electrically connected with the control end of the second output circuit and the output end of the reset circuit respectively;
the control end of the reset circuit is electrically connected with the first clock signal end, and the input end of the reset circuit is electrically connected with the first control signal end;
the control end of the second level holding circuit is electrically connected with the output end of the second inverter circuit, the input end of the second level holding circuit is electrically connected with the second control signal end, and the output end of the second level holding circuit is electrically connected with the output end of the second output circuit;
and the input end of the second output circuit is electrically connected with a fourth clock signal end.
2. A gate drive circuit according to claim 1, wherein the forward signal generating unit comprises: a leakage protection circuit;
the input end of the leakage protection circuit is electrically connected with the output end of the forward input circuit, and the output end of the leakage protection circuit is electrically connected with the first node; and the control end of the leakage protection circuit is electrically connected with the second control signal end.
3. A gate drive circuit as claimed in claim 1, wherein the first inverter circuit comprises: a first switching circuit and a second switching circuit;
the control end of the first switch circuit is electrically connected with the first clock signal end, the input end of the first switch circuit is electrically connected with the second control signal end, and the output end of the first switch circuit is electrically connected with the second node;
the control end of the second switch circuit is electrically connected with the output end of the forward input circuit, the input end of the second switch circuit is electrically connected with the first clock signal end, and the output end of the second switch circuit is electrically connected with the second node.
4. A gate drive circuit as claimed in claim 3, wherein the first level holding circuit comprises: a third switch circuit, a fourth switch circuit, and a fifth switch circuit;
the control end of the third switching circuit is electrically connected with the third clock signal end, the input end of the third switching circuit is electrically connected with the output end of the forward input circuit, and the output end of the third switching circuit is electrically connected with the output end of the fourth switching circuit;
a control end of the fourth switching circuit is electrically connected to the second node, and an input end of the fourth switching circuit is electrically connected to the first control signal end;
the control end of the fifth switch circuit is electrically connected to the second node, the input end of the fifth switch circuit is electrically connected to the first control signal end, and the output end of the fifth switch circuit is electrically connected to the other end of the first capacitor and the output end of the first output circuit respectively.
5. The gate drive circuit according to claim 1, wherein the second inverter circuit comprises: a sixth switching circuit, a seventh switching circuit, an eighth switching circuit, and a ninth switching circuit;
the control end and the input end of the sixth switching circuit are both electrically connected with a third control signal end, and the output end of the sixth switching circuit is electrically connected with the control end of the seventh switching circuit;
the input end of the seventh switch circuit is electrically connected with the third control signal end, and the output end of the seventh switch circuit is electrically connected with the output end of the eighth switch circuit and the output end of the ninth switch circuit;
the input end of the eighth switching circuit is electrically connected with the first control signal end, and the control end of the eighth switching circuit is electrically connected with the output end of the first output circuit;
the input end of the ninth switching circuit is electrically connected with the first control signal end, and the control end of the ninth switching circuit is electrically connected with the output end of the first output circuit; and/or the presence of a gas in the gas,
the reverse signal generating unit further includes: a second capacitor;
and one end of the second capacitor is electrically connected with the output end of the eighth switching circuit, and the other end of the second capacitor is electrically connected with the control end of the second output circuit.
6. The gate driving circuit according to claim 5, wherein when the transistors constituting the gate driving circuit are all P-type transistors, the first control signal terminal outputs a first control signal having a high level, the second control signal terminal outputs a second control signal having a low level, and the third control signal terminal outputs a third control signal having a low level;
in a signal input stage, the first clock signal terminal outputs a first clock signal having a low level, the second clock signal terminal outputs a second clock signal having a high level and a low level distributed according to a time sequence, the third clock signal terminal outputs a third clock signal having a high level, the fourth clock signal terminal outputs a fourth clock signal having a high level, and the input signal terminal outputs an input signal having a low level;
in a level bootstrap stage, the first clock signal terminal outputs a first clock signal having a high level, the second clock signal terminal outputs a second clock signal having a low level and a high level distributed according to a timing sequence, the third clock signal terminal outputs a third clock signal having a low level, the fourth clock signal terminal outputs a fourth clock signal having a high level and a low level distributed according to a timing sequence, and the input signal terminal outputs an input signal having a high level;
in a signal reset phase, the first clock signal terminal outputs a first clock signal having a low level, the second clock signal terminal outputs a second clock signal having a high level and a low level distributed according to a timing, the third clock signal terminal outputs a third clock signal having a high level, the fourth clock signal terminal outputs a fourth clock signal having a low level and a high level distributed according to a timing, and the input signal terminal outputs an input signal having a high level;
in the level holding stage, the first clock signal terminal outputs a first clock signal having a high level, the second clock signal terminal outputs a second clock signal having a low level and a high level distributed according to a timing, the third clock signal terminal outputs a third clock signal having a low level, the fourth clock signal terminal outputs a fourth clock signal having a high level and a low level distributed according to a timing, and the input signal terminal outputs an input signal having a high level.
7. A GOA circuit comprising the gate driver circuit of any one of claims 1 to 6.
8. A method for driving a gate driver circuit, which is applied to the gate driver circuit according to any one of claims 1 to 6, the method comprising:
in a signal input stage, controlling a forward signal generating unit to output a forward signal with a first level, and controlling a reverse signal generating unit to output a reverse signal with a second level;
in a level bootstrap stage, controlling the forward signal generation unit to output a forward signal with a second level, and controlling the reverse signal generation unit to sequentially output reverse signals with a first level and a second level;
in a signal resetting stage, controlling the forward signal generating unit to output a forward signal with a first level, and controlling the reverse signal generating unit to output a reverse signal with a second level;
and in the level holding stage, controlling the forward signal generation unit to output a forward signal with a first level, and controlling the reverse signal generation unit to output a reverse signal with a second level.
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| CN202110632363.7A CN113380172B (en) | 2021-06-07 | 2021-06-07 | Gate drive circuit, drive method and GOA circuit |
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| CN202110632363.7A CN113380172B (en) | 2021-06-07 | 2021-06-07 | Gate drive circuit, drive method and GOA circuit |
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| JP4339103B2 (en) * | 2002-12-25 | 2009-10-07 | 株式会社半導体エネルギー研究所 | Semiconductor device and display device |
| TWI493557B (en) * | 2011-04-28 | 2015-07-21 | Au Optronics Corp | Shift register circuit |
| KR20130143318A (en) * | 2012-06-21 | 2013-12-31 | 삼성디스플레이 주식회사 | Stage circuit and organic light emitting display device using the same |
| KR20150016706A (en) * | 2013-08-05 | 2015-02-13 | 삼성디스플레이 주식회사 | Stage circuit and organic light emitting display device using the same |
| CN104658475B (en) * | 2013-11-21 | 2017-04-26 | 乐金显示有限公司 | Organic light emitting diode display device |
| CN104157236B (en) * | 2014-07-16 | 2016-05-11 | 京东方科技集团股份有限公司 | A kind of shift register and gate driver circuit |
| CN104409038B (en) * | 2014-11-25 | 2017-05-24 | 北京大学深圳研究生院 | Gate drive circuit, unit thereof and AMOLED display |
| CN104599620B (en) * | 2014-12-10 | 2017-09-26 | 华南理工大学 | Phase inverter, grid integrated drive and the driving method of grid integrated drive electronics |
| CN104485061B (en) * | 2014-12-23 | 2018-03-23 | 上海天马有机发光显示技术有限公司 | Dynamic logic circuit, gate driving circuit, display panel and display device |
| CN104900184B (en) * | 2015-05-21 | 2017-07-28 | 北京大学深圳研究生院 | A kind of organic LED panel, gate driving circuit and its unit |
| CN104952396B (en) * | 2015-06-30 | 2017-10-31 | 上海天马有机发光显示技术有限公司 | A kind of shift register and its driving method |
| CN105632410B (en) * | 2016-03-15 | 2018-04-10 | 上海天马有机发光显示技术有限公司 | A kind of shift register, gate driving circuit, display panel and driving method |
| CN106601190B (en) * | 2017-03-06 | 2018-12-21 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
| CN106952602B (en) * | 2017-04-14 | 2022-01-21 | 京东方科技集团股份有限公司 | Inverter module, shift register unit, array substrate and display device |
| CN110660362B (en) * | 2018-06-28 | 2021-01-22 | 京东方科技集团股份有限公司 | Shift register and grid drive circuit |
| CN110033734B (en) * | 2019-04-25 | 2021-08-10 | 京东方科技集团股份有限公司 | Display driving circuit, driving method thereof and display device |
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