CN111916016B - Scanning driving circuit, display panel and display device - Google Patents
Scanning driving circuit, display panel and display device Download PDFInfo
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- CN111916016B CN111916016B CN202010731347.9A CN202010731347A CN111916016B CN 111916016 B CN111916016 B CN 111916016B CN 202010731347 A CN202010731347 A CN 202010731347A CN 111916016 B CN111916016 B CN 111916016B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Abstract
The invention discloses a scanning driving circuit, a display panel and a display device. The scanning driving circuit comprises an input module, a first control module, a second control module, a storage module, a first output module and a second output module; the second control module is connected with the first end of the storage module, and the second end of the storage module is connected with the control end of the second output module. When a second clock signal provided by the second clock signal input end jumps, the coupling effect of the parasitic capacitor of the second output module enables the potential of the second end of the storage module to change, the second output module is coupled to the second control module through the coupling effect of the storage module and cannot be coupled to the output end of the scanning driving circuit to influence the potential of the scanning signal output by the output end of the scanning driving circuit, so that the abnormity of the scanning signal output by the output end of the scanning driving circuit is avoided, the stability of the scanning signal output by the scanning driving circuit is improved, and the abnormal display phenomenon of the display panel is reduced.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a scanning driving circuit, a display panel and a display device.
Background
The display panel is provided with a scanning driving circuit for providing scanning signals for the pixel units and controlling the pixel units in the display panel to drive line by line. In the prior art, the scanning driving circuit has an electric leakage phenomenon, so that the output tube of the scanning driving circuit has a phenomenon of misconduction due to the coupling effect of the self capacitor, and the display panel has a splash screen caused by abnormal output signals of the scanning driving circuit.
Disclosure of Invention
The invention provides a scanning driving circuit, a display panel and a display device, which are used for improving the stability of scanning signals output by the scanning driving circuit.
In a first aspect, an embodiment of the present invention provides a scan driving circuit, including an input module, a first control module, a second control module, a storage module, a first output module, and a second output module;
the input module is connected with a first clock signal input end, an input signal end, the first control module, the second control module and the second output module, and the input module is used for providing input signals for the first control module, the second control module and the second output module;
the first control module is connected with the first clock signal input end, the first power signal input end, the first output module and the second control module, and is used for providing a first control signal for the first output module and the second control module;
the second control module is connected with a second power signal input end, a second clock signal input end and the first end of the storage module, and is used for providing a second power signal provided by the second power signal input end or a second clock signal provided by the second clock signal input end for the storage module; the second end of the storage module is connected with the control end of the second output module and is used for maintaining the potential of the control end of the second output module;
the first output module is connected with the second power supply signal input end and used for outputting the second power supply signal according to the first control signal; the second output module is connected with the second clock signal input end and used for outputting the second clock signal according to the input signal provided by the input module.
Optionally, the memory module comprises a first capacitor;
the first pole of the first capacitor is used as the first end of the storage module and is electrically connected with the output end of the second control module, and the second pole of the first capacitor is used as the second end of the storage module.
Optionally, the input module comprises a first transistor;
the gate of the first transistor is connected to the first clock signal input terminal, the first pole of the first transistor is connected to the input signal terminal, and the second pole of the first transistor is connected to the first control terminal of the first control module, the first control terminal of the second control module, and the control terminal of the second output module.
Optionally, the first control module comprises a second transistor and a third transistor;
a gate of the second transistor is electrically connected to the first clock signal input terminal, a first pole of the second transistor is connected to the first power signal input terminal, a second pole of the second transistor is connected to a second pole of the third transistor, the second control terminal of the second control module and the control terminal of the first output module, a gate of the third transistor is used as the first control terminal of the first control module, and a first pole of the third transistor is connected to the first clock signal input terminal.
Optionally, the second control module comprises a fourth transistor and a fifth transistor;
a gate of the fourth transistor is used as a first control end of the second control module, a gate of the fifth transistor is used as a second control end of the second control module, a first pole of the fourth transistor is connected with the second clock signal input end, a first pole of the fifth transistor is connected with the second power signal input end, and a second pole of the fourth transistor is connected with a second pole of the fifth transistor and used as an output end of the second control module.
Optionally, the first output module includes a sixth transistor and a second capacitor;
the gate of the sixth transistor is connected to the first pole of the second capacitor and serves as the control end of the first output module, the first pole of the sixth transistor and the second pole of the second capacitor are connected to the second power signal input end, and the second pole of the sixth transistor serves as the output end of the scan driving circuit.
Optionally, the second output module comprises a seventh transistor;
a gate of the seventh transistor is used as a control terminal of the second output module, a first pole of the seventh transistor is connected to the second clock signal input terminal, and a second pole of the seventh transistor is electrically connected to a second pole of the sixth transistor.
Optionally, the scan driving circuit further comprises an eighth transistor;
a gate of the eighth transistor is connected to the first power signal input terminal, and a second pole of the first transistor and a gate of the seventh transistor are connected through the eighth transistor.
In a second aspect, an embodiment of the present invention further provides a display panel, including a first clock signal line, a second clock signal line, a first power signal line, a second power signal line, an input signal line, and at least two scan driving circuits provided in any embodiment of the present invention;
a first clock signal input terminal of the scan driving circuit is electrically connected to the first clock signal line, a second clock signal input terminal of the scan driving circuit is electrically connected to the second clock signal line, a first power signal input terminal of the scan driving circuit is electrically connected to the first power signal line, and a second power signal input terminal of the scan driving circuit is electrically connected to the second power signal line;
at least two scanning driving circuits are connected in cascade, and the input signal end of the first scanning driving circuit is electrically connected with the input signal line; the output end of the scanning driving circuit of the previous stage is electrically connected with the input signal end of the scanning driving circuit of the next stage.
In a third aspect, an embodiment of the present invention further provides a display device including the display panel provided in any embodiment of the present invention.
According to the technical scheme of the embodiment of the invention, the first end of the storage module is connected with the second control module, and the second end of the storage module is connected with the control end of the second output module. When a second clock signal provided by the second clock signal input end jumps, the coupling effect of the parasitic capacitor of the second output module enables the potential of the second end of the storage module to change, the second output module is coupled to the second control module through the coupling effect of the storage module and cannot be coupled to the output end of the scanning driving circuit to influence the potential of the scanning signal output by the output end of the scanning driving circuit, so that the abnormity of the scanning signal output by the output end of the scanning driving circuit is avoided, the stability of the scanning signal output by the scanning driving circuit is improved, and the abnormal display phenomenon of the display panel is reduced. In addition, the second control module controls the potential of the first end of the storage module to be fixed, so that the potential change of the control end of the second output module caused by the coupling effect of the parasitic capacitor of the second output module can be reduced, the probability of the second output module outputting the second clock signal by mistake is reduced, and the stability of the scanning driving circuit can be further improved.
Drawings
FIG. 1 is a schematic diagram of a conventional scan driving circuit;
FIG. 2 is a timing simulation diagram corresponding to the scan driving circuit shown in FIG. 1;
fig. 3 is a schematic structural diagram of a scan driving circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of another exemplary scan driving circuit according to the present invention;
FIG. 7 is a schematic diagram of another exemplary scan driving circuit according to the present invention;
FIG. 8 is a schematic diagram of another exemplary scan driving circuit according to the present invention;
FIG. 9 is a schematic diagram of another exemplary scan driving circuit according to the present invention;
FIG. 10 is a timing diagram of the scan driving circuit shown in FIG. 9;
FIG. 11 is a timing simulation diagram corresponding to the scan driving circuit provided in FIG. 9;
FIG. 12 is a schematic diagram of another exemplary scan driving circuit according to the present invention;
fig. 13 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 14 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic structural diagram of a conventional scan driving circuit. As shown in fig. 1, the scan driving circuit includes 8T2C, and specifically includes a first thin film transistor M1, a second thin film transistor M2, a third thin film transistor M3, a fourth thin film transistor M4, a fifth thin film transistor M5, a sixth thin film transistor M6, a seventh thin film transistor M7, an eighth thin film transistor M8, a first storage capacitor Cs1, and a second storage capacitor Cs2. Wherein the gate of the first thin film transistor M1 and the gate of the fifth thin film transistor M5 are electrically connected to the first clock signal line CLK1, the first pole of the first thin film transistor M1 is electrically connected to the initialization signal line IN, the second pole of the first thin film transistor M1 is electrically connected to the first pole of the second thin film transistor M2, the gate of the fourth thin film transistor M4 and the first pole of the eighth thin film transistor M8, the gate of the second thin film transistor M2 is electrically connected to the second clock signal line CLK2, the second pole of the second thin film transistor M2 is electrically connected to the first pole of the third thin film transistor M3, the second pole of the third thin film transistor M3 is electrically connected to the first power source VGH, the gate of the third thin film transistor M3 is electrically connected to the second pole of the fourth thin film transistor M4, the second pole of the fifth thin film transistor M5, the first pole of the first storage capacitor Cs1 and the gate of the sixth thin film transistor vgm 6, the gate of the fourth thin film transistor M4 is electrically connected to the second power source signal line 1, the seventh thin film transistor Cs1 is electrically connected to the second power source signal line VGH, the second thin film transistor Cs2 is electrically connected to the second scan signal line Cs1, the second thin film transistor Cs2, the second scan transistor Cs1 is electrically connected to the seventh thin film transistor Cs2, the gate of the seventh thin film transistor Cs1 is electrically connected to the second scan transistor Cs 7, the seventh thin film transistor Cs2, the second scan signal line of the seventh thin film transistor Cs2, and the seventh thin film transistor Cs2 is electrically connected to the gate of the seventh thin film transistor VGH, and the second scan transistor Cs 7. The thin film transistors in the scan driver circuit provided in fig. 1 are all illustrated by taking P-type thin film transistors as examples.
In the process of the operation of the scan driving circuit, when the process fluctuation of the thin film transistor or the environmental temperature is too high, the fourth thin film transistor M4 has a leakage phenomenon in an off state. When the scan driving circuit outputs a high level, the drain of the fourth thin film transistor M4 increases the second pole potential of the fourth thin film transistor M4, that is, the potentials of the gate of the third thin film transistor M3 and the gate of the sixth thin film transistor M6 increase, which causes the third thin film transistor M3 and the sixth thin film transistor M6 to turn off, the high level provided by the first power signal line VGH cannot be output to the scan signal output terminal SOUT through the sixth thin film transistor M6, and cannot be transmitted to the gate of the seventh thin film transistor M7 through the third thin film transistor M3, and the gate of the seventh thin film transistor M7 is in a floating state. When the second clock signal provided by the second clock signal line CLK2 jumps from a high level to a low level, the coupling effect of the self-capacitance of the seventh thin film transistor M7 causes the gate potential of the seventh thin film transistor M7 to be pulled low and coupled to the scan signal output terminal SOUT through the second storage capacitor Cs2, so that the potential of the scan signal output by the scan signal output terminal SOUT is lowered, which causes the scan driving circuit to output an abnormal state, resulting in a flicker of the display panel. Fig. 2 is a timing simulation diagram corresponding to the scan driving circuit provided in fig. 1. As shown in fig. 2, the abscissa is time and the ordinate is voltage. A curve 1 is a timing sequence of a first clock signal provided by the first clock signal line, a curve 2 is a timing sequence of a second clock signal provided by the second clock signal line, a curve 3 is a timing sequence of an initialization signal provided by the initialization signal line, and a curve 4 is a timing sequence of a scan signal output by the scan signal output terminal SOUT. As can be seen from fig. 2, when the scan signal output from the scan signal output terminal SOUT is at a high level, there is an output abnormality (e.g., a dotted line in fig. 2).
In view of the above technical problems, an embodiment of the present invention provides a scan driving circuit. Fig. 3 is a schematic structural diagram of a scan driving circuit according to an embodiment of the present invention. As shown in fig. 3, the scan driving circuit includes an input module 110, a first control module 120, a second control module 130, a memory module 140, a first output module 150, and a second output module 160; the input module 110 is connected to the first clock signal input terminal CK1, the input signal terminal EN, the first control module 120, the second control module 130, and the second output module 160, and the input module 110 is configured to provide input signals to the first control module 120, the second control module 130, and the second output module 160; the first control module 120 is connected to the first clock signal input terminal CK1, the first power signal input terminal VL, the first output module 150 and the second control module 130, and the first control module 120 is configured to provide a first control signal for the first output module 150 and the second control module 130; the second control module 130 is connected to the second power signal input terminal VH, the second clock signal input terminal CK2 and the first terminal of the memory module 140, and the second control module 130 is configured to provide the second power signal provided by the second power signal input terminal VH or the second clock signal provided by the second clock signal input terminal CK2 for the memory module 140; the second terminal of the memory module 140 is connected to the control terminal of the second output module 160, and is configured to maintain the potential of the control terminal of the second output module 160; the first output module 150 is connected to the second power signal input end VH, and is configured to output a second power signal according to the first control signal; the second output module 160 is connected to the second clock signal input terminal CK2, and is configured to output the second clock signal according to the input signal provided by the input module 110.
Specifically, as shown in fig. 3, the first power signal provided from the first power signal input terminal VL may be at a low level, and the second power signal provided from the second power signal input terminal VH may be at a high level. The first clock signal provided by the first clock signal input terminal CK1 and the second clock signal provided by the second clock signal input terminal CK2 may be signals with opposite high and low levels. In the process of operating the scan driving circuit, the first control module 120 controls the first output module 150 to output the second power signal at a high level, and the input module 110 and the second control module 130 control the second output module 160 to output the second clock signal, which may be at a high level or a low level. Because the first end of the memory module 140 is connected to the second control module 130, and the second end of the memory module 140 is connected to the control end of the second output module 160, when the second clock signal provided by the second clock signal input end CK2 jumps, the coupling effect of the parasitic capacitor of the second output module 160 itself causes the potential change of the control end of the second output module 160, that is, the potential change of the second end of the memory module 140, which is coupled to the first end of the memory module 140, that is, coupled to the second control module 130, to not affect the potential of the scan signal output by the output end OUT of the scan driving circuit by being coupled to the output end OUT of the scan driving circuit, thereby avoiding the abnormality of the scan signal output by the output end OUT of the scan driving circuit, improving the stability of the scan signal output by the scan driving circuit, and further reducing the abnormal display phenomenon of the display panel. In addition, when the first control module 120 controls the first output module 150 to output the second power signal, the first control module 120 simultaneously controls the second control module 130 to output the second power signal to the first end of the storage module 140, so that the first end of the storage module 140 maintains the potential of the second power signal, and when the second clock signal jumps, the fixed potential of the first end of the storage module 140 can reduce the potential change of the control end of the second output module 160 caused by the coupling effect of the parasitic capacitor of the second output module 160, thereby reducing the probability that the second output module 160 outputs the second clock signal by mistake, and further improving the stability of the scan driving circuit.
Fig. 4 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention. As shown in fig. 4, the memory module 140 includes a first capacitor C1; a first pole of the first capacitor C1 is used as a first terminal of the memory module 140 and is electrically connected to the output terminal of the second control module 130, and a second pole of the first capacitor C1 is used as a second terminal of the memory module 140.
Specifically, as shown in fig. 4, the first capacitor C1 is not connected to the output terminal OUT of the scan driving circuit, when the second clock signal jumps, the potential of the control terminal of the second output module 160 changes, that is, the potential of the second pole of the first capacitor C1 changes, and the coupling effect of the first capacitor C1 makes the potential of the first capacitor C1 change, so that the potential of the output terminal OUT of the scan driving circuit is not affected, thereby improving the stability of the scan driving circuit. Moreover, when the potential of the first pole of the first capacitor C1 is fixed, the fixed potential of the first pole of the first capacitor C1 can reduce the potential variation of the control end of the second output module 160, and reduce the probability that the second output module 160 outputs the second clock signal by mistake, thereby further improving the stability of the scan driving circuit.
Fig. 5 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention. As shown in fig. 5, the input module 110 includes a first transistor T1; a gate of the first transistor T1 is connected to the first clock signal input terminal CK1, a first pole of the first transistor T1 is connected to the input signal terminal EN, and a second pole of the first transistor T1 is connected to the first control terminal of the first control module 120, the first control terminal of the second control module 130, and the control terminal of the second output module 160.
Specifically, fig. 5 exemplarily shows that the first transistor T1 is a P-type transistor. When the first clock signal is at a low level, the first transistor T1 is turned on, and the input signal may be transmitted to the first control terminal of the first control module 120, the first control terminal of the second control module 130, and the control terminal of the second output module 160 through the first transistor T1.
It should be noted that, in other embodiments, the first transistor T1 may also be a double-gate transistor. By providing the first transistor T1 as a double gate transistor, the leakage phenomenon of the first transistor T1 can be reduced.
Fig. 6 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention. As shown in fig. 6, the first control module 120 includes a second transistor T2 and a third transistor T3; a gate of the second transistor T2 is electrically connected to the first clock signal input terminal CK1, a first pole of the second transistor T2 is connected to the first power signal input terminal VL, a second pole of the second transistor T2 is connected to a second pole of the third transistor T3, the second control terminal of the second control module 130, and the control terminal of the first output module 150, a gate of the third transistor T3 is used as the first control terminal of the first control module 120, and a first pole of the third transistor T3 is connected to the first clock signal input terminal CK 1.
In particular, it is exemplarily shown in fig. 6 that the second transistor T2 and the third transistor T3 are P-type transistors. When the first clock signal is at a low level and the input signal is at a high level, the first transistor T1 and the second transistor T2 are turned on, the input signal is transmitted to the gate of the third transistor T3 through the first transistor T1 to control the third transistor T3 to be turned off, the first power signal is transmitted to the control terminal of the first output module 150 through the second transistor T2 to control the first output module 150 to output the second power signal. Meanwhile, the second power signal is transmitted to the control terminal of the second output module 160 through the second control module 130, and the second output module 160 is controlled not to output the second clock signal. When the first clock signal is at a high level, the first transistor T1 and the second transistor T2 are turned off, the control terminal of the first output module 150 is in a floating state and is maintained as the first power signal, and the first output module 150 is controlled to continue outputting the second power signal. Meanwhile, the second control module 130 is maintained to output the second power signal, and the second output module 160 is controlled not to output the second clock signal.
Fig. 7 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention. As shown in fig. 7, the second control module 130 includes a fourth transistor T4 and a fifth transistor T5; a gate of the fourth transistor T4 serves as a first control terminal of the second control module 130, a gate of the fifth transistor T5 serves as a second control terminal of the second control module 130, a first pole of the fourth transistor T4 is connected to the second clock signal input terminal CK2, a first pole of the fifth transistor T5 is connected to the second power signal input terminal VH, and a second pole of the fourth transistor T4 is connected to the second pole of the fifth transistor and serves as an output terminal of the second control module 130.
In particular, it is exemplarily shown in fig. 7 that the fourth transistor T4 and the fifth transistor T5 are P-type transistors. The gate of the fourth transistor T4 is connected to the second pole of the first transistor T1, the gate of the fifth transistor T5 is connected to the second pole of the second transistor T2, and the second pole of the fourth transistor T4 and the second pole of the fifth transistor T5 are connected to the first pole of the first capacitor C1. When the first clock signal is at a low level, the second clock signal is at a high level, and the input signal is at a high level, the first transistor T1 is turned on, the input signal is transmitted to the gate of the fourth transistor T4 and the control terminal of the second output module 160 through the first transistor T1, and the fourth transistor T4 is controlled to be turned off and the second output module 160 cannot output the second clock signal. The second transistor T2 is turned on, the first power signal controls the first output module 150 to output the second power signal, and at the same time, the first power signal controls the fifth transistor T5 to be turned on, the second power signal is transmitted to the first pole of the first capacitor C1 through the fifth transistor T5, and at this time, the second pole of the first capacitor C1 is at a high level, so that no electric energy is stored in the first capacitor C1. When the first clock signal is at a high level, the second clock signal is at a low level, and the input signal is at a high level, the first transistor T1 and the second transistor T2 are turned off, the control terminal of the first output module 150 is in a floating state, the first output module 150 maintains the first power signal, and the first output module 150 continues to output the second power signal. Meanwhile, the fifth transistor T5 is continuously turned on, the second power signal is transmitted to the first electrode of the first capacitor C1 through the fifth transistor T5, and the gate of the fourth transistor T4 and the control end of the second output module 160 can be prevented from being in a floating state by the maintaining function of the first capacitor C1, so that the potential change of the second output module 160 caused by the coupling function of the parasitic capacitor of the second output module 160 can be reduced when the second clock signal jumps, and the probability that the second output module 160 outputs the second clock signal by mistake is reduced.
Fig. 8 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention. As shown in fig. 8, the first output module 150 includes a sixth transistor T6 and a second capacitor C2; a gate of the sixth transistor T6 is connected to the first electrode of the second capacitor C2 and serves as a control terminal of the first output module 150, a first electrode of the sixth transistor T6 and a second electrode of the second capacitor C2 are connected to the second power signal input terminal VH, and a second electrode of the sixth transistor T6 serves as an output terminal OUT of the scan driving circuit.
Specifically, fig. 8 exemplarily shows that the sixth transistor T6 is a P-type transistor. When the input signal is at a high level, the first clock signal is at a low level, and the second clock signal is at a high level, the first transistor T1 and the second transistor T2 are turned on, the input signal is transmitted to the gate of the third transistor T3 through the first transistor T1, the third transistor T3 is controlled to be turned off, the first power supply signal is transmitted to the gate of the sixth transistor T6 through the second transistor T2, the sixth transistor T6 is controlled to be turned on, the second power supply signal is transmitted to the output terminal OUT of the scan driving circuit through the sixth transistor T6, and the scan driving circuit outputs a high level signal. Meanwhile, the input signal is transmitted to the control terminal of the second output module 160 through the first transistor T1, and the second output module 160 is controlled not to output the second clock signal. Moreover, the first power signal controls the fifth transistor T5 to be turned on, the second power signal is transmitted to the first electrode of the first capacitor C1 through the fifth transistor T5, both ends of the first capacitor C1 are at a high level, and the first capacitor C1 does not store electric energy.
When the input signal is at a high level, the first clock signal is at a high level, and the second clock signal is at a low level, the first transistor T1 and the second transistor T2 are turned off, and the gate of the sixth transistor T6 is in a floating state, at this time, the gate of the sixth transistor T6 is maintained at a low level by the maintaining function of the second capacitor C2, and the sixth transistor T6 is turned on, so as to output the second power supply signal. The first power signal controls the fifth transistor T5 to be turned on, and the second power signal is transmitted to the first electrode of the first capacitor C1 through the fifth transistor T5, so that the potential of the first power signal is fixed. The control terminal of the second output module 160 is in a floating state, and the control terminal of the second output module 160 is at a high level by the maintaining function of the first capacitor C1, so as to control the second output module 160 not to output the second clock signal.
When the input signal is at a low level, the first clock signal is at a low level, and the second clock signal is at a high level, the first transistor T1 and the second transistor T2 are turned on, the input signal is transmitted to the gate of the third transistor T3 through the first transistor T1, the third transistor T3 is controlled to be turned on, the first power signal and the first clock signal are transmitted to the gate of the sixth transistor T6 through the second transistor T2, the sixth transistor T6 is controlled to be turned on, the second power signal is transmitted to the output terminal OUT of the scan driving circuit through the sixth transistor T6, and the scan driving circuit outputs a high level signal. Meanwhile, the input signal controls the second output module 170 to output the second clock signal at a high level. And controls the second pole of the first capacitor C1 to be at a low level, so that the first capacitor C1 stores electric energy.
When the input signal is at a high level, the first clock signal is at a high level, and the second clock signal is at a low level, the first transistor T1 and the second transistor T2 are turned off, the holding function of the first capacitor C1 can make the second electrode of the first capacitor C1 at a low level, so that the third transistor T3 is turned on, the first clock signal is transmitted to the gate of the sixth transistor T6 through the third transistor T3, the sixth transistor T6 is controlled to be turned off, and the second power signal cannot be transmitted to the output terminal OUT of the scan driving circuit through the sixth transistor T6. Meanwhile, the second output module 170 outputs the second clock signal as a low level.
Fig. 9 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention. As shown in fig. 9, the second output module 160 includes a seventh transistor T7; a gate of the seventh transistor T7 serves as a control terminal of the second output module 160, a first pole of the seventh transistor T7 is connected to the second clock signal input terminal CK2, and a second pole of the seventh transistor T7 is electrically connected to a second pole of the sixth transistor T6.
Specifically, it is exemplarily shown in fig. 9 that the seventh transistor T7 is a P-type transistor. When the input signal is at a low level, the seventh transistor T7 may be controlled to be turned on, and the second clock signal is output through the seventh transistor T7, that is, the output terminal OUT of the scan driving circuit outputs the second clock signal.
Fig. 10 is a timing diagram corresponding to the scan driving circuit provided in fig. 9. The first power signal provided by the first power signal input terminal VL is at a low level, and the second power signal provided by the second power signal input terminal VH is at a high level. CK1 is a timing of a first clock signal supplied from the first clock signal line CK1, CK2 is a timing of a second clock signal supplied from the second clock signal line CK2, EN is a timing of an input signal supplied from the input signal line EN, and out is a timing of a scan signal output from the scan driving circuit. The operation of the light emission control circuit is explained with reference to fig. 9 and 10.
In the first stage T11, en is at a high level, ck1 is at a low level, ck2 is at a high level, the first transistor T1 and the second transistor T2 are turned on, the input signal controls the third transistor T3, the fourth transistor T4 and the seventh transistor T7 to be turned off through the first transistor T1, and the second clock signal cannot be transmitted to the output terminal OUT of the scan driving circuit through the seventh transistor T7. The first power supply signal is transmitted to the gate of the sixth transistor T6 and the gate of the fifth transistor T5 through the second transistor T2 to control the sixth transistor T6 and the fifth transistor T5 to be turned on, the second power supply signal is output to the output terminal OUT of the scan driving circuit through the sixth transistor T6, and the scan driving circuit outputs a high level. Meanwhile, the second power signal is transmitted to the first pole of the first capacitor C1 through the fifth transistor T5, and at this time, the second pole of the first capacitor C1 is at a high level, and no electric energy is stored in the first capacitor C1.
In the second stage T12, en is at a high level, ck1 is at a high level, ck2 is at a low level, the first transistor T1 and the second transistor T2 are turned off, the gate of the sixth transistor T6 and the gate of the seventh transistor T7 are in a floating state, the second capacitor C2 can maintain the gate potential of the sixth transistor T6 at a low level, so that the sixth transistor T6 is continuously turned on, and the sixth transistor T6 continuously outputs a high level to the output terminal OUT of the scan driving circuit. Meanwhile, the fifth transistor T5 is kept turned on, and the second power signal keeps the first electrode potential of the first capacitor C1, so that the first capacitor C1 can keep the gate potential of the seventh transistor T7 at a high level, and the second clock signal cannot be transmitted to the output terminal OUT of the scan driving circuit through the seventh transistor T7. The seventh transistor T7 is an output tube, and has a large parasitic capacitance.
In the second phase T12, when the second clock signal changes from high level to low level, the gate potential of the seventh transistor T7, i.e. the second pole potential of the first capacitor C1, changes due to the parasitic capacitance of the seventh transistor T7. The first pole of the first capacitor C1 is connected with the second pole of the fifth transistor T5, so that the potential of the scanning signal is prevented from being influenced by the output end OUT of the scanning driving circuit when the potential of the second pole of the first capacitor C1 is changed and coupled to the first pole of the first capacitor C1, the abnormal phenomenon of the scanning signal output by the output end OUT of the scanning driving circuit is reduced, the stability of the scanning signal output by the scanning driving circuit is improved, and the abnormal display phenomenon of the display panel is reduced. In addition, when the second clock signal changes from high level to low level, the potential of the first pole of the first capacitor C1 is fixed to the second power supply, so that the change of the gate potential of the seventh transistor T7 caused by the coupling action of the parasitic capacitor of the seventh transistor T7 itself can be reduced, the probability of the seventh transistor T7 being turned on by mistake to output the second clock signal is reduced, and the stability of the scanning driving circuit can be further improved. Fig. 11 is a timing simulation diagram corresponding to the scan driving circuit provided in fig. 9. As shown in fig. 11, a curve 5 is a timing sequence of the first clock signal provided by the first clock signal input terminal, a curve 6 is a timing sequence of the second clock signal provided by the second clock signal input terminal, a curve 7 is a timing sequence of the input signal provided by the input signal terminal, and a curve 8 is a timing sequence of the scan signal output by the output terminal of the scan driving circuit. As shown in fig. 11, when the scan signal is at a high level, there is no output abnormality, thereby improving the stability of the scan driving circuit.
In the third stage T13, en is a low level, ck1 is a low level, ck2 is a high level, the first transistor T1 and the second transistor T2 are turned on, the input signal is transmitted to the gate of the third transistor T3 through the first transistor T1 to control the third transistor T3 to be turned on, the first power signal and the first clock signal are transmitted to the gate of the sixth transistor T6 through the second transistor T2 to control the sixth transistor T6 to be turned on, the second power signal is transmitted to the output terminal OUT of the scan driving circuit through the sixth transistor T6, and the scan driving circuit outputs a high level signal. Meanwhile, the input signal is transmitted to the gates of the fourth transistor T4 and the seventh transistor T7 through the first transistor T1, the fourth transistor T4 and the seventh transistor T7 are controlled to be turned on, the first pole of the first capacitor C1 is at a high level, the second pole of the first capacitor C1 is at a low level, and the first capacitor C1 stores electric energy. Meanwhile, the seventh transistor T7 outputs the second clock signal as a high level.
In the fourth phase T14, en is high, ck1 is high, ck2 is low, the first transistor T1 and the second transistor T2 are turned off, the holding function of the first capacitor C1 can make the second electrode of the first capacitor C1 low, so that the third transistor T3 and the seventh transistor T7 are turned on, the first clock signal is transmitted to the gate of the sixth transistor T6 through the third transistor T3, the sixth transistor T6 is controlled to be turned off, and the second power signal cannot be transmitted to the output terminal OUT of the scan driving circuit through the sixth transistor T6. Meanwhile, the seventh transistor T7 outputs the second clock signal as a low level, thereby implementing the shift of the input signal.
Fig. 12 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention. As shown in fig. 12, the scan driving circuit further includes an eighth transistor T8; a gate of the eighth transistor T8 is connected to the first power signal input terminal VL, and a second pole of the first transistor T1 and a gate of the seventh transistor T7 are connected through the eighth transistor T8.
Specifically, it is exemplarily shown in fig. 12 that the eighth transistor T8 is a P-type transistor. The gate of the eighth transistor T6 is electrically connected to the first power signal input terminal VL, and the eighth transistor T8 is always in a conductive state. The second pole of the first transistor T1 is connected to the gate of the seventh transistor T7 through the eighth transistor T8, so that when the potential of the first pole of the seventh transistor T7 is pulled down by the second clock signal to drive the potential of the gate of the seventh transistor T7 to be pulled down, the phenomena that the potential of the second pole of the first transistor T1 is very low and the gate-source voltage difference of the first transistor T1 is too large to cause the first transistor T1 to be damaged are avoided.
The embodiment of the invention also provides a display panel. Fig. 13 is a schematic structural diagram of a display panel according to an embodiment of the present invention. As shown in fig. 13, the display panel includes a first clock signal line 20, a second clock signal line 30, a first power signal line 40, a second power signal line 50, an input signal line 60, and at least two scan driving circuits 10 provided in any of the embodiments of the present invention; a first clock signal input terminal of the scan driving circuit 10 is electrically connected to the first clock signal line 20, a second clock signal input terminal is electrically connected to the second clock signal line 30, a first power signal input terminal is electrically connected to the first power signal line 40, and a second power signal input terminal is electrically connected to the second power signal line 50; at least two scanning driving circuits 10 are connected in cascade, and the input signal end of the first scanning driving circuit 10 is electrically connected with an input signal line 60; the output terminal of the previous stage scan driving circuit 10 is electrically connected to the input signal terminal of the next stage scan driving circuit 10.
Specifically, the display panel may be, for example, an organic light emitting diode display panel, a liquid crystal display panel, an electronic paper display panel, or the like. Each stage of the scan driving circuit 10 is electrically connected to a scan line 70 on the display panel, and transmits a scan signal to each scan line 70. The first stage scan driving circuit 10 shifts the input signal on the input signal line 60 and outputs it through its output terminal. The next-stage scan driving circuit 10 shifts and outputs the scan signal output from the previous-stage scan driving circuit 10. Therefore, the display panel provided by the embodiment of the invention realizes the function of outputting the scanning signals line by line, and the stability of the scanning signals output by each stage of the scanning driving circuit 10 is good.
With continued reference to fig. 13, on the basis of the above embodiments, the scan driving circuit 10 is optionally disposed on both sides of the display panel. Illustratively, the scan driving circuits 10 located at the left side of the display panel are cascade-connected, sequentially transmitting scan signals to odd-numbered scan lines. The scan driving circuits 10 located on the right side of the display panel are connected in cascade and sequentially transmit scan signals to even number of scan lines. The arrangement of the embodiment of the present invention is beneficial to reducing the frame of the scan driving circuit 10 occupying one side of the display panel, thereby being beneficial to reducing the frame width of the display panel.
The embodiment of the invention also provides a display device. Fig. 14 is a schematic structural diagram of a display device according to an embodiment of the present invention. As shown in fig. 14, the display device includes a display panel 1 provided in any embodiment of the present invention. The display device can be, for example, a mobile phone, a tablet computer, an intelligent wearable device, an information inquiry machine in a hall of a public place, and the like. The display device comprises the display panel 1 provided by any embodiment of the invention, and the technical principle and the generated technical effect are similar, and are not described again here.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements and substitutions will now be apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in some detail by the above embodiments, the invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the invention, and the scope of the invention is determined by the scope of the appended claims.
Claims (9)
1. A scanning drive circuit is characterized by comprising an input module, a first control module, a second control module, a storage module, a first output module and a second output module;
the input module is connected with a first clock signal input end, an input signal end, the first control module, the second control module and the second output module, and is used for providing input signals for the first control module, the second control module and the second output module;
the first control module is connected with the first clock signal input end, the first power signal input end, the first output module and the second control module, and is used for providing a first control signal for the first output module and the second control module;
the second control module is connected with a second power signal input end, a second clock signal input end and the first end of the storage module, and is used for providing a second power signal provided by the second power signal input end or a second clock signal provided by the second clock signal input end for the storage module; the second end of the storage module is connected with the control end of the second output module and is used for maintaining the potential of the control end of the second output module;
the first output module is connected with the second power supply signal input end and used for outputting the second power supply signal according to the first control signal; the second output module is connected with the second clock signal input end and used for outputting the second clock signal according to the input signal provided by the input module;
the first control module is used for controlling the second control module to output a second power supply signal to the first end of the storage module;
the second control module comprises a fourth transistor and a fifth transistor;
a gate of the fourth transistor is used as a first control end of the second control module, a gate of the fifth transistor is used as a second control end of the second control module, a first pole of the fourth transistor is connected with the second clock signal input end, a first pole of the fifth transistor is connected with the second power signal input end, and a second pole of the fourth transistor is connected with a second pole of the fifth transistor and is used as an output end of the second control module.
2. The scan driving circuit according to claim 1, wherein the storage module comprises a first capacitor;
the first pole of the first capacitor is used as the first end of the storage module and is electrically connected with the output end of the second control module, and the second pole of the first capacitor is used as the second end of the storage module.
3. The scan driving circuit according to claim 2, wherein the input block comprises a first transistor;
the gate of the first transistor is connected to the first clock signal input terminal, the first pole of the first transistor is connected to the input signal terminal, and the second pole of the first transistor is connected to the first control terminal of the first control module, the first control terminal of the second control module, and the control terminal of the second output module.
4. The scan driving circuit of claim 3, wherein the first control module comprises a second transistor and a third transistor;
a gate of the second transistor is electrically connected to the first clock signal input terminal, a first pole of the second transistor is connected to the first power signal input terminal, a second pole of the second transistor is connected to a second pole of the third transistor, a second control terminal of the second control module, and a control terminal of the first output module, a gate of the third transistor is used as the first control terminal of the first control module, and a first pole of the third transistor is connected to the first clock signal input terminal.
5. The scan driving circuit according to claim 3 or 4, wherein the first output module comprises a sixth transistor and a second capacitor;
a gate of the sixth transistor is connected to the first pole of the second capacitor and serves as a control end of the first output module, the first pole of the sixth transistor and the second pole of the second capacitor are connected to the second power signal input end, and the second pole of the sixth transistor serves as an output end of the scan driving circuit.
6. The scan driving circuit according to claim 5, wherein the second output module comprises a seventh transistor;
a gate of the seventh transistor is used as a control terminal of the second output module, a first pole of the seventh transistor is connected to the second clock signal input terminal, and a second pole of the seventh transistor is electrically connected to a second pole of the sixth transistor.
7. The scan driving circuit according to claim 6, further comprising an eighth transistor;
a gate of the eighth transistor is connected to the first power signal input terminal, and a second pole of the first transistor and a gate of the seventh transistor are connected through the eighth transistor.
8. A display panel comprising a first clock signal line, a second clock signal line, a first power supply signal line, a second power supply signal line, an input signal line, and at least two scan driver circuits according to any one of claims 1 to 7;
a first clock signal input terminal of the scan driving circuit is electrically connected to the first clock signal line, a second clock signal input terminal of the scan driving circuit is electrically connected to the second clock signal line, a first power supply signal input terminal of the scan driving circuit is electrically connected to the first power supply signal line, and a second power supply signal input terminal of the scan driving circuit is electrically connected to the second power supply signal line;
at least two scanning driving circuits are connected in a cascade mode, and the input signal end of the first stage of scanning driving circuit is electrically connected with the input signal line; the output end of the scanning driving circuit of the previous stage is electrically connected with the input signal end of the scanning driving circuit of the next stage.
9. A display device characterized by comprising the display panel according to claim 8.
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| CN112489582A (en) * | 2020-11-26 | 2021-03-12 | 昆山国显光电有限公司 | Shift register and display panel |
| CN112802422B (en) * | 2021-01-29 | 2022-06-10 | 云谷（固安）科技有限公司 | Shift register, grid drive circuit and display panel |
| CN112927644B (en) * | 2021-02-02 | 2022-08-23 | 合肥维信诺科技有限公司 | Gate drive circuit and display panel |
| CN112967652B (en) * | 2021-03-08 | 2023-05-02 | 武汉天马微电子有限公司 | Scanning signal circuit, display panel, display device and driving method |
| CN113362761B (en) * | 2021-06-25 | 2022-09-06 | 合肥维信诺科技有限公司 | Display driving circuit and display panel |
| CN114299883B (en) * | 2021-12-31 | 2023-02-28 | 云谷（固安）科技有限公司 | Scanning drive circuit, display panel and display device |
| CN115294915B (en) * | 2022-08-29 | 2023-07-18 | 惠科股份有限公司 | Gate driving circuit and display device |
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