KR20070109387A - Shift register of lcd and driving method of the same - Google Patents

Abstract

A shift register of an LCD(Liquid Crystal Display) device and a driving method thereof are provided to prevent coupling and deteriorating phenomena of a transistor by implementing a shift register driven by a four phase clock signal. A pull-up driver(101) includes first and second transistors(T1,T2). The first transistor, which is connected between a first source voltage stage and a Q node, is turned on according to a gate driving signal of a previous stage. The second transistor, which is connected between a first clock signal stage and a main gate driving signal stage, is turned on according to an output of the Q node. A pull-down driver(102) includes third and fourth transistors(T3,T4). The third transistor, which is connected between the Q node and a second source voltage stage, is turned on according to a gate driving signal of a next stage. The fourth transistor, which is connected between the second source voltage stage and the main gate driving signal stage, is turned on according to an output of a second clock signal stage. An auxiliary driver(104), which is connected between the Q node and the main gate driving signal stage, is turned on according to an output of the first clock signal stage.

Description

Shift register of LCD and driving method thereof {Shift register of LCD and driving method of the same}

1 is a block diagram schematically illustrating a structure of a general GIP type liquid crystal display device.

FIG. 2A is a block diagram schematically illustrating a structure of the gate driving circuit of FIG. 1.

FIG. 2B is a waveform diagram schematically illustrating waveforms of some signals used in the gate driving circuit of FIG. 2A.

FIG. 3A is a circuit diagram showing one stage circuit in a shift register of a liquid crystal display device using a four-phase clock signal of the first conventional art.

FIG. 3B is a waveform diagram specifically illustrating waveforms of important signals among signals input and output to the stage circuit of FIG. 3A.

Fig. 4A is a circuit diagram showing one stage circuit in the shift register of the liquid crystal display device using the four-phase clock signal of the second prior art.

FIG. 4B is a waveform diagram illustrating in detail the waveforms of the important signals among the signals input and output to the stage circuit of FIG. 4A.

5A is a circuit diagram showing one stage circuit of the shift register according to the first embodiment of the present invention.

5B is a waveform diagram showing waveforms of important signals among signals inputted and outputted to one stage circuit of the shift register according to the first embodiment of the present invention.

5C is a waveform diagram schematically illustrating a waveform of a signal having an overlapped signal form used in a gate driving circuit.

FIG. 6 is a circuit diagram schematically illustrating another connection structure of the pull-down driver fourth transistor in the stage circuit of FIG. 5A.

FIG. 7A is a circuit diagram schematically illustrating a connection structure of a pull-up driver first transistor in the stage circuit of FIG. 5A.

FIG. 7B is a circuit diagram schematically illustrating T1-1 and T1-2 transistors having a connection structure different from that of the first transistor of the pull-up driver in the stage circuit of FIG. 5A.

FIG. 7C is a circuit diagram schematically illustrating T1-1 and T1-2 transistors having another connection structure with the first transistor of the pull-up driver in the stage circuit of FIG. 5A.

8 is a circuit diagram showing one stage circuit of a shift register according to a second embodiment of the present invention.

9 is a circuit diagram showing one stage circuit of the shift register according to the third embodiment of the present invention.

10 is a circuit diagram showing one stage circuit of a shift register according to a fourth embodiment of the present invention.

<Brief description of the main parts of the drawing>

VDD: first power supply voltage VSS: second power supply voltage

CLK1 to CLK4: first and fourth clock signals

VstN: Start signal of Nth stage circuit

VoutN: Gate driving signal of Nth stage circuit

101: pull-up drive unit 102: pull-down drive unit

104: auxiliary drive unit Q, Qb: Q-node and Qb-node

T1 to T5: first to fifth transistors

The present invention relates to a shift register of a liquid crystal display device and a driving method thereof, and more particularly, to a shift resistor that prevents coupling due to driving an amorphous thin film transistor and removes deterioration of the thin film transistor and provides a stable output.

In general, a liquid crystal display device is a flat panel display device that controls the light transmittance of a liquid crystal cell on a liquid crystal panel by forming an electric field in the liquid crystal materials arranged in a specific shape, thereby changing the arrangement of the liquid crystal material, and displays a corresponding image. .

Such a liquid crystal display device includes a driving circuit for converting RGB data and various control signals input from an external system into an appropriate electrical signal and a liquid crystal panel showing the user through the liquid crystal panel. In general, the driving circuit is a PCB substrate separate from the liquid crystal panel. Is produced on.

In such a liquid crystal display device, a liquid crystal display device having a gate in panel (GIP) method has recently been proposed in which the driving circuit is mounted in a liquid crystal panel to reduce manufacturing cost and minimize power consumption.

FIG. 1 is a view illustrating a conventional GIP type liquid crystal display. Referring to FIG. 1, a plurality of gate lines GL and data lines DL intersect and are arranged in the liquid crystal panel 1. The pixel is positioned at the intersection of the GL and the data line DL. Such a pixel includes a thin film transistor (TFT), which is a switching element, and a pixel electrode connected to the TFT. In this case, the TFT receives a signal from the gate line GL and performs a switching operation, and electrically connects the data line DL and the pixel electrode.

The gate driving circuit 2 sequentially supplies a gate driving signal to the gate line GL so that the pixels on the liquid crystal panel 1 are selected one horizontal line. In addition, the data driving circuit 3 supplies an RGB data signal to the data line DL whenever the gate line GL is sequentially selected. Accordingly, the image is displayed by adjusting the light transmittance of the liquid crystal layer by an electric field formed between the pixel electrode and the common electrode according to the data signal supplied for each pixel.

The gate driver circuit 2 of the GIP type liquid crystal display device is configured on the liquid crystal panel 1 through the same process as the TFT of the pixel, and the data driver circuit 3 may or may not be configured on the liquid crystal panel. It may be.

FIG. 2A is a block diagram schematically illustrating the configuration of a gate driver circuit in a GIP type liquid crystal display. Referring to FIG. 2A, the gate driver circuit 2 includes N stage circuits that receive and drive four clock signals. It includes a shift register.

Among the stage circuits, the first stage circuit receives the first clock signal CLK1 and the start signal VstN from the outside and outputs the gate driving signal Vout1 on the first horizontal line, and the Nth shift register is N−. The gate driving signal Vout (N-1) of the first shift register is input as the start signal VstN, and the Nth gate driving signal VoutN is output. That is, as shown in FIG. 2B, when the start signal VstN is input, the first clock signal CLK1 to the fourth clock signal CLK4 are input in the form of swinging sequentially. The drive signal VoutN is output.

FIG. 3A is a circuit diagram illustrating one stage circuit in a shift register of a liquid crystal display device using a four-phase clock signal of FIG. 1, and FIG. 3B is a diagram illustrating some signal types among signals input to the stage circuit of FIG. 3A. This is a waveform diagram.

Referring to FIG. 3A, the N-th stage circuit of the shift register includes a pull-up driver 11 including first and second transistors T1 and T2, and third and fourth transistors T3 and T4. And a pull-down driver 12 for receiving the first power supply voltage VDD, the second power supply voltage VSS, the first to fourth clock signals CLK1 to CLK4, and the start signal VstN. It is structured.

Referring to the driving of the N-th stage circuit, a high level start signal VstN is first input to the gate of the first transistor T1 of the pull-up driver 11 and the first transistor T1. Is turned on to charge the capacitor (C) connected to the Q-node (Q). Thereafter, when the capacitor C is charged above the threshold voltage between the gate and the source of the second transistor T2, and the first clock signal CLK1 becomes high, a bootstrapping occurs. The Q-node (Q) charges up to about 40V to a certain high level. Accordingly, the second transistor T2 is turned on and generates the high level gate driving signal VoutN. The gate drive signal VoutN at this time is a start signal Vst (N + 1) of the next stage N + 1 stage circuit and a signal {Vout for driving the pull-down driving unit of the previous stage N-1 stage circuit. (N-1)}.

Subsequently, when the gate driving signal Vout (N + 1) is input to the third and fourth transistors T3 and T4 of the pull-down driver 12 from the next N + 1 stage circuit, the third transistor ( T3 is turned on so that the Q-node Q is discharged to a low level, and the second transistor T2 is turned off. In addition, when the gate driving signal Vout (N + 1) is input to the fourth transistor T4, the fourth transistor T4 is turned on so that the gate driving signal VoutN becomes a low level. Afterwards, when the fourth transistor T4 is turned off, the gate driving signal VoutN terminal continues to float until the next frame is scanned. Therefore, this gate drive signal VoutN is kept at a low level.

As shown in FIG. 3B, the shift register having the above-described configuration has the first clock signal CLK1 in the pull-up driver 11 due to internal capacitance or the like between the gate and the source of the second transistor T2. Coupling noise was generated whenever the high level was reached. Accordingly, a malfunction of the circuit occurs due to the swing of the first clock signal CLK1.

FIG. 4A is a circuit diagram showing one stage circuit in a shift register of a liquid crystal display device using a second conventional four-phase clock signal proposed to solve the coupling phenomenon described above, and FIG. 4B is a diagram of the shift register. This is a waveform diagram showing waveforms of some signals among the signals inputted and outputted to the.

Referring to FIG. 4A, the N-th stage circuit of the shift register includes a pull-up driver 21 including first and second transistors T1 and T2, and 3-1 and 3-2 transistors T3-. A first pull-down driver 22 including 1 to T3-2, and a second pull-down driver 23 including third and third-4 transistors T3-3 and T3-4. ), And a structure in which the first and second power supply voltages VDD and VSS and the clock signals CLK1 to CLK4 are input, are the same as the first conventional technology.

Referring to the operation of the N-th stage circuit of the other prior art, first, when the start signal VstN is input to the first transistor T1 of the pull-up driver 21 constituted by the diode method, The first transistor T1 is turned on so that the Q-node Q is charged to a high level. Accordingly, the first capacitor C1 is charged and the Qb-node Qb is discharged to a low level by the 3-4 transistor T3-4 of the second pull-down driver 23. do. When the first capacitor C1 is charged above the threshold voltage between the gate and the source of the third-second transistor T3-2, and then the first clock signal CLK1 becomes high, bootstrapping is performed. Bootstraping occurs, causing the Q-node (Q) to charge to a certain high level of about 40V. Accordingly, the second transistor T2 is turned on and generates the high level gate driving signal VoutN. At this time, the gate driving signal VoutN includes the start signal Vst (N + 1) of the next stage N + 1 stage circuit and the first and second pull-down driving units 22 of the front stage N-1 stage circuit. And a driving signal Vout (N-1) for driving the.

Accordingly, the second transistor T2 of the first pull-down driver 22 and the third-3 transistor T3-3 of the second pull-down driver 23 are removed from the next N + 1 stage circuit. The gate driving signal Vout (N + 1) is input so that the voltage level of the Q-node Q is at a low level, and the second capacitor C2 is connected to the 3-2 transistor T3-2 and the second capacitor C2. When charged above the threshold voltage between the gate and the source of the fourth transistor T4, the Qb-node Qb rises to a high level. Accordingly, the third-second transistor T3-2 and the fourth transistor T4 of the first pull-down driver 22 are turned on, and the Q-node (the third transistor T3-2) is turned on. The coupling noise voltage generated at Q) is discharged, and the fourth transistor T4 generates the gate driving signal VoutN having a low level. The gate drive signal VoutN is then maintained at a low level voltage until the next frame is scanned.

As shown in FIG. 4B, the shift register having such a configuration is coupled to the pull-up driver 21 and the second transistor T2 according to the first clock signal CLK1 swinging between −5v and 20v. The noise voltage of the Q-node Q due to the coupling phenomenon is prevented by the 3-2 transistor T3-2 of the first pull-down driver 22.

However, the shift register circuit driven in the above manner is subjected to different bias stresses depending on the role of the TFT, and this bias stress causes a threshold voltage shift, thereby improving reliability of circuit operation. Will be degraded.

In particular, in the configuration of the stage circuit shown in FIG. 4A, the third-2 transistor T3-2 and the fourth transistor T4 of the first pull-down driver 22 are one frame by the Qb-node Qb. This causes the most severe characteristic change in output during the operating cycle.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a shift register of a liquid crystal display device which prevents coupling in a shift register that operates with a clock of at least four phases and improves characteristics change due to transistor degradation. Its purpose is.

In order to achieve the above object, the present invention, as a first embodiment ,

A liquid crystal display for generating a signal corresponding to an output signal of the first to fourth clock signal terminals, the first power voltage terminal and the second power voltage terminal, and the start signal terminal to which the front gate driving signal is input, through the gate driving signal terminal. The driving circuit of claim 1, further comprising: a first transistor electrically connected between the first power supply voltage terminal and a Q-node, the first transistor configured to determine whether to turn on a start signal to which a gate driving signal of a front stage is input, and the first clock; A pull-up driver electrically connected between the signal terminal and the main gate driving signal terminal, the pull-up driving unit comprising a second transistor configured to determine whether to turn on the output of the Q-node; A third transistor electrically connected between the Q-node and the second power supply voltage terminal and configured to be turned on by a gate driving signal of a next stage stage, the second power supply voltage terminal and the main gate driving signal terminal; A pull-down driver electrically connected between the fourth transistor and a fourth transistor configured to determine whether to turn on the output of the second clock signal terminal; The stage includes an auxiliary driver configured to be electrically connected between the Q-node and the main gate driving signal terminal, and includes a fifth transistor configured to determine whether to turn on the output of the first clock signal terminal. A shift register of a liquid crystal display device is proposed.

As a second embodiment of the present invention,

A liquid crystal display for generating a signal corresponding to an output signal of the first to fourth clock signal terminals, the first power voltage terminal and the second power voltage terminal, and the start signal terminal to which the front gate driving signal is input, through the gate driving signal terminal. The driving circuit of claim 1, further comprising: a first transistor electrically connected between the first power supply voltage terminal and a Q-node, the first transistor configured to determine whether to turn on a start signal to which a gate driving signal of a front stage is input, and the first clock; A pull-up driver electrically connected between the signal terminal and the main gate driving signal terminal, the pull-up driver including a second transistor configured to determine whether to turn on the output of the Q-node; 3-1 and 3-2 transistors electrically connected between the Q-node and the second power supply voltage terminal and configured to be turned on by a gate driving signal of a next stage stage, and the second power supply voltage; A pull-down driving unit electrically connected between the terminal and the main gate driving signal terminal and configured to include a fourth transistor configured to determine whether to turn on the output of the second clock signal terminal; The stage includes an auxiliary driver configured to be electrically connected between the Q-node and the main gate driving signal terminal, and includes a fifth transistor configured to determine whether to turn on the output of the first clock signal terminal. A shift register of a liquid crystal display device is proposed.

As a third embodiment of the present invention,

A liquid crystal display for generating a signal corresponding to an output signal of the first to fourth clock signal terminals, the first power voltage terminal and the second power voltage terminal, and the start signal terminal to which the front gate driving signal is input, through the gate driving signal terminal. The driving circuit of claim 1, further comprising: a first transistor electrically connected between the first power supply voltage terminal and the Q-node, the first transistor configured to determine whether to turn on the gate driving signal of a previous stage, the first clock signal terminal, and the main gate driving; A pull-up driver electrically connected between signal terminals, the pull-up driver including a second transistor configured to determine whether to turn on the output of the Q-node; 3-1 and 3-2 transistors electrically connected between the Q-node and the second power supply voltage terminal and configured to be turned on by a gate driving signal of a next stage stage, and the second power supply voltage; A 4-1 transistor electrically connected between the terminal and the main gate driving signal terminal and determining whether to turn on the output of the second clock signal terminal, and between the second power voltage terminal and the main gate driving signal terminal. A pull-down driver electrically connected to the 4th transistor, the pull-down driver configured to turn on the gate driving signal of the front end stage; The stage includes an auxiliary driver configured to be electrically connected between the Q-node and the main gate driving signal terminal, and includes a fifth transistor configured to determine whether to turn on the output of the first clock signal terminal. A shift register of a liquid crystal display device is proposed.

As a fourth embodiment of the present invention,

A liquid crystal display for generating a signal corresponding to an output signal of the first to fourth clock signal terminals, the first power voltage terminal and the second power voltage terminal, and the start signal terminal to which the front gate driving signal is input, through the gate driving signal terminal. The driving circuit of claim 1, further comprising: a first transistor electrically connected between the first power supply voltage terminal and the Q-node, the first transistor configured to determine whether to turn on the gate driving signal of a previous stage, the first clock signal terminal, and the main gate driving; A pull-up driver electrically connected between signal terminals, the pull-up driver including a second transistor configured to determine whether to turn on the output of the Q-node; 3-1 and 3-2 transistors electrically connected between the Q-node and the second power supply voltage terminal and configured to be turned on by a gate driving signal of a next stage stage, and the second power supply voltage; A 4-1 transistor electrically connected between the terminal and the main gate driving signal terminal, and having a turn-on state determined at an output of the Qb node; and electrically connected between the first power voltage terminal and the Qb node. And a 4-2 transistor configured to determine whether the output of the second clock signal stage is turned on, and electrically connected between the Qb-node and the second power voltage terminal, and turn on the output of the fourth clock signal stage. A pull-down driver configured as a 4-3 transistor whose on or off is determined; The stage includes an auxiliary driver configured to be electrically connected between the Q-node and the main gate driving signal terminal, and includes a fifth transistor configured to determine whether to turn on the output of the first clock signal terminal. A shift register of a liquid crystal display device is proposed.

Here, the common features of the first to fourth embodiments,

The first power supply voltage is a high level power supply voltage or a signal having a voltage level equal to or higher than the high level power supply voltage; The second power supply voltage is a shift register of a liquid crystal display device, characterized in that a low level ground voltage or a signal of a voltage level below the low level ground voltage.

A shift register of a liquid crystal display device is characterized in that each transistor is an N type amorphous silicon thin film transistor.

The pull-up driving unit may include: a 1-1 transistor configured to be turned on at an output of the start signal terminal and configured in a diode manner; The first-first transistor and the Q-node Q are electrically connected to each other, and the first-second transistor having a turn-on state determined at an output of the clock signal terminal is replaced with the first transistor. A shift register of a liquid crystal display device is proposed.

The pull-up driving unit includes: a 1-1 transistor electrically connecting the first power voltage terminal and the Q-node and determining whether to turn on the output of the start signal terminal; A first-second transistor electrically connecting the first power voltage terminal to the Q-node and determining whether to turn on the output of the clock signal terminal; The shift register of the liquid crystal display device according to claim 1, wherein the first-first transistor and the first-second transistor are connected in parallel and are configured in place of the first transistor.

In addition, as a common feature of the second to fourth embodiments,

The 3-2 transistor proposes a shift register of a liquid crystal display, characterized in that the turn-on is determined by an output signal of the second to fourth clock signal terminals.

In addition, as a common feature of the first to second embodiments,

When the outputs of the first to fourth clock signal stages overlap each other, the fourth transistor of the pull-down driving unit is determined to be turned on by the output of the third clock signal stage. A shift register of a display device is proposed.

Also, as a feature of the third embodiment,

When the outputs of the first to fourth clock signal stages overlap each other, whether the 4-1 transistor of the pull-down driver is turned on by the output of the third clock signal stage, The 4-2 transistor proposes a shift register of a liquid crystal display device, characterized in that the transistor is turned on by the output of the gate driving signal terminal after the next stage.

Also, as a feature of the fourth embodiment,

When the outputs of the first to fourth clock signal stages overlap each other, whether the 4-2 transistor of the pull-down driver is turned on by the output of the third clock signal stage, The 4-3 transistor proposes a shift register of a liquid crystal display device, characterized in that the transistor is turned on by the output of the gate driving signal terminal after the next stage.

In the following description, an example of an N-th stage circuit in which a first transistor of a pull-up driver receives and drives a first clock signal will be described. Therefore, when the first transistor of the next stage stage circuit is an N + 1st stage circuit that receives and drives a second clock signal, the transistors that receive and drive the second clock signal in the Nth stage circuit input a third clock signal. It is a receiving structure.

In addition, the first stage circuit receives and drives the start signal from the outside, and the remaining stage circuits are driven by receiving the gate drive signal of the front stage circuit as the start signal.

In addition, each transistor is implemented as an N type amorphous thin film transistor mounted in a liquid crystal panel.

First embodiment

Hereinafter, the structure of the shift register according to the first embodiment of the present invention will be described with reference to FIG. 5A.

Referring to the features of the structure, the first pull-up driver 101 including the first transistor T1 and the second transistor T2, the auxiliary driver 104 including the fifth transistor T5, The pull-down driver 102 includes a third transistor T3 and a fourth transistor T4. In this case, the pull-up driving unit 101 receives the start signal VstN from the first transistor T1 and turns on the second transistor T2 with the first power voltage VDD, thereby providing a first clock signal. The gate driving signal VstN of high level is generated through CLK1. In addition, the pull-down driver 102 receives the gate driving signal Vst (N + 1) from the next stage (N + 1) stage and receives the second transistor T2 of the pull-up driver 101. The turn-off and the second clock signal CLK2 are input to turn on the fourth transistor T4 to generate the gate driving signal VoutN having a low level through the second power voltage VSS. The auxiliary driver 104 is configured to prevent coupling of the second transistor T2.

The start signal VstN and the clock signals CLK1 to CLK4 are signals having the same period and waveform as those of the conventional shift register of FIG. 2B.

Looking at the operation of the shift register according to the first embodiment of the present invention having the characteristics of such a structure as follows.

First, when the start signal VstN is input to the gate terminal of the first transistor T1 of the pull-up driving unit 101, the first transistor T1 is turned on so that the first power supply voltage VDD is Q−. The node Q is charged. When the Q-node Q is charged above the threshold voltage between the gate and the source of the second transistor T2 and the first clock signal CLK1 becomes high, a bootstrapping phenomenon occurs and a second transistor is generated. T2 and the fifth transistor are turned on. Accordingly, a high level gate driving signal VoutN is generated through the second transistor T2 and the fifth transistor T5 of the auxiliary driver 104. That is, since the fifth transistor T5 is also turned on by the first clock signal CLK1 and the Q-node Q connected to the input terminal is also currently at a high level, the second transistor T2 is turned on. And the fifth transistor T5 are both driven by a pull-up element.

The gate driving signal VoutN is used to drive the start signal Vst (N + 1) of the next stage N + 1 stage circuit and the pull-down driver 102 of the stage N-1 stage circuit. The driving signal Vout (N-1) is inputted.

Subsequently, when the pull-down driving signal Vout (N + 1) is input from the next stage N + 1 stage circuit to the third transistor T3 of the pull-down driving unit 102, the third transistor T3. Is turned on, so that the Q-node Q discharged to the second power supply voltage VSS level becomes a low level, and the second transistor T2 is turned off.

In addition, when the second clock signal CLK2 becomes high, the Qb-node Qb connected to the fourth transistor T4 rises to a high level, and accordingly, the pull-down driver The fourth transistor T4 of 102 is turned on to generate a gate driving signal VoutN of a low level. After that, the gate driving signal VoutN is continuously maintained until the next frame is scanned.

Herein, a coupling phenomenon occurs due to the swing of the first clock signal CLK1 in the second transistor T2 of the pull-up driving unit 101, which causes noise to the Q-node Q. The voltage is charged. At the same time, the fifth transistor T5 of the auxiliary driver 104 connected to the second transistor T is turned on by the first clock signal CLK1, and the fifth transistor T5 is turned on by the fifth transistor T5. The coupling noise voltage generated at the Q-node Q is discharged. As a result, the Q-node Q is maintained at a low level and is in a stable state.

Referring to FIG. 5B, when the start signal VstN is input, the Q-node Q is charged to about 20V, and when the clock signal CLKN becomes high, bootstrapping is performed to Q-node Q. Is charged to about 40V. When the clock signal CLKN swings at a voltage level between -5V and 20V, a noise voltage due to coupling is generated, but is discharged by the fifth transistor T5.

Accordingly, the shift register according to the first embodiment of the present invention is prevented from malfunctioning of the circuit due to coupling and deterioration of the transistor due to continuous bias stress.

The above embodiment exemplifies only a case in which a square wave clock signal of a simple type that does not overlap with each other is used, but a pull-down having the following configuration applicable to a case where a square wave clock signal of a form in which the clock signal overlaps is used Present part of the drive.

More specifically, when the overlapped clock signals CLK1 to CLK4 of FIG. 5C are used in the shift register, the third transistor T3 of the pull-down driving unit starts from the next stage (N + 1) stage. Upon receiving {Vst (n + 1)}, the third transistor of the pull-down driving unit must be delayed and driven as much as overlapped. Therefore, as illustrated in FIG. 6, a shift register in which an overlapped clock signal is used is used. In FIG. 4, the fourth transistor T4 of the pull-down driver may be configured to receive the fourth clock signal CLK3.

In addition, as shown in FIG. 7A, the first transistor T1 of the pull-up driving unit 101 (in FIG. 5A) has a start signal VstN terminal connected to a gate, and a first power supply voltage VDD. Although only the configuration in which the stage and the source are connected, the pull-up driving unit may be configured in more various forms. In particular, in the above embodiment, the Q-node is charged under the control of the control signal VstN, but the pull-up driving unit under the control of the clock signal CLKN is synchronized with the control signal. present.

More specifically, as shown in FIG. 7B, the first-first transistor T1-1 is diode-connected to the start signal VstN, and the first-second transistor T1-2 is connected to the first first transistor. It may be configured to receive the output of the -1 transistor (T1-2) to output a signal under the control of the clock signal (CLKN) stage.

In addition, as shown in FIG. 7C, the first-first transistor T1-1 and the first-second transistor T1-2 of the pull-up driving unit are connected in parallel, and the first power supply voltage VDD is connected to each other. It may be configured to receive a signal and output a signal under the control of the start signal terminal VstN and the clock signal CLKN, respectively.

Accordingly, the pull-up driving unit including the first-first transistor T1-1 and the first-second transistor T1-2 corresponds to the clock signal CKLN in synchronization with the start signal VstN. The node Q will be charged.

Second embodiment

FIG. 8 is a diagram showing a shift register according to a second embodiment of the present invention, in which the discharge characteristics of the Q-node are further improved during operation. Hereinafter, a structure of a second embodiment of the present invention will be described with reference to FIG. 8.

Looking at the characteristics of the structure, the first pull-up driver 111 including the first transistor (T1) and the second transistor (T2), the auxiliary driver (114) including the fifth transistor (T5), The pull-down driver 112 includes a 3-1 transistor T3-1, a 3-2 transistor T3-2, and a fourth transistor T4. In this case, the pull-up driving unit 111 receives the start signal VstN from the first transistor T1 and turns on the second transistor T2 with the first power voltage VDD, thereby providing a first clock signal. A gate driving signal VoutN having a high level is generated through CLK1, and the pull-down driving unit 112 includes three transistors T3-1, T3-2, and T4. The second transistor of the pull-up driver 111 receives the gate driving signal Vout (N + 1) and the N + 1 clock signal CLK (N + 1) from the next stage (N + 1) stage. The T2 is turned off, the second clock signal CLK2 is input, the fourth transistor T4 is turned on, and the gate driving signal having a low level is applied through the second power voltage VSS. VoutN), and the auxiliary driver 114 prevents the coupling phenomenon of the second transistor T2.

The start signal VstN and the clock signals CLK1 to CLK4 are signals having the same period and waveform as those of the conventional shift register of FIG. 2B.

Looking at the operation of the shift register according to the second embodiment of the present invention having the characteristics of such a structure as follows.

First, when the start signal VstN is input to the first transistor T1 of the pull-up driving unit 111, the first transistor T1 is turned on so that the first power supply voltage VDD is a Q-node ( Q) is charged. When the Q-node Q is charged above the threshold voltage between the gate and the source of the second transistor T2, and the first clock signal CLK1 becomes high, a bootstrapping phenomenon occurs and a second transistor is generated. (T2) is turned on. Subsequently, when the first clock signal CLK1 having a high level is input to the second transistor T2 and the fifth transistor T5, the gate driving signal VoutN is generated through the second transistor T2. . At this time, the fifth transistor T5 is also turned on by the first clock signal CLK1, and since the Q-node Q is currently at a high level, the second transistor T2 and the fifth transistor T5 are turned on. Are all driven by pull-up devices.

The gate driving signal VoutN is a driving signal for driving the start signal Vst (N + 1) of the next stage N + 1 stage stage circuit and the pull-down driving unit 112 of the previous stage N-1 stage circuit. It is input as the signal Vout (N-1)}.

Subsequently, when a pull-down driving signal Vout (N + 1) is input from the next N + 1 stage stage circuit to the 3-1 transistor T3-1 of the pull-down driving unit 112, the third-first transistor T3-1 is inputted to the third-1 transistor T3-1. The transistor T3-1 is turned on, so that the Q-node Q discharged to the second power supply voltage VSS level is at a low level, and the second transistor T2 is turned on. It will be off.

At this time, the third-second transistor T3-2 further included in the pull-down driving unit 112 is pull-down driving signal Vout (N + 1) or the first from the next stage N + 1 stage circuit. The N + 1 clock signal CLK (N + 1) is input to discharge the Q-node Q to a low level at the same time as the 3-1 transistor T3-1. As a result, the Q-node Q is discharged more stably.

Here, although the third-second transistor T3-2 receives the N + 1 th clock signal CLK (N + 1) and is driven simultaneously, the N-2 th transistor T3-2 is driven. (N + 1)} is a clock signal CLK2 to CLK4 other than the first clock signal CLK1 used as the input of the pull-up driving unit 111, and the gate driving signal {of the next stage (N + 1) stage { Vout (N + 1)}.

Subsequently, when the second clock signal CLK2 is input to the fourth transistor T4, the voltage level of the Qb-node Qb rises to a high level, and thereafter, the fourth clock of the pull-down driver 112 is applied. The transistor T4 is turned on to generate a gate driving signal VoutN of a low level. After that, the gate driving signal VoutN is continuously maintained until the next frame is scanned.

In this case, coupling occurs due to the swing of the first clock signal CLK1 in the second transistor T2 of the pull-up driving unit 111, which causes noise to the Q-node Q. The voltage is charged. At the same time, the fifth transistor T5 of the auxiliary driver 114 connected to the gate terminal of the second transistor is turned on by the first clock signal CLK1, thereby charging the Q-node Q. The noise voltage is discharged.

In addition, when the square wave clock signal having the overlapping shape of the clock signal CLKN is used, the pull-down driver 112 has a third gate of the fourth transistor T4 as shown in FIG. 6. The clock signal CLK3 may be input.

In addition, as shown in FIG. 7B, the first transistor T1 of the pull-up driver 111 may further include a diode type 1-1 transistor T1-1 and the diode type. The first-first transistor T1-1 may be replaced with the first-second transistor T1-2 for controlling the output.

In addition, as illustrated in FIG. 7C, the first transistor T1 of the pull-up driver 111 is connected in parallel with the first-first transistor T1-1 and the first-second transistor T1-2. The first power supply voltage VDD may be output to correspond to the signals output from the start signal VstN and the clock signal CLKN.

Third embodiment

9 is a diagram illustrating a shift register according to a third embodiment of the present invention, in which the discharge characteristics of the Qb-node Qb are further improved. Hereinafter, a structure of a third embodiment of the present invention will be described with reference to FIG. 9.

Referring to the characteristics of the structure, the pull-up driver 121 including the first transistor (T1) and the second transistor (T2), the auxiliary driver 124 including the fifth transistor (T5), and the third- Pull-down driver including one transistor T3-1, third-2 transistor T3-2, fourth-1 transistor T4-1, and fourth-2 transistor T4-2. Consisting of 122. In this case, the pull-up driving unit 121 receives the start signal VstN from the first transistor T1 and turns on the second transistor T2 with the first power voltage VDD. A gate driving signal VoutN having a high level is generated through CLK1, and the pull-down driver 122 includes four transistors T3-1, T3-2, T4-1, and T4-. 2), the gate driving signal {Vout (N + 1)} is input from the next stage (N + 1) stage, and the second transistor T2 of the pull-up driving unit 121 is turned off. The second clock signal CLK2 is input to turn on the 4-1 transistor T4-1 to generate a gate driving signal VoutN having a low level through the second power supply voltage VSS. The auxiliary driver 124 is a structure for preventing the coupling of the fifth transistor T5.

The start signal VstN and the clock signals CLK1 to CLK4 are signals having the same period and waveform as those of the conventional shift register of FIG. 2B.

Looking at the operation of the shift register according to the third embodiment of the present invention having the feature of such a structure as follows.

First, when the start signal VstN is input to the first transistor T1 of the pull-up driving unit 121, the first transistor T1 is turned on so that the first power supply voltage VDD is a Q-node Q. ) Is charged. When the Q-node Q is charged above the threshold voltage between the gate and the source of the second transistor T2 and the first clock signal CLK1 becomes high, a bootstrapping phenomenon occurs and a second transistor is generated. (T2) is turned on. Thereafter, when the first clock signal CLK1 is input to the second transistor T2 and the fifth transistor T5 of the auxiliary driver 124, the gate driving signal having a high level through the second transistor T2 ( VoutN) is generated. At this time, the fifth transistor T5 is also turned on by the first clock signal CLK1, and the Q-node Q connected to the fifth transistor T5 is also currently high. Both the second transistor T2 and the fifth transistor T5 are driven by a pull-up device.

The gate driving signal VoutN is used to drive the start signal Vst (N + 1) of the next stage N + 1 stage circuit and the pull-down driver 122 of the previous stage N-1 stage circuit. It is input as the signal Vout (N-1)}.

Subsequently, when the pull-down driving signal Vout (N + 1) is input from the next stage N + 1 stage circuit to the 3-1 transistor T3-1 of the pull-down driving unit 122, the third-first transistor T3-1 is inputted. The -1 transistor T3-1 is turned on, so that the Q-node Q discharged to the second power supply voltage VSS level becomes a low level so that the second transistor T2 It will be turned off.

In this case, the third-second transistor T3-2 further provided in the pull-down driving unit 122 may have a pull-down driving signal Vout (N + 1) or a first from the next stage N + 1 stage circuit. The N + 1 clock signal CLK (N + 1) is input to discharge the Q-node Q to a low level at the same time as the 3-1 transistor T3-1. As a result, the Q-node Q is discharged more stably.

Here, although the third-second transistor T3-2 is driven by receiving an N + 1 th clock signal CLK (N + 1), the N-2 th transistor T3-2 is driven. N + 1)} is another clock signal CLK2 to CLK4 other than the first clock signal CLK1 used as the input of the pull-up driving unit 121 and the gate driving signal Vout of the next stage N + 1 stage. (N + 1)}.

Thereafter, the second clock signal CLK2 is input to the 4-1 transistor T4-1, and the gate driving signal Vout (N + 1) of the next stage N + 1 stage is 4-2. When input to the transistor T4-2, the fourth-first transistor T4-1 and the fourth-second transistor T4-2 of the pull-down driving unit 112 are turned on to have a low level. The gate drive signal VoutN is generated. After that, the gate driving signal VoutN is continuously maintained until the next frame is scanned.

In this case, a coupling phenomenon occurs due to the swing of the first clock signal CLK1 in the second transistor T2 of the pull-up driver 121, which causes noise to the Q-node Q. The voltage is charged. At the same time, the fifth transistor T5 of the auxiliary driver 124 connected to the gate terminal of the second transistor is turned on by the first clock signal CLK1, thereby charging the Q-node Q. The noise voltage is discharged.

In addition, when a square wave clock signal having an overlapping shape of the clock signal CLKN is used, the pull-down driving unit 122 has a configuration of the 4-1 transistor T4-1 as shown in FIG. The gate may be configured to receive the third clock signal CLK3. Accordingly, the 4-2 transistor T4-2 operating in synchronization with the 4-1 transistor T4-1 has the gate driving signal Vout (N + 2) of the next stage (N + 2) stage. It may be configured in the form of receiving.

In addition, as shown in FIG. 7B, the first transistor T1 of the pull-up driving unit 121 is a diode type 1-1 transistor T1-1 and the diode type. It may be configured by being replaced by the 1-2 transistor T1-2 for controlling the output of the first-first transistor.

In addition, as illustrated in FIG. 7C, the first transistor T1 of the pull-up driver 121 is connected in parallel with the first-first transistor T1-1 and the first-second transistor T1-2. The first power supply voltage VDD may be output to correspond to the signals output from the start signal VstN and the clock signal CLKN.

4th Example

FIG. 10 is a diagram illustrating a shift register according to a fourth embodiment of the present invention, in which the sizes of the fourth transistors of the first and second embodiments are reduced. Hereinafter, a structure of a fourth embodiment of the present invention will be described with reference to FIG. 10.

Referring to the characteristics of the structure, the pull-up driver 131 including the first transistor T1 and the second transistor T2, the auxiliary driver 134 including the fifth transistor T5, and the third transistor And a pull-down driving unit 132 including T1 and 4-1 to 4-3 transistors T4-1 to T4-3. In this case, the pull-up driving unit 131 receives the start signal VstN from the first transistor T1 and turns on the second transistor T2 with the first power voltage VDD, thereby providing a first clock signal. A gate driving signal VoutN having a high level is generated through CLK1, and the pull-down driving unit 132 includes four transistors T3, T4-1, T4-2, and T4-3. The second transistor T2 of the pull-up driver 131 is turned off by receiving the gate driving signal Vout (N + 1) from the next stage (N + 1) stage. The gate driving signal having a low level through the second power supply voltage VSS is turned on by receiving the clock signal CLK2 and the third clock signal CLK3. (VoutN) is generated, and the auxiliary driver 134 is a structure that prevents coupling of the fifth transistor T5.

In particular, in the above-described first and second embodiments, the fourth transistor (T4 of FIGS. 5A and 8) of the pull-down driving unit electrically connects the second power supply voltage VSS terminal and the main gate driving signal VoutN terminal. The size of the circuit is quite large. Accordingly, a plurality of TFTs are connected to the same clock signal in the entire stage circuit to act as a large capacitor load. In the fourth embodiment, the fourth-second transistor T4-2 and the fourth-3 transistor ( T4-3 controls the operation of the 4-1 transistor T4-1 so that the margin of the output signal required for driving is secured even if the size of the 4-1 transistor T4-1 is reduced. do. That is, when the size of the 4-1 transistor T4-1 is configured to be small, the turn-on period should be increased accordingly. For this purpose, in the fourth embodiment, the 4-1 transistor T4-1 is controlled. A separate transistor is further provided to secure more turn-on periods of the 4-1 transistor T4-1.

Here, the start signal VstN and the clock signals CLK1 to CLK4 are signals having the same period and waveform as those of the conventional shift register of FIG. 2B.

Looking at the operation of the shift register according to the fourth embodiment of the present invention having the characteristics of such a structure as follows.

First, when the start signal VstN is input to the first transistor T1 of the pull-up driving unit 131, the first transistor T1 is turned on so that the first power supply voltage VDD is a Q-node ( Q) is charged. When the Q-node Q is charged above the threshold voltage between the gate and the source of the second transistor T2 and the first clock signal CLK1 becomes high, a bootstrapping phenomenon occurs and a second transistor is generated. (T2) is turned on. Subsequently, when the first clock signal CLK1 is input to the second transistor T2 and the fifth transistor T5 of the auxiliary driver 134, the gate driving signal VoutN having a high level through the second transistor T2. ) Will occur. At this time, the fifth transistor T5 is also turned on by the first clock signal CLK1, and the Q-node Q connected to the fifth transistor T5 is also currently high. Therefore, both the second transistor T2 and the fifth transistor T5 are driven by a pull-up element.

The gate driving signal VoutN is used to drive the start signal Vst (N + 1) of the next stage N + 1 stage circuit and the pull-down driver 132 of the previous stage N-1 stage circuit. It is input as the signal Vout (N-1)}.

Subsequently, when the gate driving signal Vout (N + 1) is input from the next stage N + 1 stage circuit to the third transistor T3 of the pull-down driver 132, the third transistor T3 is turned on. On, the Q-node Q is low level through the second power supply voltage VSS to turn off the second transistor T2.

When the second clock signal CLK2 reaches the high level, the 4-2 transistor T4-2 is turned on so that the voltage level of the Qb-node Qb rises to the high level. Accordingly, the fourth-first transistor T4-1 of the pull-down driver 132 is turned on to generate the gate driving signal VoutN having a low level.

In addition, the second clock signal CLK2 is at a low level, and the fourth-second transistor T4-2 is turned off, and the fourth clock signal CLK4 is at a high level. The 4-3 transistor T4-3 is turned on to discharge the voltage level of the Qb-node Qb to a low level, and the 4-1 transistor T4-1 is turned off. . Accordingly, the gate driving signal VoutN is kept in a floating state until the next frame is scanned.

Here, the 4-2 and 4-3 transistors T4-2 and T4-3 may be driven by receiving an appropriate clock signal according to the size of the 4-1 transistor T4-1. In FIG. 10, an example in which the second clock signal CLK2 and the fourth clock signal CLK4 are input is described. However, the fourth and fourth transistors T4-2 and T4-3 are described. According to the size of the 4-1 transistor T4-1, additionally provided clock signals having an appropriate phase difference, the clock signals can be received and controlled.

In this case, coupling occurs due to the swing of the first clock signal CLK1 in the second transistor T2 of the pull-up driving unit 131, and therefore, noise is generated in the Q-node Q. The voltage is charged. At the same time, the fifth transistor T5 of the auxiliary driver 134 connected to the gate of the second transistor T2 is turned on by the first clock signal CLK1 and, accordingly, the Q-node Q The noise voltage charged in the) is discharged.

In addition, when a square wave clock signal having an overlapping shape of the clock signal CLKN is used, the pull-down driving unit 132 may be configured such that the fourth-2 transistor T4-2 is configured to include a third clock signal ( CLK3) may be configured to receive an input. Accordingly, the 4-2 transistor T4-2 receives a clock signal used in the next stage (N + 1) stage or additionally includes a clock signal having an appropriate phase difference and receives the clock signal. It may be configured in the form.

In addition, as shown in FIG. 7B, the first transistor T1 of the pull-up driving unit 131 provides a diode type first-first transistor T1-1 and the first transistor T1-1. It may be configured by being replaced by the 1-2 transistor T1-2 for controlling the output of the first-first transistor.

In addition, as illustrated in FIG. 7C, the first transistor T1 of the pull-up driver 131 is connected in parallel with the first-first transistor T1-1 and the first-second transistor T1-2. The first power supply voltage VDD may be output to correspond to the signals output from the start signal VstN and the clock signal CLKN.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art various modifications and variations of the present invention without departing from the spirit and scope of the present invention described in the claims below I can understand that you can.

Therefore, the shift register of the liquid crystal display according to the embodiment of the present invention prevents the coupling phenomenon of the thin film transistor for gate driving mounted in the liquid crystal panel and the deterioration due to the continuous bias voltage of the transistor for pull-down driving. This has the advantage.

That is, by further comprising an auxiliary driver to prevent the coupling phenomenon to prevent the malfunction of the circuit, and further includes a transistor for the pull-down drive, to ensure the normal operation of the circuit more stable and has the effect of extending the life of the circuit have.

Claims (27)

A liquid crystal display for generating a signal corresponding to an output signal of the first to fourth clock signal terminals, the first power voltage terminal and the second power voltage terminal, and the start signal terminal to which the front gate driving signal is input, through the gate driving signal terminal. In the driving circuit of A first transistor electrically connected between the first power supply voltage terminal and the Q-node and configured to determine whether to turn on the start signal to which the gate driving signal of the front stage is input, the first clock signal terminal and the main gate driving signal; A pull-up driver electrically connected between stages, the pull-up driver including a second transistor configured to determine whether to turn on the output of the Q-node; A third transistor electrically connected between the Q-node and the second power supply voltage terminal and configured to be turned on by a gate driving signal of a next stage stage, the second power supply voltage terminal and the main gate driving signal terminal; A pull-down driver electrically connected between the fourth transistor and a fourth transistor configured to determine whether to turn on the output of the second clock signal terminal; An auxiliary driver electrically connected between the Q-node and the main gate driving signal terminal and configured to include a fifth transistor configured to determine whether to turn on the output of the first clock signal terminal; Shift register of the liquid crystal display device comprising a stage comprising a. According to claim 1, The first power supply voltage is a high level power supply voltage or a signal having a voltage level equal to or higher than the high level power supply voltage; And the second power supply voltage is a low level ground voltage or a signal having a voltage level equal to or lower than the low level ground voltage. According to claim 1, Wherein each of the transistors is an N-type amorphous silicon thin film transistor. According to claim 1, The pull-up driving unit may include: a 1-1 transistor configured to be turned on at an output of the start signal terminal and configured in a diode manner; A first-second transistor electrically connecting the first-first transistor and the Q-node Q, and determining whether to turn on the output of the clock signal terminal; The shift register of claim 1, wherein the shift register is configured to replace the first transistor. According to claim 1, The pull-up driving unit includes: a 1-1 transistor electrically connecting the first power voltage terminal and the Q-node and determining whether to turn on the output of the start signal terminal;  A first-second transistor electrically connecting the first power voltage terminal to the Q-node and determining whether to turn on the output of the clock signal terminal; And the first-first transistor and the first-second transistor are connected in parallel, and configured to replace the first transistor. According to claim 1, When the outputs of the first to fourth clock signal stages overlap each other, the fourth transistor of the pull-down driver may be turned on by the output of the third clock signal stage. Shift register of the device. A liquid crystal display for generating a signal corresponding to an output signal of the first to fourth clock signal terminals, the first power voltage terminal and the second power voltage terminal, and the start signal terminal to which the front gate driving signal is input, through the gate driving signal terminal. In the driving circuit of A first transistor electrically connected between the first power supply voltage terminal and the Q-node and configured to determine whether to turn on the start signal to which the gate driving signal of the front stage is input, the first clock signal terminal and the main gate driving signal; A pull-up driver electrically connected between stages, the pull-up driver comprising a second transistor configured to determine whether to turn on the output of the Q-node; 3-1 and 3-2 transistors electrically connected between the Q-node and the second power supply voltage terminal and configured to be turned on by a gate driving signal of a next stage stage, and the second power supply voltage; A pull-down driving unit electrically connected between the terminal and the main gate driving signal terminal and configured to include a fourth transistor configured to determine whether to turn on the output of the second clock signal terminal; An auxiliary driver electrically connected between the Q-node and the main gate driving signal terminal and configured to include a fifth transistor configured to determine whether to turn on the output of the first clock signal terminal; Shift register of the liquid crystal display device comprising a stage comprising a. The method of claim 7, wherein The first power supply voltage is a high level power supply voltage or a signal having a voltage level equal to or higher than the high level power supply voltage; And the second power supply voltage is a low level ground voltage or a signal having a voltage level equal to or lower than the low level ground voltage. The method of claim 7, wherein Wherein each of the transistors is an N-type amorphous silicon thin film transistor. The method of claim 7, wherein The pull-up driving unit may include: a 1-1 transistor configured to be turned on at an output of the start signal terminal and configured in a diode manner; A first-second transistor electrically connecting the first-first transistor and the Q-node (Q), and determining whether to turn on the output of the clock signal terminal; The shift register of claim 1, wherein the shift register is configured to replace the first transistor. The method of claim 7, wherein The pull-up driving unit includes: a 1-1 transistor electrically connecting the first power voltage terminal and the Q-node, and determining whether to turn on the output of the start signal terminal;  A first-second transistor electrically connecting the first power voltage terminal to the Q-node and determining whether to turn on the output of the clock signal terminal; And the first-first transistor and the first-second transistor are connected in parallel, and configured to replace the first transistor. The method of claim 7, wherein When the outputs of the first to fourth clock signal stages overlap each other, the fourth transistor of the pull-down driver may be turned on by the output of the third clock signal stage. Shift register of the device. The method of claim 7, wherein And the third-2 transistor is turned on by an output signal of a second to fourth clock signal terminal. A liquid crystal display which generates a signal corresponding to an output signal of the first to fourth clock signal terminals, the first power voltage terminal and the second power voltage terminal, and the start signal terminal to which the front gate driving signal is input, through the gate driving signal terminal In the drive circuit of the device, A first transistor electrically connected between the first power supply voltage terminal and a Q-node, the first transistor configured to determine whether to turn on the gate driving signal of a previous stage, and electrically between the first clock signal terminal and the main gate driving signal terminal; A pull-up driver connected to the output of the Q-node, the second transistor configured to determine whether to turn on; 3-1 and 3-2 transistors electrically connected between the Q-node and the second power supply voltage terminal and configured to be turned on by a gate driving signal of a next stage stage, and the second power supply voltage; A 4-1 transistor electrically connected between the terminal and the main gate driving signal terminal and determining whether to turn on the output of the second clock signal terminal, and between the second power voltage terminal and the main gate driving signal terminal. A pull-down driver electrically connected to the 4th transistor, the pull-down driver configured to turn on the gate driving signal of the front stage; An auxiliary driver electrically connected between the Q-node and the main gate driving signal terminal and configured to include a fifth transistor configured to determine whether to turn on the output of the first clock signal terminal; Shift register of the liquid crystal display device comprising a stage comprising a. The method of claim 14, The first power supply voltage is a high level power supply voltage or a signal having a voltage level equal to or higher than the high level power supply voltage; And the second power supply voltage is a low level ground voltage or a signal having a voltage level equal to or lower than the low level ground voltage. The method of claim 14, Wherein each of the transistors is an N-type amorphous silicon thin film transistor. The method of claim 14, The pull-up driving unit may include: a 1-1 transistor configured to be turned on at an output of the start signal terminal and configured in a diode manner; A first-second transistor electrically connecting the first-first transistor and the Q-node (Q), and determining whether to turn on the output of the clock signal terminal; The shift register of claim 1, wherein the shift register is configured to replace the first transistor. The method of claim 14, The pull-up driving unit includes: a 1-1 transistor electrically connecting the first power voltage terminal and the Q-node and determining whether to turn on the output of the start signal terminal;  A first-second transistor electrically connecting the first power voltage terminal to the Q-node and determining whether to turn on the output of the clock signal terminal; And the first-first transistor and the first-second transistor are connected in parallel, and configured to replace the first transistor. The method of claim 14, When the outputs of the first to fourth clock signal stages overlap each other, whether the 4-1 transistor of the pull-down driver is turned on by the output of the third clock signal stage, 4-2. The shift register of the liquid crystal display device, characterized in that the transistor is turned on by the output of the gate driving signal terminal after the next stage. The method of claim 14, And the third-2 transistor is turned on by an output signal of a second to fourth clock signal terminal. A liquid crystal display for generating a signal corresponding to an output signal of the first to fourth clock signal stages, the first power voltage stage and the second power voltage stage, and the start signal stage to which the front gate drive signal is input through the gate drive signal stage In the driving circuit of A first transistor electrically connected between the first power supply voltage terminal and a Q-node, the first transistor configured to determine whether to turn on the gate driving signal of a previous stage, and electrically between the first clock signal terminal and the main gate driving signal terminal; A pull-up driver connected to the output of the Q-node, the second transistor configured to determine whether to turn on; 3-1 and 3-2 transistors electrically connected between the Q-node and the second power supply voltage terminal and configured to be turned on by a gate driving signal of a next stage stage, and the second power supply voltage; A 4-1 transistor electrically connected between the terminal and the main gate driving signal terminal, and having a turn-on state determined at an output of the Qb node; and electrically connected between the first power voltage terminal and the Qb node. And a 4-2 transistor configured to determine whether the output of the second clock signal stage is turned on, and electrically connected between the Qb-node and the second power voltage terminal, and turn on the output of the fourth clock signal stage. A pull-down driver configured as a 4-3 transistor whose on or off is determined; An auxiliary driver electrically connected between the Q-node and the main gate driving signal terminal and configured to include a fifth transistor configured to determine whether to turn on the output of the first clock signal terminal; Shift register of the liquid crystal display device comprising a stage comprising a. The method of claim 21, The first power supply voltage is a high level power supply voltage or a signal having a voltage level equal to or higher than the high level power supply voltage; And the second power supply voltage is a low level ground voltage or a signal having a voltage level equal to or lower than the low level ground voltage. The method of claim 21, Wherein each of the transistors is an N-type amorphous silicon thin film transistor. The method of claim 21, The pull-up driving unit may include: a 1-1 transistor configured to be turned on at an output of the start signal terminal and configured in a diode manner; A first-second transistor electrically connecting the first-first transistor and the Q-node (Q), and determining whether to turn on the output of the clock signal terminal; The shift register of claim 1, wherein the shift register is configured to replace the first transistor. The method of claim 21, The pull-up driving unit includes: a 1-1 transistor electrically connecting the first power voltage terminal and the Q-node and determining whether to turn on the output of the start signal terminal;  A first-second transistor electrically connecting the first power voltage terminal to the Q-node and determining whether to turn on the output of the clock signal terminal; And the first-first transistor and the first-second transistor are connected in parallel, and configured to replace the first transistor. The method of claim 21, When the outputs of the first to fourth clock signal stages overlap each other, the 4-2 transistor of the pull-down driving unit is determined to be turned on by the output of the third clock signal stage, 4-3 A shift register of a liquid crystal display device, characterized in that the transistor is turned on by the output of the gate driving signal terminal after the next stage. The method of claim 21, And the third-2 transistor is turned on by an output signal of a second to fourth clock signal terminal.

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