CN110992871A

CN110992871A - Shift register and display panel

Info

Publication number: CN110992871A
Application number: CN201911364682.3A
Authority: CN
Inventors: 赵欣; 朱正勇; 胡思明; 韩珍珍
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd
Priority date: 2019-12-26
Filing date: 2019-12-26
Publication date: 2020-04-10

Abstract

The invention discloses a shift register and a display panel. The shift register comprises an output adjusting module, a first node and a second node, wherein the output adjusting module is used for adjusting output signals of the shift register according to signals on the first node and the second node; the trigger writing module is used for writing a trigger signal into the second node according to a first clock signal; wherein a signal on the second node is written only by the trigger write module; the node adjusting module is used for adjusting signals on the first node and comprises a power supply lead-in sub module and a first adjusting sub module; the power supply leading-in submodule is used for leading a set power supply signal to the control end of the first adjusting submodule according to the first clock signal; the first adjusting submodule is used for adjusting the signal on the first node according to the signal of the control end of the first adjusting submodule. The embodiment of the invention can reduce the number of components in the shift register and can avoid the phenomenon of electric leakage of the shift register.

Description

Shift register and display panel

Technical Field

The embodiment of the invention relates to a shift register technology, in particular to a shift register and a display panel.

Background

With the development of display technology, the application of display panels is becoming more and more widespread, and the non-display area of the display panel includes a plurality of shift registers, such as enable circuits, etc., to provide enable signals for the display panel.

However, the shift register in the conventional display panel is easy to leak electricity, which causes the screen flashing phenomenon of the display panel and seriously affects the display effect of the display panel.

Disclosure of Invention

The invention provides a shift register and a display panel, which are used for avoiding the electric leakage phenomenon of the shift register and improving the stability of output signals of the shift register.

In a first aspect, an embodiment of the present invention provides a shift register, including: the output adjusting module is used for adjusting the output signals of the shift register according to the signals on the first node and the second node; the trigger writing module is used for writing a trigger signal into the second node according to a first clock signal; wherein a signal on the second node is written only by the trigger write module; the node adjusting module is used for adjusting signals on the first node and comprises a power supply lead-in sub module and a first adjusting sub module; the power supply leading-in submodule is used for leading a set power supply signal to the control end of the first adjusting submodule according to the first clock signal; the first adjusting submodule is used for adjusting the signal on the first node according to the signal of the control end of the first adjusting submodule.

Optionally, the shift register further includes: a first coupling module to couple an output signal of the shift register to the second node.

Optionally, the output adjusting module comprises: the control end of the pull-up sub-module is electrically connected with the first node, and the first end of the pull-up sub-module is connected with a first power supply signal; and the control end of the pull-down submodule is electrically connected with the second node, the first end of the pull-down submodule is accessed to a second power supply signal, and the second end of the pull-up submodule and the second end of the pull-down submodule are in short circuit and then are used for outputting the output signal of the shift register.

Optionally, a control end of the power supply lead-in sub-module is connected to the first clock signal, a first end of the power supply lead-in sub-module is connected to the first power supply signal, and a second end of the power supply lead-in sub-module is electrically connected to a control end of the first regulation sub-module; the node adjustment module further comprises: and a first end of the coupling submodule is connected to the second clock signal, and a second end of the coupling submodule is electrically connected with the control end of the first adjusting submodule.

Optionally, a control end of the power supply lead-in sub-module is connected to the first clock signal, a first end of the power supply lead-in sub-module is connected to a second power supply signal, and a second end of the power supply lead-in sub-module is electrically connected to a control end of the first regulation sub-module; the node adjustment module further comprises: the first end of the holding submodule is electrically connected with the control end of the first adjusting submodule, and the second end of the holding submodule is electrically connected with the first node; the shift register further includes: and the control end of the clock writing module is electrically connected with the second node, the first end of the clock writing module is connected into the first clock signal, and the second end of the clock writing module is electrically connected with the second end of the power supply lead-in submodule.

Optionally, the shift register further comprises a maintaining module; the first end of the maintaining module is connected with a first power supply signal, and the second end of the maintaining module is electrically connected with the first node.

Optionally, the shift register further includes: an isolation module; the first end of the first adjusting submodule is connected to the second clock signal, and the second end of the first adjusting submodule is electrically connected with the first end of the isolation module; and the control end of the isolation module is connected to the second clock signal, and the second end of the isolation module is electrically connected with the first node.

Optionally, the node adjusting module further includes: and a control end of the second adjusting submodule is electrically connected with the second node, a first end of the second adjusting submodule is connected to the first power signal, and a second end of the second adjusting submodule is electrically connected with the first node.

Optionally, the shift register further includes: the control end of the first normally-open module is connected with a second power supply signal, the first end of the first normally-open module is electrically connected with the second end of the power supply lead-in submodule, and the second end of the first normally-open module is electrically connected with the control end of the first regulation submodule; and/or the second normally-open module, the control end of the second normally-open module is connected into a second power signal, the first end of the second normally-open module is electrically connected with the second end of the trigger writing module, and the second end of the second normally-open module is electrically connected with the second node.

In a second aspect, an embodiment of the present invention further provides a display panel, including at least one driving circuit located in a non-display area of the display panel, where the driving circuit includes a plurality of cascaded shift registers according to the first aspect, a signal output end of each shift register is electrically connected to a corresponding enable signal line in the display panel, and the driving circuit includes an enable driving circuit.

The shift register adopted by the invention comprises an output adjusting module, a trigger writing module and a node adjusting module comprising a power supply lead-in submodule and a first adjusting submodule, and a signal on a second node is only written in by the trigger writing module, so that on one hand, the using number of components in the shift register can be reduced, and the realization of a narrow frame of a display panel is facilitated; on the other hand, the problem of unstable electric potential on the second node caused by electric leakage can be avoided, and the stability of the output signal of the shift register is further improved.

Drawings

FIG. 1 is a schematic circuit diagram of a shift register of the prior art;

fig. 2 is a schematic circuit diagram of a shift register according to an embodiment of the present invention;

fig. 3 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;

fig. 4 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;

fig. 5 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;

fig. 6 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;

fig. 7 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;

FIG. 8 is a timing diagram of a shift register according to an embodiment of the present invention;

fig. 9 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;

fig. 10 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;

fig. 11 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;

fig. 12 is a schematic circuit diagram of a display panel according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

As mentioned in the background art, there is a leakage phenomenon in the conventional shift register, fig. 1 is a schematic circuit structure diagram of a shift register in the related art, and referring to fig. 1, the shift register can be applied in an enable circuit of a display panel to provide an enable signal for a pixel driving circuit in the display panel, and includes 13 transistors (M1 ', M2', M3 ', M4', M5 ', M6', M7 ', M8', M9 ', M10', M11 ', M12', M13 ') and 3 capacitors (C1', C2 ', and C3'), and an output signal Gout 'has a certain shift with respect to an input signal EIN' under the combined action of a first clock signal ECK1 ', a second clock signal ECK 2', a first dc signal VGH ', and a second dc signal VGL'; however, when the transistor M5 'and the transistor M4' are biased seriously or the temperature rises, the leakage of the transistor M4 'or the transistor M5' becomes large, and at this time, that is, when the transistor M4 'and the transistor M5' should not be turned on, a conduction phenomenon may exist, so that the first dc signal VGH 'flows into the gate of the transistor M10', and further the transistor M10 'is turned off in a conduction stage, that is, the shift register output signal Gout' cannot normally output a low-level signal, which causes an abnormal output of the shift register.

In order to solve the technical problems, the invention provides the following solutions:

fig. 2 is a schematic circuit diagram of a shift register according to an embodiment of the present invention, and referring to fig. 2, the shift register includes: an output adjusting module 101, wherein the output adjusting module 101 is used for adjusting the output signal of the shift register according to the signals on the first node N1 and the second node N2; a toggle write module 102, the toggle write module 102 being configured to write the toggle signal IN into the second node N2 according to the first clock signal CLK 1; wherein the signal on the second node N2 is written only by the toggle write module 102; the node adjusting module is used for adjusting a signal on a first node N1 and comprises a power supply lead-in submodule 103 and a first adjusting submodule 104; the power supply introducing submodule 103 is used for introducing a set power supply signal to a control end of the first regulating submodule 105 according to the first clock signal CLK 1; the first adjusting submodule 104 is used to adjust the signal at the first node N1 according to the input signal at its own control terminal.

Specifically, the output adjusting module 101 may control the output signal Gout to be the first power signal VGH according to the control signal on the first node N1, and may control the output signal Gout to be the second power signal VGL according to the control signal on the second node N2, where the first power signal VGH and the second power signal VGL have different high and low levels, for example, the first power signal VGH is at a high level, and the second power signal VGL is at a low level. The first clock signal CLK1 and the second clock signal CLK2 may be opposite clock signals to each other, and there may be a time margin between the first clock signal CLK1 and the second clock signal CLK 2.

The setting clock signal may be a first power signal VGH or a second clock signal VGL, the first power signal VGH may be used to turn off the first regulation submodule 104, and the second power signal VGL may be used to turn on the first regulation submodule 104; the signal at the second node N2 is written only by the trigger writing module 102, i.e. the second node N2 only has a conductive path with the trigger writing module 102, the signal at the second node N2 is only related to the trigger signal IN, and when the trigger signal IN is at a low level, the second node N2 can be controlled to write a low level, and further the output adjustment module can be controlled to output a low level. The transistors M4 'and M5' in the display panel in FIG. 1 are not required to be arranged, so that on one hand, the number of components in the shift register can be reduced, and the realization of a narrow frame of the display panel is facilitated; on the other hand, the unstable potential at the second node N2 caused by the leakage of the transistor M4 'or the transistor M5' in fig. 1 can be avoided, so as to improve the stability of the output signal of the shift register.

In the technical scheme of this embodiment, the shift register includes an output adjusting module, a trigger writing module, and a node adjusting module including a power supply introducing submodule and a first adjusting submodule, and a signal on the second node is written only by the trigger writing module without setting the transistor M4 'and the transistor M5' in fig. 1, so that on one hand, the number of components in the shift register can be reduced, and the realization of a narrow frame of a display panel is facilitated; on the other hand, the instability of the potential at the second node N2 caused by the leakage of the transistor M4 'or the transistor M5' can be avoided, and the stability of the output signal of the shift register can be improved.

Fig. 3 is a schematic circuit structure diagram of another shift register according to an embodiment of the present invention, referring to fig. 3, the shift register further includes a first coupling module 105, and the first coupling module 105 is configured to couple an output signal Gout of the shift register to a second node N2.

Specifically, the first coupling module 105 may include a capacitor, and the first coupling module 105 may feed back the output signal Gout to the second node N2, so as to stabilize the output signal Gout, if the first coupling module 105 is not electrically connected to the signal output terminal of the shift register, but is electrically connected to a level transition signal, such as a clock signal, which may be coupled to the second node, thereby affecting the stability of the output signal of the shift register. The first coupling module 105 is configured to couple the output signal Gout of the shift register to the second node N2, for example, when the output signal Gout outputs a low level, the first coupling module 105 may couple the output signal Gout of the shift register to the second node N2, and further pull down the potential of the second node N2, so that a transistor that controls the output signal Gout of the shift register to output a low level, for example, a P-type transistor enters a deep linear region, optimize the turn-on degree of the transistor, further improve the stability of the output signal Gout of the shift register, prevent the output signal Gout from generating a corner cut due to instability, and ensure the stability of the output signal Gout of the shift register.

Fig. 4 is a schematic circuit diagram of another shift register according to an embodiment of the present invention, and referring to fig. 4, the output adjusting module 101 includes: a control end of the pull-up sub-module 1011 is electrically connected to the first node N1, and a first end of the pull-up sub-module 1011 is connected to a first power signal VGH; in the pull-down submodule 1012, a control end of the pull-down submodule 1012 is electrically connected to the second node N2, a first end of the pull-down submodule 1012 is connected to the second power signal VGL, and the pull-up submodule VGH is short-circuited with a second end of the pull-down submodule VGL and then used for outputting an output signal Gout of the shift register.

Specifically, the pull-up sub-module 1011 and the pull-down sub-module 1012 can both adopt P-type transistors or N-type transistors, and for example, the pull-up sub-module 1011 and the pull-down sub-module 1012 can both adopt P-type transistors, when the potential at the first node N1 is a low level, the pull-up sub-module 1011 is turned on, and at this time, the shift register outputs the first power signal VGH, that is, the output signal Gout is the same as the first power signal VGH; when the voltage level at the second node N2 is low, the pull-down sub-module 1012 is turned on, and the shift register outputs the second power signal VGL, and the output signal Gout is the same as the second power signal VGL.

Fig. 5 is a schematic circuit structure diagram of another shift register according to an embodiment of the present invention, and referring to fig. 5, a control terminal of the power supply sub-module 103 is connected to a first clock signal CLK1, a first terminal of the power supply sub-module 103 is connected to a first power signal VGH, and a second terminal of the power supply sub-module 103 is electrically connected to a control terminal of the first adjusting sub-module 104; the node adjusting module further comprises a coupling submodule 105, and a second end of the coupling submodule 105 is electrically connected to the control end of the first adjusting submodule 104.

Specifically, the coupling submodule 106 may be configured to couple the second clock signal CLK2 to a control terminal of the first regulation submodule 104, and when the first clock signal CLK1 is at a high level and the second clock signal CLK2 is at a low level, the power supply introducing submodule 103 may be turned off under the control of the first clock signal CLK1, and the second clock signal CLK2 may be coupled to the control terminal of the first regulation submodule 104, so as to turn on the first regulation submodule 104, so that the first regulation submodule 104 adjusts the potential of the first node N1 to be at a low level, turn on the pull-up submodule 1011, and control the shift register to output the first power supply signal VGH.

Fig. 6 is a schematic circuit structure diagram of another shift register according to an embodiment of the present invention, referring to fig. 6, based on the shift register circuit shown in fig. 5, the shift register may further include a maintaining module 108, a first end of the maintaining module 108 is connected to the first power signal VGH, and a second end of the maintaining module 108 is electrically connected to the first node N1.

Specifically, the maintaining module 108 may employ a capacitor to maintain the voltage level at the first node N1, so that when the first adjusting submodule 104 is turned off, the control terminal of the pull-up submodule 1011 can still maintain the low level, that is, the pull-up submodule 1011 can be normally turned on, and the shift register can be ensured to normally output the high level.

With continued reference to fig. 6, the node adjustment module further comprises: and a second regulation submodule 110, wherein a control terminal of the second regulation submodule 110 is electrically connected with a second node N2, a first terminal of the second regulation submodule 110 is connected to the first power signal VGH, and a second terminal of the second regulation submodule 108 is electrically connected with the first node N1.

Specifically, the second adjusting sub-module 110 may control the potential of the first node N1 according to a signal output by the trigger writing module 102 to control the state of the pull-up sub-module 1011, so that the trigger signal IN may affect both the pull-up sub-module 1011 and the pull-down sub-module 1012, and the output of the shift register may be affected by the input, thereby implementing the shift of the output signal to the trigger signal.

With continued reference to fig. 6, the shift register further includes: a control end of the first normally open module 201 is connected to the second power signal VGL, a first end of the first normally open module 201 is electrically connected to a second end of the power supply lead-in submodule 103, and a second end of the first normally open module 201 is electrically connected to a second end of the first regulation submodule 104; and/or the second normally-open module 202, a control end of the second normally-open module 202 is connected to the second power signal VGL, a first end of the second normally-open module 202 is electrically connected to a second end of the trigger write module 102, and a second end of the second normally-open module 202 is electrically connected to the second node N2.

Specifically, the first normally-open module 201 and the second normally-open module 202 can both adopt P-type transistors, the second power signal VGL adopts a low level, the first normally-open module 201 and the second normally-open module 202 can be ensured to be continuously in a conducting state, the stability of the potential of the second node N2 can be improved, namely, the stability of the control end of the first adjusting submodule 104 and the control end potential of the pull-down submodule 1012 can be further improved, and the working stability of the shift register is further improved.

Fig. 7 is a schematic circuit structure diagram of another shift register according to an embodiment of the present invention, referring to fig. 7, taking P-type transistors as examples of transistors in the shift register, the trigger write module 102 employs a first transistor M1, the power supply lead-in sub-module 103 employs a second transistor M2, the first adjustment sub-module 104 employs a third transistor M3, the second adjustment sub-module 110 employs a fourth transistor M4, the pull-up sub-module 1011 employs a fifth transistor M5, the pull-down sub-module 1012 employs a sixth transistor M6, the second normally-open module 202 employs a seventh transistor M7, the isolation module 109 employs an eighth transistor M8, the first normally-open module 201 employs a ninth transistor M9, the coupling sub-module 106 employs a first capacitor C1, the first coupling module 105 employs a second capacitor C2, and the sustain module 108 employs a third capacitor C3.

FIG. 8 is a timing diagram of a shift register according to an embodiment of the present invention, which can correspond to the shift register shown in FIG. 7, with reference to FIG. 7 and FIG. 8;

IN the first stage T0, the trigger signal IN is at a low level, the first clock signal CLK1 is at a high level, the second clock signal CLK2 is at a high level, the first transistor M1 is turned off, the sixth transistor M6 is also turned off, and the output signal Gout is not output;

IN the second stage T1, at this time, the first clock signal CLK1 changes to a low level, so that the first transistor M1 is turned on, the low-level trigger signal IN is transmitted to the gate of the sixth transistor M6, and the sixth transistor M6 is controlled to be turned on, so that the shift register outputs the second power signal VGL, that is, the output signal Gout and the trigger signal IN are both at a low level; when the first transistor M1 is turned on, the low level trigger signal IN is written into the second capacitor C2, and when the first transistor M1 is turned off, the second capacitor C2 can maintain the low level of the gate of the sixth transistor M6, so that the sixth transistor M6 maintains the on state, and the shift register continuously outputs the low level signal. IN addition, when the first transistor M1 is turned on, the low-level trigger signal IN is written into the gate of the fourth transistor M4 to control the fourth transistor M4 to be turned on, so that the first power signal VGH is written into the gate of the fifth transistor M5 to control the fifth transistor M5 to be turned off, thereby preventing the shift register from outputting a high-level signal; the second capacitor C2 can also maintain the fourth transistor M4 turned on when the first clock signal CLK1 becomes high, thereby writing a high potential to the gate of the fifth transistor M5. That is, in the second stage T2, the output of the shift register does not vary with the first clock signal CLK1 or the second clock signal CLK 2.

IN the third stage T2, when the trigger signal IN changes to a high level, the first clock signal CLK1 is at a low level, the second clock signal CLK2 is at a high level, and the first transistor M1 is turned on, so that the sixth transistor M6 is turned off, but since the second transistor M2 is turned on, the gate of the third transistor M3 writes a high level, that is, the third transistor M3 is turned off, and at this time, the fifth transistor M5 is also IN an off state, and under the holding action of the second capacitor C2, the shift register still outputs a low level.

IN a fourth phase T3, the trigger signal IN is at a high level, the first clock signal CLK1 is at a high level, the second clock signal CLK2 is at a low level, the first transistor M1 is turned off, the gate of the sixth transistor M6 cannot write a low level, at this time, the sixth transistor M6 is turned off, the low-level second clock signal CLK2 is coupled to the gate of the third transistor M3 through the first capacitor C1, the third transistor M3 is turned on, the eighth transistor M8 is also turned on under the control of the second clock signal CLK2, so that the gate of the fifth transistor M5 is written with the low level, the fifth transistor M5 is turned on, and the output terminal of the shift register outputs the high level. And the third capacitor C3 is also written low at this time, so that the gate of the fifth transistor M5 is maintained at a low level at the next time. When the first clock signal CLK1 changes to a low level and the second clock signal CLK2 changes to a high level, since the sixth transistor M6 cannot be turned on, the potential of the gate of the fifth transistor M5 remains at a low level under the hold of the third capacitor C3, so that the fifth transistor M5 is turned on, and the shift register outputs a high level, that is, the output of the shift register does not follow the influence of the first clock signal CLK1 and the second clock signal CLK2 in the fourth stage T3.

IN the fifth phase T4, the trigger signal IN goes high, the first clock signal CLK1 goes high, and the second clock signal CLK2 goes low, at this time, since the first transistor M1 is turned off, the low trigger signal IN cannot be transmitted to the gate of the sixth transistor M6, that is, the sixth transistor M6 cannot be turned on, and the fifth transistor M5 is still turned on under the hold of the third capacitor C3, that is, the shift register still outputs a high signal.

In the sixth stage Tn, the timing of the sixth stage Tn is the same as the timing of the second stage T1, and the state of the shift register is the same as the state in the second stage T1, which is not described herein again. Thus, the shift register realizes a function of shifting the output signal to the trigger signal IN.

Fig. 9 is a schematic circuit structure diagram of another shift register according to an embodiment of the present invention, referring to fig. 9, a control terminal of the power supply sub-module 103 is connected to a first clock signal CLK1, a first terminal of the power supply sub-module 103 is connected to a first power supply signal VGL, and a second terminal of the power supply sub-module 103 is electrically connected to a control terminal of the first adjusting sub-module 104; the first end of the trigger writing module 102 is connected to the trigger signal IN, and the shift register further includes: a clock writing module 107, wherein a control terminal of the clock writing module 107 is electrically connected to a second terminal of the trigger writing module 102, i.e. a second node N2, a first terminal of the clock writing module 107 is connected to a first clock signal CLK1, and a second terminal of the clock writing module 107 is electrically connected to a second terminal of the power supply lead-in submodule 103; the node adjustment module further comprises: and a holding submodule 1061, wherein a first end of the holding submodule 1061 is electrically connected to the control end of the first adjusting submodule 104, and a second end of the holding submodule 1061 is electrically connected to the first node N1.

Specifically, the clock writing module 107 may be configured to, when the first clock signal CLK1 is at a high level and the trigger signal IN is at a low level, due to a holding effect of the first coupling module 105, turn on the clock writing module at this time, and write the first clock signal at the high level into the control end of the first adjusting submodule 104, so that the first adjusting submodule 104 is turned off, thereby preventing the first adjusting submodule 104 from writing the second clock signal CLK2 at the low level into the pull-up submodule 1011, that is, preventing the control pole of the pull-up submodule 1011 from being written into the low level, so as to prevent the pull-up submodule 1011 from being turned on by mistake, that is, preventing the shift register from outputting an abnormal state.

Fig. 10 is a schematic circuit structure diagram of another shift register according to an embodiment of the present invention, referring to fig. 10, based on the shift register shown in fig. 9, the shift register may further include a sustain module 108, a first end of the sustain module 108 is connected to the first power signal VGH, and a second end of the sustain module 108 is electrically connected to the first node N1.

With continued reference to FIG. 10, the shift register further includes an isolation module 109, a first terminal of the first regulation submodule 104 is coupled to the second clock signal CLK2, and a second terminal of the first regulation submodule 104 is electrically coupled to the first terminal of the isolation module 109; the control terminal of the isolation module 109 is coupled to the second clock signal CLK2, and the first terminal of the isolation module 109 is electrically connected to the first node N1.

Specifically, the isolation module 109 may be configured to isolate the holding submodule 1061 from the pull-up submodule 1011, so as to avoid an influence of a signal on the holding submodule 1061 on a gate potential of the pull-up submodule 1011 when the second clock signal CLK2 is at a high level, and further improve the stability of the shift register.

With continued reference to fig. 10, the node adjustment module further includes: and a second regulation submodule 110, wherein a control terminal of the second regulation submodule 110 is electrically connected with a second node N2, a first terminal of the second regulation submodule 110 is connected to the first power signal VGH, and a second terminal of the second regulation submodule 108 is electrically connected with the first node N1.

With continued reference to fig. 10, the shift register further includes: a control end of the first normally open module 201 is connected to the second power signal VGL, a first end of the first normally open module 201 is electrically connected to a second end of the power supply lead-in submodule 103, and a second end of the first normally open module 201 is electrically connected to a second end of the first regulation submodule 104; and/or the second normally-open module 202, a control end of the second normally-open module 202 is connected to the second power signal VGL, a first end of the second normally-open module 202 is electrically connected to a second end of the trigger write module 102, and a second end of the second normally-open module 202 is electrically connected to the second node N2.

Fig. 11 is a schematic circuit diagram of another shift register according to an embodiment of the present invention, and referring to fig. 11, taking P-type transistors as examples of transistors in the shift register, the trigger write module 102 employs a first transistor M1, the power supply lead-in sub-module 103 employs a second transistor M2, the first regulation sub-module 104 employs a third transistor M3, the second regulation sub-module 110 employs a fourth transistor M4, the pull-up sub-module 1011 employs a fifth transistor M5, the pull-down sub-module 1012 employs a sixth transistor M6, the second normally-open module 202 employs a seventh transistor M7, the isolation module 109 employs an eighth transistor M8, the first normally-open module 201 employs a ninth transistor M9, the clock write module 107 may employ a tenth transistor M10, the coupling sub-module 106 employs a first capacitor C1, the first coupling module 105 employs a second capacitor C2, and the sustain module 108 employs a third capacitor C3.

Specifically, the timing chart shown in fig. 8 may also correspond to the shift register shown in fig. 11, in conjunction with fig. 8 and 11:

IN the second stage T1, at this time, the first clock signal CLK1 changes to a low level, so that the first transistor M1 is turned on, the low-level trigger signal IN is transmitted to the gate of the sixth transistor M6, and the sixth transistor M6 is controlled to be turned on, so that the shift register outputs the second power signal VGL, that is, the output signal Gout and the trigger signal IN are both at a low level; when the first transistor M1 is turned on, the low level trigger signal IN is written into the second capacitor C2, and when the first transistor M1 is turned off, the second capacitor C2 can maintain the low level of the gate of the sixth transistor M6, so that the sixth transistor M6 maintains the on state, and the shift register continuously outputs the low level signal. IN addition, when the first transistor M1 is turned on, the low-level trigger signal IN is written into the gate of the fourth transistor M4 to control the fourth transistor M4 to be turned on, so that the first power signal VGH is written into the gate of the fifth transistor M5 to control the fifth transistor M5 to be turned off, thereby preventing the shift register from outputting a high-level signal; the second capacitor C2 can also maintain the fourth transistor M4 turned on when the first clock signal CLK1 becomes high, thereby writing a high potential to the gate of the fifth transistor M5. And when the first clock signal CLK1 changes to a high level, at which time the second clock signal CLK2 changes to a low level, the second capacitor C2 keeps the tenth transistor M10 turned on, thereby writing the high-level first clock signal CLK1 into the gate of the third transistor M3, turning off the third transistor M3, preventing the third transistor M3 from writing the low-level second clock signal CLK2 into the gate of the fifth transistor M5, and thereby preventing the fifth transistor M5 from being turned on. That is, in the second stage T2, the output of the shift register does not vary with the first clock signal CLK1 or the second clock signal CLK 2.

IN the third stage T2, when the trigger signal IN changes to a high level, the first clock signal CLK1 is at a low level, the second clock signal CLK2 is at a high level, the first transistor M1 is turned on, so that the sixth transistor M6 is turned off, the second transistor M2 is turned on, the gate of the third transistor M3 is written with a low level, that is, the third transistor M3 is turned on, the third transistor M3 writes the second clock signal CLK2 at a high level into the gate of the fifth transistor M5, at this time, the fifth transistor M5 is also IN a turned-off state, and under the holding action of the second capacitor C2, the shift register still outputs a low level.

IN a fourth phase T3, the trigger signal IN is at a high level, the first clock signal CLK1 is at a high level, the second clock signal CLK2 is at a low level, the first transistor M1 is turned off, the gate of the sixth transistor M6 cannot be written with a low level, the sixth transistor M6 is turned off, due to the holding effect of the first capacitor C1, the third transistor M3 is still turned on, the low level second clock signal CLK2 is output to the gate of the fifth transistor M5, so that the fifth transistor M5 is controlled to be turned on, the shift register outputs the first power signal VGH, that is, the output signal Gout is at a high level; when the third transistor M3 is turned on, the low-level second clock signal CLK2 charges the third capacitor C3, so as to ensure that the fifth transistor M5 can still be turned on when the eighth transistor M8 is turned off at the next time; that is, the output of the shift register does not follow the first clock signal CLK1 and the second clock signal CLK2 at the fourth stage T3.

Fig. 12 is a schematic circuit structure diagram of a display panel according to an embodiment of the present invention, referring to fig. 12, the display panel includes at least one driving circuit 200 located in a non-display area NAA, fig. 12 exemplarily shows one driving circuit 200, and each driving circuit 200 includes a plurality of cascaded shift registers 10 according to the embodiment described above, so that the display panel according to the present invention has the above-mentioned advantageous effects, which are not described herein again, an output terminal OUT of each shift register 10 is electrically connected to a corresponding enable signal line 5 in the display panel, and the driving circuit 200 includes an enable driving circuit.

Specifically, as shown in fig. 12, the output signal of each shift register 10 is transmitted to the corresponding enable signal line 5 in the display panel 100, the pixel units 6 located in the display area AA emit light under the control of the enable signal transmitted by the corresponding enable signal line 5, that is, the output signal of the corresponding stage shift register 10, and the data signal transmitted by the corresponding data signal line 7, and fig. 12 exemplarily sets the driving circuit 200 as an enable driving circuit, and the driving circuit 200 is electrically connected to the enable signal line of the corresponding pixel unit of each row.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A shift register, comprising:

the output adjusting module is used for adjusting the output signals of the shift register according to the signals on the first node and the second node;

the trigger writing module is used for writing a trigger signal into the second node according to a first clock signal; wherein a signal on the second node is written only by the trigger write module;

the node adjusting module is used for adjusting signals on the first node and comprises a power supply lead-in sub module and a first adjusting sub module;

the power supply leading-in submodule is used for leading a set power supply signal to the control end of the first adjusting submodule according to the first clock signal;

the first adjusting submodule is used for adjusting the signal on the first node according to the signal of the control end of the first adjusting submodule.

2. The shift register of claim 1, further comprising:

a first coupling module to couple an output signal of the shift register to the second node.

3. The shift register of claim 1, wherein the output adjustment module comprises:

the control end of the pull-up sub-module is electrically connected with the first node, and the first end of the pull-up sub-module is connected with a first power supply signal;

and the control end of the pull-down submodule is electrically connected with the second node, the first end of the pull-down submodule is accessed to a second power supply signal, and the second end of the pull-up submodule and the second end of the pull-down submodule are in short circuit and then are used for outputting the output signal of the shift register.

4. The shift register according to claim 1, wherein a control terminal of the power supply import submodule is connected to the first clock signal, a first terminal of the power supply import submodule is connected to a first power supply signal, and a second terminal of the power supply import submodule is electrically connected to a control terminal of the first regulation submodule;

the node adjustment module further comprises:

and the first end of the coupling submodule is connected with a second clock signal, and the second end of the coupling submodule is electrically connected with the control end of the first adjusting submodule.

5. The shift register according to claim 1, wherein a control terminal of the power supply import submodule is connected to the first clock signal, a first terminal of the power supply import submodule is connected to the second power supply signal, and a second terminal of the power supply import submodule is electrically connected to the control terminal of the first regulation submodule;

the node adjustment module further comprises:

the first end of the holding submodule is electrically connected with the control end of the first adjusting submodule, and the second end of the holding submodule is electrically connected with the first node;

the shift register further includes:

and the control end of the clock writing module is electrically connected with the second node, the first end of the clock writing module is connected into the first clock signal, and the second end of the clock writing module is electrically connected with the second end of the power supply lead-in submodule.

6. The shift register of claim 1, further comprising:

and a first end of the maintaining module is connected with a first power supply signal, and a second end of the maintaining module is electrically connected with the first node.

7. The shift register of claim 1, further comprising:

the first end of the first adjusting submodule is connected with a second clock signal, and the second end of the first adjusting submodule is electrically connected with the first end of the isolating module;

and the control end of the isolation module is connected with a second clock signal, and the second end of the isolation module is electrically connected with the first node.

8. The shift register of claim 1, wherein the node adjustment module further comprises:

and the control end of the second adjusting submodule is electrically connected with the second node, the first end of the second adjusting submodule is connected into a first power supply signal, and the second end of the second adjusting submodule is electrically connected with the first node.

9. The shift register of claim 1, further comprising:

the control end of the first normally-open module is connected with a second power supply signal, the first end of the first normally-open module is electrically connected with the second end of the power supply lead-in submodule, and the second end of the first normally-open module is electrically connected with the control end of the first regulation submodule; and/or

The control end of the second normally-open module is connected into a second power signal, the first end of the second normally-open module is electrically connected with the second end of the trigger writing module, and the second end of the second normally-open module is electrically connected with the second node.

10. A display panel comprising at least one driving circuit in a non-display region of the display panel, the driving circuit comprising a plurality of cascaded shift registers according to any one of claims 1 to 9, a signal output terminal of each shift register being electrically connected to a corresponding enable signal line in the display panel, the driving circuit comprising an enable driving circuit.