CN113838402B

CN113838402B - Shift register, gate driving circuit and display panel

Info

Publication number: CN113838402B
Application number: CN202111197357.XA
Authority: CN
Inventors: 张元波; 朱正勇; 贾溪洋; 孙光远
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd
Priority date: 2021-10-14
Filing date: 2021-10-14
Publication date: 2024-05-24
Anticipated expiration: 2041-10-14
Also published as: CN113838402A

Abstract

The invention discloses a shift register, a grid driving circuit and a display panel; the shift register includes: the first output regulation submodule is used for outputting a first power supply signal from the output end according to the conduction signal of the first node and outputting a first clock signal from the output end according to the conduction signal of the second node; the second output adjusting sub-module is used for outputting the first power supply signal from the output end according to the conduction signal of the first node and outputting a second clock signal from the output end according to the conduction signal of the second node; the first clock signal and the second clock signal have the same time sequence; the power supply introduction sub-module is used for writing a second power supply signal into the first node according to a third clock signal; and the trigger writing sub-module is used for writing a trigger signal into the second node according to the third clock signal. The invention can make the pixel circuit fully initialize and write data, and improve the display effect of the display panel.

Description

Shift register, gate driving circuit and display panel

Technical Field

The embodiment of the invention relates to a display technology, in particular to a shift register, a grid driving circuit and a display panel.

Background

Along with the development of display technology, the application of display panels is also becoming wider, and the corresponding requirements on the display technology are also becoming higher.

The display panel needs the shift register to provide the scanning signal required by the operation of the pixel circuit, however, the pixel circuit adopting the existing shift register has the problems of insufficient initialization and data writing, and seriously affects the display effect of the display panel.

Disclosure of Invention

The invention provides a shift register, a grid driving circuit and a display panel, so that a pixel circuit can be fully initialized and data written in, and the display effect of the display panel is improved.

In a first aspect, an embodiment of the present invention provides a shift register, including:

the first output regulation submodule is used for outputting a first power supply signal from the output end according to the conduction signal of the first node and outputting a first clock signal from the output end according to the conduction signal of the second node;

the second output adjusting sub-module is used for outputting the first power supply signal from the output end according to the conduction signal of the first node and outputting a second clock signal from the output end according to the conduction signal of the second node; wherein the first clock signal and the second clock signal have the same time sequence;

The power supply introduction sub-module is used for writing a second power supply signal into the first node according to a third clock signal;

and the trigger writing sub-module is used for writing a trigger signal into the second node according to the third clock signal.

Optionally, the first output adjustment submodule includes:

The first power supply signal is connected to the first end of the first pull-up sub-module, and the control end of the first pull-up sub-module is electrically connected with the first node;

The first end of the first pull-down sub-module is connected with the first clock signal, the control end of the first pull-down sub-module is electrically connected with the second node, and the second end of the first pull-up sub-module is short-circuited with the second end of the first pull-down sub-module and then used as the output end of the first output regulation sub-module;

the second output conditioning submodule includes:

the first end of the second pull-up sub-module is connected with the first power supply signal, and the control end of the second pull-up sub-module is electrically connected with the first node;

The first end of the second pull-down sub-module is connected with the second clock signal, the control end of the second pull-down sub-module is electrically connected with the second node, and the second end of the second pull-down sub-module is short-circuited with the second end of the second pull-up sub-module and then used as the output end of the second output adjustment sub-module.

Optionally, the shift register further includes:

The first end of the holding module is electrically connected with the second node, the second end of the holding module is electrically connected with the second end of the first pull-down sub-module or the second end of the second pull-down sub-module, and the holding module is used for holding the potential of the second node.

Optionally, the trigger writing submodule includes a first transistor, a first end of the first transistor is connected to the trigger signal, a control end of the first transistor is connected to the third clock signal, and a second end of the first transistor is electrically connected to the second node;

The power supply introduction submodule comprises a second transistor, a first end of the second transistor is connected with the second power supply signal, a control end of the second transistor is connected with the third clock signal, and a second end of the second transistor is electrically connected with the first node;

the first pull-up sub-module comprises a third transistor, a first end of the third transistor is used as a first end of the first pull-up sub-module, a control end of the third transistor is used as a control end of the first pull-up sub-module, and a second end of the third transistor is used as a second end of the first pull-up sub-module;

the first pull-down submodule comprises a fourth transistor, a first end of the fourth transistor is used as a first end of the first pull-down submodule, a control end of the fourth transistor is used as a control end of the first pull-down submodule, and a second end of the fourth transistor is used as a second end of the first pull-down submodule;

the second pull-up sub-module comprises a fifth transistor, a first end of the fifth transistor is used as a first end of the second pull-up sub-module, a control end of the fifth transistor is used as a control end of the second pull-up sub-module, and a second end of the fifth transistor is used as a second end of the second pull-up sub-module;

The second pull-down submodule comprises a sixth transistor, a first end of the sixth transistor is used as a first end of the second pull-down submodule, a control end of the sixth transistor is used as a control end of the second pull-down submodule, and a second end of the sixth transistor is used as a control end of the second pull-down submodule;

the holding module includes a first capacitor having a first end as a first end of the holding module and a second end as a second end of the holding module.

Optionally, the shift register further includes: the first end of the second capacitor is connected with the first power supply signal, and the second end of the second capacitor is electrically connected with the first node;

The second end of the first transistor is electrically connected with the second node through the normally-off transistor, wherein the second end of the first transistor is electrically connected with the first end of the normally-off transistor, the second end of the normally-off transistor is connected with a conduction signal of the normally-off transistor, and the second end of the normally-off transistor is electrically connected with the second node.

Optionally, the shift register further includes:

The first feedback sub-module is used for writing the first power supply signal into the second node according to the potential of the first node and the first clock signal;

And the second feedback sub-module is used for writing the third clock signal into the first node according to the potential of the second node.

Optionally, the first feedback submodule includes a seventh transistor and an eighth transistor, a first end of the seventh transistor is connected to the first power signal, a control end of the seventh transistor is electrically connected to the second node, a second end of the seventh transistor is electrically connected to the first end of the eighth transistor, a control end of the eighth transistor is connected to the first clock signal, and a second end of the eighth transistor is electrically connected to the second node;

the second feedback submodule comprises a ninth transistor, a first end of the ninth transistor is connected with the third clock signal, a control end of the ninth transistor is electrically connected with the second node, and a second end of the ninth transistor is electrically connected with the first node.

In a second aspect, an embodiment of the present invention further provides a gate driving circuit, where the gate driving circuit includes a plurality of shift registers as described in the first aspect;

the output end of the first output regulation submodule or the output end of the second output regulation submodule in the n-th shift register provides a trigger signal of the n+1th shift register; n is an integer greater than or equal to 1.

In a third aspect, an embodiment of the present invention further provides a display panel, where the display panel includes the gate driving circuit of the second aspect, a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line;

the first clock signal line is used for providing a first clock signal for the 2k-1 stage shift register and providing a third clock signal for the 2k stage shift register;

The second clock signal line is used for providing a third clock signal for the 2k-1 stage shift register and providing a first clock signal for the 2k stage shift register;

The third clock signal line is used for outputting a second clock signal to the 2k-1 stage shift register;

the fourth clock signal line is used for outputting a second clock signal to the 2 k-th stage shift register; wherein k is an integer greater than or equal to 1.

Optionally, the display panel further includes a plurality of rows of pixel circuits, and the pixel circuits include an initialization module, a data writing module, a driving module and a light emitting module;

The initialization module is used for initializing the driving module and/or initializing the light-emitting module in an initialization stage;

the data writing module is used for writing data voltage into the control end of the driving module in a data writing stage;

the driving module is used for generating driving current in a light-emitting stage, and the light-emitting module responds to the driving current;

The control end of the initializing module of the kth row of pixel circuits is electrically connected with the output end of the first output adjusting sub-module of the kth stage of shift register;

the control end of the data writing module of the k row of pixel circuits is electrically connected with the output end of the second output adjusting sub-module of the k+1 stage shift register.

According to the technical scheme of the embodiment of the invention, the adopted shift register comprises: the first output regulation submodule is used for outputting a first power supply signal from the output end according to the conduction signal of the first node and outputting a first clock signal from the output end according to the conduction signal of the second node; the second output regulation submodule is used for outputting a first power supply signal from the output end according to the conduction signal of the first node and outputting a second clock signal from the output end according to the conduction signal of the second node; the first clock signal and the second clock signal have the same time sequence; the power supply introduction sub-module is used for writing a second power supply signal into the first node according to a third clock signal; and the trigger writing sub-module is used for writing the trigger signal into the second node according to the third clock signal. The shift register of the embodiment utilizes two output ends to drive two rows of pixel circuits respectively, each output end is only used for driving one row of pixel circuits, the signal delay of the output signals of each output end of the shift register in the display area of the display panel is small, the initialization and the data writing can be better carried out, the display non-uniformity phenomenon is improved, and the display effect is improved.

Drawings

Fig. 1 is a schematic circuit diagram of a shift register according to an embodiment of the present invention;

FIG. 2 is a schematic circuit diagram of a shift register according to another embodiment of the present invention;

FIG. 3 is a timing diagram illustrating the operation of a shift register according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 5 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present invention;

Fig. 6 is a timing chart of a pixel circuit according to an embodiment of the invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.

As mentioned in the background art, the pixel circuit using the existing shift register has the problems of insufficient initialization and data writing, and the applicant has found through careful study that the reason for this technical problem is that:

The data writing process of the pixel circuit comprises two stages, wherein the first stage is an initialization stage for initializing a control end of a driving module and a light emitting module in the pixel circuit; the second stage is a data writing stage, which is used for writing data voltage into the driving module; the control signals of the initialization stage and the data writing stage are driven by a shift register, one output end of the existing shift register outputs the control signals of the initialization stage and the control signals of the data writing stage at the same time, namely, the output end of the shift register is connected with a larger load, as the screen size of a mobile phone is larger and larger, the resolution, the refresh rate and the like are higher and higher, the scanning time of each row is shorter and shorter, the condition of insufficient initialization and data writing is caused due to the larger load connected with the output end of the shift register, and therefore, the difference of data voltages written in different positions of the display panel is caused, the display of the display panel is uneven, and the display effect is seriously reduced.

Aiming at the technical problems, the invention provides the following solutions:

Fig. 1 is a schematic circuit diagram of a shift register according to an embodiment of the present invention, and referring to fig. 1, the shift register includes: the first output adjustment sub-module 101, where the first output adjustment sub-module 101 is configured to output the first power signal PVGH from the output end thereof according to the on signal of the first node N1, and output the first clock signal SCK1 from the output end thereof according to the on signal of the second node N2; the second output adjustment sub-module 102, where the second output adjustment sub-module 102 is configured to output the first power signal PVGH from the output end thereof according to the on signal of the first node N1, and output the second clock signal SCK2 from the output end thereof according to the on signal of the second node N2; wherein, the first clock signal SCK1 and the second clock signal SCK2 have the same time sequence; a power supply introduction sub-module 103, configured to write a second power supply signal PVGL to the first node N1 according to the third clock signal SCK 3; the toggle writing sub-module 104 is configured to write the toggle signal SIN to the second node N2 according to the third clock signal SCK 3.

Specifically, the shift register is capable of shifting the trigger signal SIN and outputting the shifted trigger signal SIN, the output end of the first output adjustment sub-module 101 may be understood as a first output end SoutI of the shift register, and the output end of the second output adjustment sub-module 102 may be understood as a second output end SoutW of the shift register; the first node N1 is configured to control whether the first output adjusting sub-module 101 outputs the first power signal PVGH, and also to control whether the second output adjusting sub-module 102 outputs the first power signal PVGH, where the on signal of the first node N1 may be, for example, a low level, that is, when the first node N1 is at a low level, the first output terminal SoutI and the second output terminal SoutW of the shift register each output the first power signal PVGH, where the first power signal PVGH may be, for example, a high level, and the second power signal PVGL may be, for example, a low level; the second node N2 is configured to control whether the first output adjusting sub-module 101 outputs the first clock signal SCK1, and the second node N2 is further configured to control whether the second output adjusting sub-module 102 outputs the second clock signal SCK2, and the on signal of the second node N2 may be, for example, a low level, that is, when the second node N2 is at a low level, the first output terminal SoutI of the shift register outputs the first clock signal SCK1, and the second output terminal SoutW of the shift register outputs the second clock signal SCK2; the first clock signal SCK1 and the second clock signal SCK2 have the same time sequence, that is, at any time, the phases of the first clock signal SCK1 and the second clock signal SCK2 are the same, and preferably, the amplitudes of the first clock signal SCK1 and the second clock signal SCK2 are the same at any time; therefore, the output signals of the first output terminal SoutI and the second output terminal SoutW have the same timing at any time, and both can be used as the scan signals of the pixel circuits in the display panel, when the display panel is applied to the display panel, the first output terminal SoutI can be used as the scan signals for driving the pixel circuits of the current row into the initialization phase, the second output terminal SoutW can be used as the scan signals for driving the pixel circuits of the previous row into the data writing phase, that is, the first output terminal SoutI corresponding to the first clock signal SCK1 is only used for driving one row of the pixel circuits, the RC load of the output signal of the first output terminal SoutI in the display area of the display panel is lower, the signal delay is reduced, so that the initialization can be better performed; meanwhile, the second output end SoutW corresponding to the second clock signal SCK2 is also only used for driving one row of pixel circuits, the RC load of the second output end SoutW output signal in the display area of the display panel is also lower, the signal delay is reduced, and the initialization can be performed better; that is, the shift register of the embodiment uses two output ends to drive two rows of pixel circuits respectively, each output end is only used for driving one row of pixel circuits, the signal delay of the output signal of each output end of the shift register in the display area of the display panel is smaller, the initialization and the data writing can be better performed, the display non-uniformity phenomenon is improved, and the display effect is improved; meanwhile, the first output end SoutI and the second output end SoutW respectively correspond to the first clock signal SCK1 and the second clock signal SCK2, which can be understood that the first clock signal SCK1 drives the first output end SoutI, the second clock signal SCK2 drives the second output end SoutW, and the first clock signal SCK1 and the second clock signal SCK2 respectively provide clock signals by different clock signal lines, so that the driving capability of the output signals of the first output end SoutI and the second output end SoutW can be further enhanced, the signal delay is reduced, and the display effect is improved.

The power supply introduction sub-module 103 can control the level on the first node N1, the trigger writing sub-module 104 can control the level on the second node N2, the third clock signal SCK3 is opposite to the first clock signal SCK1 in time sequence, it is understood in the art that the third clock signal SCK3 and the first clock signal SCK1 do not need to have a completely opposite time sequence, and a certain time sequence margin can exist between the two, and the trigger signal SIN is output by the first output terminal SoutI and the second output terminal SoutW after being shifted through the cooperation control of the first clock signal SCK1, the second clock signal SCK2, the third clock signal SCK3, the first power supply signal PVGH and the second power supply signal PVGL.

According to the technical scheme of the embodiment, the adopted shift register comprises: the first output regulation submodule is used for outputting a first power supply signal from the output end according to the conduction signal of the first node and outputting a first clock signal from the output end according to the conduction signal of the second node; the second output regulation submodule is used for outputting a first power supply signal from the output end according to the conduction signal of the first node and outputting a second clock signal from the output end according to the conduction signal of the second node; the first clock signal and the second clock signal have the same time sequence; the power supply introduction sub-module is used for writing a second power supply signal into the first node according to a third clock signal; and the trigger writing sub-module is used for writing the trigger signal into the second node according to the third clock signal. The shift register of the embodiment utilizes two output ends to drive two rows of pixel circuits respectively, each output end is only used for driving one row of pixel circuits, the signal delay of the output signals of each output end of the shift register in the display area of the display panel is small, the initialization and the data writing can be better carried out, the display non-uniformity phenomenon is improved, and the display effect is improved.

Optionally, fig. 2 is a schematic circuit diagram of a shift register according to an embodiment of the present invention, and referring to fig. 2, the first output adjustment submodule 101 includes: the first pull-up sub-module 1011, a first end of the first pull-up sub-module 1011 is connected to the first power signal PVGH, and a control end of the first pull-up sub-module 1011 is electrically connected to the first node N1; the first end of the first pull-down submodule 1012 is connected with a first clock signal SCK1, the control end of the first pull-down submodule 1012 is electrically connected with the second node N2, and the second end of the first pull-up submodule 1011 is short-circuited with the second end of the first pull-down submodule 1012 and then used as the output end of the first output regulation submodule 101;

The second output conditioning sub-module 102 includes: the second pull-up sub-module 1021, the first end of the second pull-up sub-module 1021 is connected to the first power signal PVGH, and the second end of the second pull-up sub-module 1021 is electrically connected with the first node N1; the second pull-down sub-module 1022, the first end of the second pull-down sub-module 1022 is connected to the second clock signal SCK2, the control end of the second pull-down sub-module 1022 is electrically connected to the second node N2, and the second end of the second pull-down sub-module 1022 is short-circuited with the second end of the second pull-up sub-module 1021 and then is used as the output end of the second output adjustment sub-module 102.

Specifically, the first pull-up sub-module 1011 can conduct its first terminal with its second terminal according to the conduction signal of the first node N1, thereby outputting the first power signal PVGH from its output terminal; the first pull-down submodule 1012 can conduct the first end and the second end of the second node N2 according to the conduction signal of the second node N2, so that the first clock signal SCK1 is output from the output end thereof; the second pull-up sub-module 1021 can conduct the first terminal thereof with the second terminal thereof according to the conduction signal of the first node N1, thereby outputting the first power signal PVGH from the output terminal thereof, and the second pull-down sub-module 1022 can conduct the first terminal thereof with the second terminal thereof according to the conduction signal of the second node N2, thereby outputting the second clock signal SCK2 from the output terminal thereof. The functions of the first output adjusting sub-module 101 and the second output adjusting sub-module 102 can be completed by adopting the first pull-up sub-module 1011, the first pull-down sub-module 1012, the second pull-up sub-module 1021 and the second pull-down sub-module 1022, so that the structure is simple, and the cost of the shift register is reduced.

Optionally, with continued reference to fig. 2, the shift register further includes a holding module 105, a first end of the holding module 105 is electrically connected to the second node N2, a second end of the holding module 105 is electrically connected to a second end of the first pull-down sub-module 1021 or a second end of the second pull-down sub-module 1022, and the holding module 105 is configured to hold the potential of the second node N2.

Specifically, the holding module 105 may hold the potential of the second node N2, such that the first pull-down submodule 1012 and the second pull-down submodule 1022 can continuously hold the on state until the second node N2 is triggered to write the new potential by the write submodule 104. Preferably, the second terminal of the holding module 105 may be electrically connected to the second terminal of the first pull-down sub-module 1012, and the signal output from the output terminal of the second output adjustment sub-module 102 may be used for the scanning signal of the pixel circuit data writing stage, so that connecting the second terminal of the holding module 105 to the second terminal of the first pull-down sub-module 1012 can avoid increasing the load on the second output adjustment sub-module, thereby avoiding increasing the delay of the output signal from the second output terminal SoutW.

Illustratively, the first and second modules are connected to one another. As shown in fig. 2, the trigger writing sub-module 101 includes a first transistor M1, a first end of the first transistor M1 is connected to the trigger signal SIN, a control end of the first transistor M1 is connected to the third clock signal SCK3, and a second end of the first transistor M1 is electrically connected to the second node N2; the power supply introduction sub-module 103 comprises a second transistor M2, a first end of the second transistor M2 is connected to a second power supply signal PVGL, a control end of the second transistor M2 is connected to a third clock signal SCK3, and a second end of the second transistor M2 is electrically connected to the first node N1; the first pull-up sub-module 1011 includes a third transistor M3, a first terminal of the third transistor M3 is used as a first terminal of the first pull-up sub-module 1011, a control terminal of the third transistor M3 is used as a control terminal of the first pull-up sub-module 1011, and a second terminal of the third transistor M3 is used as a second terminal of the first pull-up sub-module 1011; the first pull-down sub-module 1012 includes a fourth transistor M4, a first terminal of the fourth transistor M4 being a first terminal of the first pull-down sub-module 1012, a control terminal of the fourth transistor M4 being a control terminal of the first pull-down sub-module 1012, a second terminal of the fourth transistor M4 being a second terminal of the first pull-down sub-module 1012; the second pull-up submodule 1021 includes a fifth transistor M5, a first terminal of the fifth transistor M5 is used as a first terminal of the second pull-up submodule 1021, a control terminal of the fifth transistor M5 is used as a control terminal of the second pull-up submodule 1021, and a second terminal of the fifth transistor M5 is used as a second terminal of the second pull-up submodule 1021; the second pull-down sub-module 1022 includes a sixth transistor M6, a first terminal of the sixth transistor M6 is used as the first terminal of the second pull-down sub-module 1022, a control terminal of the sixth transistor M6 is used as the control terminal of the second pull-down sub-module 1022, and a second terminal of the sixth transistor M6 is used as the control terminal of the second pull-down sub-module 1022; the holding module 105 includes a first capacitor C1, a first end of the first capacitor C1 being a first end of the holding module 105, and a second end of the first capacitor C1 being a second end of the holding module.

The first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 may be P-type transistors or N-type transistors, preferably P-type transistors, which have advantages of low cost and easy fabrication in a display panel, and the trigger writing sub-module 104, the power introducing sub-module 103, the first pull-up sub-module 1011, the first pull-down sub-module 1012, the second pull-up sub-module 1021, and the second pull-down sub-module 1022 are implemented by P-type transistors, which is beneficial to reducing the fabrication cost of the shift register and improving the stability of the operation.

Optionally, as shown in fig. 2, the shift register further includes: the first end of the second capacitor C2 is connected with the first power supply signal PVGH, and the second end of the second capacitor C2 is electrically connected with the first node N1; the second end of the first transistor M1 is electrically connected to the second node N2 through the normally-off transistor M10, wherein the second end of the first transistor M1 is electrically connected to the first end of the normally-off transistor M10, the second end of the normally-off transistor M10 is connected to the on signal of the normally-off transistor M10, and the second end of the normally-off transistor M10 is electrically connected to the second node N2.

Specifically, the second capacitor C2 may be used to maintain the potential on the first node N1; the normally-off transistor M10 may be, for example, a P-type transistor or an N-type transistor, preferably, a P-type transistor, and at this time, the on signal of the normally-off transistor M10 is at a low level, i.e., the control terminal thereof is connected to a low level, for example, connected to the second power signal PVGL, and the normally-off transistor M10 can reduce the leakage current on the second node N2, thereby further improving the stability of the shift register.

Optionally, with continued reference to fig. 2, the shift register further includes: the first feedback sub-module 106, the first feedback sub-module 106 is configured to write the first power signal PVGH into the second node N2 according to the potential of the first node N1 and the first clock signal SCK 1; the second feedback sub-module 107, the second feedback sub-module 107 is configured to write the third clock signal SCK3 into the first node N1 according to the potential of the second node N2.

Specifically, in this embodiment, the second feedback sub-module 107 includes a ninth transistor M9, a first end of the ninth transistor M9 is connected to the third clock signal SCK3, a second end of the ninth transistor M9 is electrically connected to the first node N1, and a control end of the ninth transistor M9 is electrically connected to the second node N2; the first feedback submodule comprises a seventh transistor M7 and an eighth transistor M8, a first end of the seventh transistor M7 is connected with a first power supply signal PVGH, a second end of the seventh transistor M7 is electrically connected with a first end of the eighth transistor M8, and a control end of the seventh transistor M7 is electrically connected with the first node N1; the second terminal of the eighth transistor M8 is electrically connected to the second node N2, and the control terminal of the eighth transistor M8 is connected to the first clock signal SCK1. The second feedback module can control the first node N1 according to the potential feedback of the second node N2, so that when the third clock signal SCK3 is at a high level and the fourth transistor M4 is turned on, the third transistor M3 is in an off state, so as to prevent the first output terminal and the second output terminal of the shift register from simultaneously outputting a high level and a low level, that is, prevent the first output terminal and the second output terminal from finding unstable conditions; the first feedback module can control the potential of the second node N2 according to the potential feedback of the second node N1, so that the first clock signal SCK1 is at a low level, and when the first node N1 is at a low level, the second node N2 is controlled to be at a high level, so as to prevent the first output end and the second output end of the shift register from simultaneously outputting the high level and the low level, that is, prevent the first output end and the second output end from being unstable. It should be noted that, since the register is used in the present embodiment, the first output terminal SoutI and the second output terminal SoutW have a relatively high load capacity, and therefore, the fourth transistor M4 and the sixth transistor M6 can be smaller in size, and thus, the parasitic capacitance of the fourth transistor M4 and the sixth transistor M6 is also smaller, and thus, the delay of the output signals of the first output terminal SoutI and the second output terminal SoutW is further reduced.

FIG. 3 is a timing diagram illustrating the operation of a shift register according to an embodiment of the present invention, which may correspond to the shift register shown in FIG. 2;

In the first stage T1, the trigger signal SIN is at a high level, when the third clock signal SCK3 is at a low level and the second clock signal SCK1 is at a high level, the first transistor M1 and the second transistor M2 are turned on, the second power signal PVGL is written into the first node N1, so that the third transistor M3 and the fifth transistor M5 are turned on, and the first output terminal SoutI and the second output terminal SoutW both output a high level; meanwhile, since the trigger signal SIN is at a high level, the first transistor M1 is turned on, and the second node N2 is at a high level, that is, the fourth transistor M4 and the sixth transistor M6 are both in an off state at this time; when the third clock signal SCK3 is at a high level and the first clock signal SCK2 and the second clock signal SCK2 are at a low level, the first transistor M1 and the second transistor M2 are turned off, and the first node N1 is still at a low level and the second node N2 is still at a high level due to the holding effect of the first capacitor C1 and the second capacitor C2, so that the first output end SoutI and the second output end SoutW continuously output a high level; in addition, when the first clock signal SCK1 is at a low level and the third clock signal SCK3 is at a high level, the eighth transistor M8 is turned on, the first transistor M1 is turned off, and in the first stage T1, since the first node N1 is at a low level, the seventh transistor M7 is also in a turned-on state, and at this time, the first power signal PVGH is written into the second node N2, so that the second node N2 maintains a high level, and erroneous turn-on of the fourth transistor M4 and the sixth transistor M6 is avoided.

In the second stage T2, the trigger signal SIN is at a low level, the third clock signal SCK3 is at a low level, the first clock signal SCK1 and the second clock signal SCK2 are at a high level, the first transistor M1 and the second transistor M2 are turned on at this time, the trigger signal SIN at a low level is written into the second node N2, the second power signal PVGL is written into the first node N1, the third transistor M3 and the fourth transistor M4 are both turned on, the fifth transistor M5 and the sixth transistor M6 are both turned on, and the first output terminal SoutI and the second output terminal SoutW both output a high level at this time because the first clock signal SCK1 and the second clock signal SCK2 are both at a high level.

In the third stage T3, the trigger signal SIN is at a low level, the third clock signal SCK3 is at a high level, the first clock signal SCK1 and the second clock signal SCK2 are at a low level, the first transistor M1 and the second transistor M2 are turned off at this time, the second node N2 is still at a low level due to the holding effect of the first capacitor C1, the fourth transistor M4 and the sixth transistor M6 are turned on, the first output terminal SoutI and the second output terminal SoutW both output a low level, the second node N2 at a low level enables the ninth transistor M9 to be turned on, the third clock signal SCK3 at a high level feedback controls the first node N1 to write a high level, the first node N1 is at a high level, and the third transistor M3 and the fifth transistor M5 are prevented from being turned off, so that the first output terminal SoutI and the second output terminal SoutW can both stably output a low level.

In the fourth stage T4, the trigger signal SIN is at a low level, the third clock signal SCK3 is at a low level, the first clock signal SCK1 and the second clock signal SCK2 are at a high level, the first transistor M1 and the second transistor M2 are turned on, the first node N1 and the second node N2 are simultaneously written with the low level, and the third transistor M3, the fifth transistor M5, the fourth transistor M4 and the sixth transistor M6 are all turned on, but the first output terminal SoutI and the second output terminal SoutW output the high level due to the high level of the first clock signal SCK1 and the second clock signal SCK 2.

In the fifth stage T5, the trigger signal SIN is at a high level, the third clock signal SCK3 is at a high level, the first clock signal SCK1 and the second clock signal SCK2 are at a low level, and the potentials at the first node N1 and the second node N2 are still at a low level due to the holding effect of the first capacitor C1 and the second capacitor C2, so that the first output terminal SoutI and the second output terminal SoutW output a low level.

The working state of the sixth stage T6 is the same as the working state of the first stage T1, and will not be described here again, thereby completing the shift output of the trigger signal SIN; it should be noted that, in this embodiment, the first stage shift register of the plurality of cascaded shift registers is taken as an example, the trigger signal SIN of the first stage shift register is a signal with a single pulse shown in fig. 3, and the signal is shifted and outputted by the first stage shift register and becomes two pulses, that is, the first output terminal SoutI and the second output terminal SoutW are both output signals including two pulses, which is more suitable for the driving method of the existing pixel circuit, and any one of them can be used as the trigger signal of the next stage shift register.

The embodiment of the invention also provides a gate driving circuit, which comprises a plurality of shift registers provided by any embodiment of the invention; the output end of the first output regulation submodule or the output end of the second output regulation submodule in the n-th shift register provides a trigger signal of the n+1th shift register; n is an integer greater than or equal to 1.

Specifically, the gate driving circuit is composed of a plurality of cascaded shift registers, and can provide scanning signals for the pixel circuits in a plurality of rows, and the shift registers provided in any embodiment of the present invention have the same beneficial effects, and are not described herein.

Fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and referring to fig. 4, the display panel includes a gate driving circuit, a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, and a fourth clock signal line CLK4 according to any embodiment of the present invention; the first clock signal line CLK1 is used to supply the first clock signal to the 2k-1 st stage shift register 10 and to supply the third clock signal to the 2 k-th stage shift register; the second clock signal line is used for providing a third clock signal for the 2k-1 stage shift register and providing a first clock signal for the 2k stage shift register; the third clock signal line is used for outputting a second clock signal to the 2k-1 stage shift register; the fourth clock signal line is used for outputting a second clock signal to the 2 k-th shift register; wherein k is an integer greater than or equal to 1.

Specifically, as shown in fig. 4, the clock signal on the first clock signal line CLK1 and the clock signal on the third clock signal line CLK3 are identical in timing, and the clock signal on the second clock signal line CLK2 and the clock signal on the fourth clock signal line CLK4 are identical in timing; because the display panel provided by the embodiment of the invention includes the gate driving circuit provided by any embodiment of the invention, the display panel also has the same beneficial effects, and is not described herein again.

Optionally, the display panel further includes a plurality of rows of pixel circuits, as shown in fig. 5, fig. 5 is a schematic circuit structure diagram of a pixel circuit according to an embodiment of the present invention, where the pixel circuit includes an initialization module, a data writing module, a driving module, and a light emitting module; the initialization module is used for initializing the driving module and/or initializing the light-emitting module in an initialization stage; the data writing module is used for writing data voltage into the control end of the driving module in the data writing stage; the driving module is used for generating driving current in a light-emitting stage, and the light-emitting module responds to the driving current; the control end of the initializing module of the kth row of pixel circuits is electrically connected with the output end of the first output adjusting sub-module of the kth stage of shift register; the control end of the data writing module of the k row of pixel circuits is electrically connected with the output end of the second output adjusting sub-module of the k+1 stage shift register.

Specifically, the pixel circuit includes a driving module data writing module 201 for writing a data voltage Vdata to the driving module 204 under the control of the second scan signal S2; a memory module 202 for maintaining the potential of the control terminal of the driving module 204; a first light emitting control module 203 and a second light emitting control module 206 for providing a current path required for light emission under the control of an enable signal EM; the threshold compensation module 205 is configured to capture a threshold voltage of the driving module 204 to a control end of the driving module; the initialization module includes a first initialization module 207 and a second initialization module 208, which are configured to initialize the driving module 204 and the light emitting module D by using an initialization signal Vref under the control of the first scan signal S1; as shown in fig. 6, fig. 6 is a timing chart of a pixel circuit according to an embodiment of the present invention, and the working principle of the pixel circuit is well known to those skilled in the art and will not be described herein again; in this embodiment, the third clock signal line CLK3 and the fourth clock signal line CLK4 are less in load, and only half of the shift registers in the gate driving circuit are connected, so that the output driving capability is stronger, that is, the load capability of the second output terminal SoutW is greater than that of the first output terminal SoutI, so that the output signal of the second output terminal SoutW can be used as the second scan signal S2, and in the display area of the display panel, the second scan signal S2 has a lower signal delay than the first scan signal S1, so that the data writing of the pixel circuit can be ensured to be more sufficient, the display non-uniformity phenomenon can be further reduced, and the display effect can be improved.

Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims

1. A shift register, the shift register comprising:

the second output adjusting sub-module is used for outputting the first power supply signal from the output end according to the conduction signal of the first node and outputting a second clock signal from the output end according to the conduction signal of the second node; wherein the first clock signal and the second clock signal have the same time sequence; the output end of the first output regulation submodule is the same as the output signal of the output end of the second output regulation submodule in time sequence at any moment; the output signal of the output end of the first output adjusting sub-module is used as a scanning signal in the initializing stage of a row of pixel circuits, and the output signal of the output end of the second output adjusting sub-module is used as a scanning signal in the data writing stage of a row of pixel circuits;

2. The shift register of claim 1, wherein the first output adjustment submodule comprises:

the second output conditioning submodule includes:

3. The shift register of claim 2, wherein the shift register further comprises:

4. A shift register as claimed in claim 3, in which the toggle writing submodule comprises a first transistor, a first terminal of the first transistor being connected to the toggle signal, a control terminal of the first transistor being connected to the third clock signal, a second terminal of the first transistor being electrically connected to the second node;

5. The shift register of claim 4, wherein said shift register further comprises: the first end of the second capacitor is connected with the first power supply signal, and the second end of the second capacitor is electrically connected with the first node;

6. The shift register of claim 1, wherein the shift register further comprises:

7. The shift register of claim 6, wherein the first feedback submodule comprises a seventh transistor and an eighth transistor, a first end of the seventh transistor being connected to the first power supply signal, a control end of the seventh transistor being electrically connected to the second node, a second end of the seventh transistor being electrically connected to the first end of the eighth transistor, a control end of the eighth transistor being connected to the first clock signal, a second end of the eighth transistor being electrically connected to the second node;

8. A gate driving circuit comprising a plurality of shift registers according to any one of claims 1 to 7;

9. A display panel comprising the gate driving circuit of claim 8, a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line;

10. The display panel of claim 9, further comprising a plurality of rows of pixel circuits, the pixel circuits comprising an initialization module, a data writing module, a driving module, and a light emitting module;