CN105976749A - Shift register, grid driving circuit and display panel - Google Patents
Shift register, grid driving circuit and display panel Download PDFInfo
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- CN105976749A CN105976749A CN201610545458.4A CN201610545458A CN105976749A CN 105976749 A CN105976749 A CN 105976749A CN 201610545458 A CN201610545458 A CN 201610545458A CN 105976749 A CN105976749 A CN 105976749A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Shift Register Type Memory (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a shift register, a grid driving circuit and a display panel. The shift register comprises a control module and an output module, wherein the control module is used for changing potential of a first node and a second node through signals of a first clock signal end, signals of a reference signal end and signals of a signal input end under the control of the first clock signal end and the signal input end; and the output module is used for outputting the signals of the reference signal end through a scanning signal output end under the control of the first node and outputting signals of a second clock signal end through the scanning signal output end under the control of the second node. In such a way, the shift register provided by the embodiment of the invention realize normal output of scanning signals through the control module and the output module, at the same time, the shift register only comprises the control module and the output module, the structure is simple, the power consumption is low, and realization of narrow-frame design of the display panel is facilitated.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of shift register, gate driver circuit and show
Show panel.
Background technology
At present, along with the development of Display Technique, the competition of display floater industry is more and more fierce, reduces display floater
Production cost become panel business and improve the preferred option of competitiveness, and become to reduce the production of display floater
This, usually, those skilled in the technology concerned utilize the edge of display floater to build gate driver circuit,
Gate driver circuit includes multiple shift register, the corresponding grid line of each shift register, multiple displacements
Depositor uses cascade system to arrange, and has, between adjacent two shift registers, the triggering signal transmitted step by step,
After each shift register receives triggering signal, to corresponding grid line output grid line scanning signal, and triggering
Signal flows to next stage element circuit to realize the function of raster data model, and such design can be saved aobvious
Show that the frame region of panel is separately provided grid drive chip, reduce the production cost of Related product, improve
The display competitiveness of product in market.
But, in existing display floater designs, shift-register circuit structure is generally located on display surface
The neighboring area of plate, occupies bigger bezel locations, is unfavorable for showing at present the need to narrow frame in field
Ask, and the circuit structure of shift register is the most more complicated, thus cause its power consumption bigger.Narrow limit
Frame is an important development direction of currently displaying screen, it is generally the case that the periphery sealed plastic box district of display product
The part that territory can reduce has reached capacity, and simplifies the circuit structure of shift register and optimizes shift LD
The layout design of device circuit becomes reduction shift register and takes up room the effective ways of width.Current displacement
The circuit structure of depositor is as it is shown in figure 1, including 8 switching transistors (T1-T8) and 2 electricity
Holding (C1 and C2), its width that takes up room is the biggest.
Therefore, how to simplify the circuit structure of shift register, meet the narrow frame design demand of display floater,
It is those skilled in the art's technical problems urgently to be resolved hurrily.
Summary of the invention
Embodiments provide a kind of shift register, gate driver circuit and display floater, in order to solve
Certainly the complicated structure of shift register present in prior art, takies the bezel locations of display floater relatively
Big problem.
Embodiments provide a kind of shift register, including: control module and output module；Wherein,
The first input end of described control module and first controls end and is connected with the first clock signal terminal respectively, the
Two inputs and second control end and are connected with signal input part respectively, and the 3rd input and four-input terminal are respectively
Being connected with reference signal end, the first outfan is connected with primary nodal point, and the second outfan is connected with secondary nodal point；
Described control module is under the control of described first clock signal terminal and described signal input part, by institute
State the signal of the first clock signal terminal, the signal of described reference signal end, the signal of described signal input part change
Become described primary nodal point and the current potential of described secondary nodal point；
The first input end of described output module is connected with described reference signal end, the second input and when second
Clock signal end is connected, and first controls end is connected with described primary nodal point, and second controls end is connected with secondary nodal point,
Outfan is connected with scanning signal output part；Described output module is used under the control of described primary nodal point,
The signal of described reference signal end is exported by described scanning signal output part；Control at described secondary nodal point
Under system, the signal of described second clock signal end is exported by described scanning signal output part.
In a kind of possible embodiment, in the above-mentioned shift register that the embodiment of the present invention provides, described
Control module, including: the first input block, the second input block and control unit；Wherein,
The input of described first input block is connected with described first clock signal terminal respectively with controlling end, defeated
Go out end to be connected with described primary nodal point；Described first input block is for the control at described first clock signal terminal
Under system, the signal of described first clock signal terminal is exported described primary nodal point；
The input of described second input block is connected with described signal input part respectively with controlling end, outfan
It is connected with described secondary nodal point；Described second input block is used under the control of described signal input part, will
The signal of described signal input part exports described secondary nodal point；
The first input end of described control unit and the second input are connected with described reference signal end respectively, the
One outfan and first controls end and is connected with described primary nodal point respectively, and the second outfan and second controls end and divides
It is not connected with described secondary nodal point；Described control unit is under the control of described primary nodal point, by described
The signal of reference signal end exports described secondary nodal point；Under the control of described secondary nodal point, by described ginseng
The signal examining signal end exports described primary nodal point.
In a kind of possible embodiment, in the above-mentioned shift register that the embodiment of the present invention provides, described
First input block, including: the first switching transistor；
The grid of described first switching transistor is connected with described first clock signal terminal respectively with source electrode, drain electrode
It is connected with described primary nodal point.
In a kind of possible embodiment, in the above-mentioned shift register that the embodiment of the present invention provides, described
Second input block, including: second switch transistor；
The grid of described second switch transistor is connected with described signal input part respectively with source electrode, drain electrode and institute
State secondary nodal point to be connected.
In a kind of possible embodiment, in the above-mentioned shift register that the embodiment of the present invention provides, described
Control unit, including: the 3rd switching transistor and the 4th switching transistor；Wherein,
The grid of described 3rd switching transistor is connected with described primary nodal point, source electrode and described reference signal end
Being connected, drain electrode is connected with described secondary nodal point；
The grid of described 4th switching transistor is connected with described secondary nodal point, source electrode and described reference signal end
Being connected, drain electrode is connected with described primary nodal point.
In a kind of possible embodiment, in the above-mentioned shift register that the embodiment of the present invention provides, described
Output module, including: the first output unit and the second output unit；Wherein,
The input of described first output unit is connected with described reference signal end, controls end and described first segment
Point is connected, and outfan is connected with described scanning signal output part；Described first output unit is for described the
Under the control of one node, the signal of described reference signal end is exported by described scanning signal output part；
The input of described second output unit is connected with described second clock signal end, controls end and described the
Two nodes are connected, and outfan is connected with described scanning signal output part；Described second output unit is in institute
State under the control of secondary nodal point, by the signal of described second clock signal end by described scanning signal output part
Output.
In a kind of possible embodiment, in the above-mentioned shift register that the embodiment of the present invention provides, described
First output unit, including: the 5th switching transistor and storage electric capacity；Wherein,
The grid of described 5th switching transistor is connected with described primary nodal point, source electrode and described reference signal end
Being connected, drain electrode is connected with described scanning signal output part；
Described storage electric capacity is connected between described reference signal end and described primary nodal point.
In a kind of possible embodiment, in the above-mentioned shift register that the embodiment of the present invention provides, described
Second output unit, including: the 6th switching transistor；
The grid of described 6th switching transistor is connected with described secondary nodal point, and source electrode is believed with described second clock
Number end be connected, drain electrode be connected with described scanning signal output part.
Embodiments providing a kind of gate driver circuit, the multiple embodiment of the present invention including cascade carry
The above-mentioned shift register of confession, the scanning signal output part of each described shift register is all to corresponding grid
Line input scanning signal；In addition to afterbody shift register, the scanning letter of remaining every grade shift register
Number outfan also inputs to the signal input part of the next stage shift register being adjacent and triggers signal.
Embodiments providing a kind of display floater, the above-mentioned grid provided including the embodiment of the present invention drives
Galvanic electricity road.
The beneficial effect of the embodiment of the present invention includes:
Embodiments provide a kind of shift register, gate driver circuit and display floater, this displacement
Depositor includes: control module and output module；Wherein, control module at the first clock signal terminal and
Under the control of signal input part, by the signal of the first clock signal terminal, the signal of reference signal end, signal
The signal change primary nodal point of input and the current potential of secondary nodal point；Output module is for the control at primary nodal point
Under system, the signal of reference signal end is exported by scanning signal output part, under the control of secondary nodal point,
The signal of second clock signal end is exported by described scanning signal output part.So embodiment of the present invention carries
The above-mentioned shift register of confession can realize the normal output of scanning signal by control module and output module,
This shift register only includes control module and output module simultaneously, and its simple in construction is low in energy consumption, and is conducive to
Realize the narrow frame design of display floater.
Accompanying drawing explanation
Fig. 1 is the electrical block diagram of the shift register of prior art；
Fig. 2-Fig. 4 is respectively the structural representation of the shift register that the embodiment of the present invention provides；
The work schedule schematic diagram of the shift register that Fig. 5 provides for the embodiment of the present invention；
The structural representation of the gate driver circuit that Fig. 6 provides for the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawings, shift register, gate driver circuit and the display embodiment of the present invention provided
The detailed description of the invention of panel is described in detail.
Embodiments provide a kind of shift register, as in figure 2 it is shown, may include that control module
01 and output module 02；Wherein,
The first input end of control module 01 and first control end respectively with the first clock signal terminal CLK1 phase
Even, the second input and second controls end and is connected with signal input part Input respectively, the 3rd input and the
Four-input terminal is connected with reference signal end VGH respectively, and the first outfan is connected with primary nodal point P1, and second
Outfan is connected with secondary nodal point P2；Control module 01 is at the first clock signal terminal CLK1 and signal
Under the control of input Input, by the signal of the first clock signal terminal CLK1, reference signal end VGH
Signal, the signal change primary nodal point P1 of signal input part Input and the current potential of described secondary nodal point P2；
The first input end of output module 02 is connected with reference signal end VGH, and the second input is believed with second clock
Number end CLK2 is connected, and first controls end is connected with primary nodal point P1, and second controls end and secondary nodal point P2
Being connected, outfan is connected with scanning signal output part Out；Output module 02 is for primary nodal point P1's
Under control, the signal of reference signal end VGH is exported by scanning signal output part Out；At second section
Under the control of some P2, the signal of second clock signal end CLK2 is defeated by scanning signal output part Out
Go out.
That the embodiment of the present invention provides and above-mentioned shift register can be real by control module and output module
The now normal output of scanning signal, this shift register only includes control module and output module simultaneously, its knot
Structure is the most low in energy consumption, and is advantageously implemented the narrow frame design of display floater.
In the specific implementation, in the above-mentioned shift register that the embodiment of the present invention provides, as it is shown on figure 3, control
Molding block 01 may include that the first input block the 011, second input block 012 and control unit 013；
Wherein, the input of the first input block 011 is connected with the first clock signal terminal CLK1 respectively with controlling end,
Outfan is connected with primary nodal point P1；First input block 011 is at the first clock signal terminal CLK1
Control under, the signal of the first clock signal terminal CLK1 is exported primary nodal point P1；Second input block
The input of 012 is connected with signal input part Input respectively with controlling end, outfan and secondary nodal point P2 phase
Even；Second input block 012, under the control of signal input part Input, inputs a signal into end Input
Signal export secondary nodal point P2；The first input end of control unit 013 and the second input respectively with ginseng
Examining signal end VGH to be connected, the first outfan and first controls end and is connected with primary nodal point P1 respectively, and second
Outfan and second controls end and is connected with secondary nodal point P2 respectively；Control unit 013 is at primary nodal point
Under the control of P1, the signal of reference signal end VGH is exported secondary nodal point P2；At secondary nodal point P2
Control under, the signal of reference signal end VGH is exported primary nodal point P1.
Specifically, in the above-mentioned shift register that the embodiment of the present invention provides, control module can include first
Input list, the second input block and control unit, wherein, the first input block can be in the first clock signal
Under the control of end, the signal of the first clock signal terminal is exported primary nodal point；Second input block can be at letter
The signal inputting a signal into end under the control of number input exports secondary nodal point；Control unit can be first
Under the control of node, the signal of reference signal end is exported secondary nodal point, under the control of secondary nodal point,
The signal of reference signal end is exported primary nodal point.Such that it is able to realize control module at corresponding control signal
Under the control of end, change primary nodal point and the current potential of secondary nodal point.
In the specific implementation, in the above-mentioned shift register that the embodiment of the present invention provides, as shown in Figure 4, the
One input block 011 may include that the first switching transistor M1；The grid of the first switching transistor M1
Being connected with the first clock signal terminal CLK1 respectively with source electrode, drain electrode is connected with primary nodal point P1.Specifically,
First switching transistor can turn under the control of the first clock signal terminal, the first switching transistor of conducting
The signal of the first clock signal terminal can be exported primary nodal point.
In the specific implementation, in the above-mentioned shift register that the embodiment of the present invention provides, as shown in Figure 4, the
Two input blocks 012 may include that second switch transistor M2；The grid of second switch transistor M2
Being connected with signal input part Input respectively with source electrode, drain electrode is connected with secondary nodal point P2.Specifically, second
Switching transistor can turn under the control of signal input part, and the second switch transistor of conducting can will be believed
The signal of number input exports secondary nodal point.
In the specific implementation, in the above-mentioned shift register that the embodiment of the present invention provides, as shown in Figure 4, control
Unit 013 processed may include that the 3rd switching transistor M3 and the 4th switching transistor M4；Wherein,
The grid of three switching transistors M3 is connected with primary nodal point P1, and source electrode is connected with reference signal end VGH,
Drain electrode is connected with secondary nodal point P2；The grid of the 4th switching transistor M4 is connected with secondary nodal point P2, source
Pole is connected with reference signal end VGH, and drain electrode is connected with primary nodal point P1.Specifically, the 3rd switch crystal
Pipe can turn under the control of primary nodal point, and the 3rd switching transistor of conducting can be by reference signal end
Signal exports secondary nodal point；4th switching transistor can turn under the control of secondary nodal point, conducting
The signal of reference signal end can be exported primary nodal point by the 4th switching transistor.
In the specific implementation, in the above-mentioned shift register that the embodiment of the present invention provides, as it is shown on figure 3, defeated
Go out module 02 and may include that the first output unit 021 and the second output unit 022；Wherein, the first output
The input of unit 021 is connected with reference signal end VGH, controls end and is connected with primary nodal point P1, output
Hold and be connected with scanning signal output part Out；First output unit 021 is for the control at primary nodal point P1
Under, the signal of reference signal end VGH is exported by scanning signal output part Out；Second output unit
The input of 022 is connected with second clock signal end CLK2, controls end and is connected with secondary nodal point P2, output
Hold and be connected with scanning signal output part Out；Second output unit 022 is for the control at secondary nodal point P2
Under, the signal of second clock signal end CLK2 is exported by scanning signal output part Out.
Specifically, in the above-mentioned shift register that the embodiment of the present invention provides, output module can include first
Output unit and the second output unit, wherein, the first output unit can be under the control of primary nodal point, will
The signal of reference signal end is exported by scanning signal output part；Second output unit can be at secondary nodal point
Under control, the signal of second clock signal end is exported by scanning signal output part.So output module can
To control under the control of end in correspondence, by the signal of the first output unit output reference signal end or by the
The signal of two output unit output second clock signal ends, thus realize scanning the normal output of signal.
In the specific implementation, in the above-mentioned shift register that the embodiment of the present invention provides, as shown in Figure 4, the
One output unit 021 may include that the 5th switching transistor M5 and storage electric capacity C；Wherein, the 5th open
The grid closing transistor M5 is connected with primary nodal point P1, and source electrode is connected with reference signal end VGH, drain electrode
It is connected with scanning signal output part Out；Storage electric capacity C is connected to reference signal end VGH and primary nodal point
Between P1.Specifically, the 5th switching transistor can turn under the control of primary nodal point, the 5th of conducting
The signal of reference signal end can be exported scanning signal output part by switching transistor；Storage electric capacity can be
The current potential of primary nodal point is maintained during the 5th switching transistor conducting.
In the specific implementation, in the above-mentioned shift register that the embodiment of the present invention provides, as shown in Figure 4, the
Two output units 022 may include that the 6th switching transistor M6；The grid of the 6th switching transistor M6
Being connected with secondary nodal point P2, source electrode is connected with second clock signal end CLK2, drains with to scan signal defeated
Go out to hold Out to be connected.Body ground, the 6th switching transistor can turn under the control of secondary nodal point, conducting
The signal of second clock signal end can be exported scanning signal output part by the 6th switching transistor.
It should be noted that the switching transistor mentioned in the above embodiment of the present invention can be thin film transistor (TFT)
(TFT, Thin Film Transistor), it is also possible to be metal oxide semiconductor field effect tube (MOS,
Metal Oxide Semiconductor), do not limit at this.In being embodied as, the source of these transistors
Pole and drain electrode can be exchanged, and do not do concrete differentiation.Enter as a example by thin film transistor (TFT) when describing specific embodiment
Row explanation.
Below in conjunction with the input and output sequential chart of the shift register shown in Fig. 4 and the Fig. 4 shown in Fig. 5,
The work process of the shift register that the embodiment of the present invention provides is described, the wherein displacement shown in Fig. 4
Switching transistor in depositor illustrates as a example by P-type transistor.Specifically, choose as shown in Figure 5
Input and output sequential chart in t1～t3 three phases.High level signal is represented with 1 in described below, 0
Represent low level signal.
At t1 stage, Input=1, CLK1=0, CLK2=1, VGH=1.Due to CLK1=0, therefore
First switching transistor M1 conducting, the first switching transistor M1 of conducting can be by the first clock signal terminal
The signal of CLK1 exports primary nodal point P1；Due to CLK1=0, the therefore current potential quilt of primary nodal point P1
Drag down so that the 3rd switching transistor M3 and the conducting of the 5th switching transistor M5；5th switch of conducting
The signal of reference signal end VGH is exported by transistor M5 by scanning signal output part Out, i.e. scans
Signal output part Out exports high level signal；3rd switching transistor M3 of conducting is by reference signal end
The signal of VGH exports secondary nodal point P2 so that the current potential of secondary nodal point P2 is driven high so that the 4th opens
Close transistor M4 and the cut-off of the 6th switching transistor M6.
At t2 stage, Input=0, CLK1=1, CLK2=1, VGH=1.Due to Input=0, therefore
Two switching transistor M2 conductings, the second switch transistor M2 of conducting can input a signal into end Input
Signal export secondary nodal point P2；Due to Input=0, therefore the current potential of secondary nodal point P2 is pulled low, and makes
Obtain the 4th switching transistor M4 and the conducting of the 6th switching transistor M6；4th switching transistor of conducting
The signal of reference signal end VGH is exported primary nodal point P1 by M4 so that the current potential quilt of primary nodal point P1
Draw high so that the 3rd switching transistor M3 and the cut-off of the 5th switching transistor M5；6th switch of conducting
The signal of second clock signal end CLK2 is exported scanning signal output part Out by transistor M6, now
CLK2=1, therefore scanning signal output part Out exports high level signal.
At t3 stage, Input=1, CLK1=1, CLK2=0, VGH=1.Due to Input=1, CLK1=1,
Therefore, the first switching transistor M1 and second switch transistor M2 cut-off, primary nodal point P1 and second
Node P2 maintains current potential on last stage, i.e. the current potential of this stage primary nodal point P1 is still high potential so that
3rd switching transistor M3 and the cut-off of the 5th switching transistor M5；The current potential of secondary nodal point P2 is still low
Current potential so that the 4th switching transistor M4 and the conducting of the 6th switching transistor M6；4th switch of conducting
The signal of reference signal end VGH is exported primary nodal point P1 by transistor M4, maintains first segment further
The high potential of some P1；6th switching transistor M6 of conducting is by the signal of second clock signal end CLK2
Output is to scanning signal output part Out, now CLK2=0, and therefore scanning signal output part Out output is low
Level signal.
Based on same inventive concept, embodiments provide a kind of gate driver circuit, including cascade
The above-mentioned shift register that multiple embodiment of the present invention provide, the scanning signal output part of each shift register is equal
To corresponding grid line input scanning signal；In addition to afterbody shift register, remaining every grade displacement
The scanning signal output part of depositor is also defeated to the signal input part of the next stage shift register being adjacent
Enter to trigger signal.
Specifically, for convenience of explanation, Fig. 6 illustrate only eight shift registers, respectively the 1st grade
Shift register, the 2nd grade of shift register, 3rd level shift register, the 4th grade of shift register,
N-3 level shift register, N-2 level shift register, N-1 level shift register, N level shift
Depositor.Wherein, in addition to N level shift register, the scanning signal output of remaining every grade shift register
End Out not only opens signal to connected grid line output grid, also posts to the next stage displacement being adjacent
The signal input part input of storage triggers signal.It addition, the gate driver circuit bag that the embodiment of the present invention provides
Including three clock signals, every one-level shift register only uses two clock signals therein.Specifically,
One-level shift register uses CLK1 and CLK2 in three clock signals；Second level shift register makes
With CLK2 and CLK3 in three clock signals；Third level shift register uses in three clock signals
CLK3 and CLK1；It is so one group with three adjacent shift registers, repeats above three clock
The using method of signal.Additionally, the clock signal of the gate driver circuit use of embodiment of the present invention offer
Dutycycle is 33%, in order to realize the shift LD function of shift register.
Based on same inventive concept, embodiments provide a kind of display floater, implement including the present invention
The above-mentioned gate driver circuit that example provides.This display floater can apply to mobile phone, panel computer, TV
Any products with display function such as machine, display, notebook computer, DPF, navigator or
Parts.Owing to the principle of this display floater solution problem is similar to gate driver circuit, therefore this display floater
Enforcement may refer to the enforcement of above-mentioned gate driver circuit, repeat no more in place of repetition.
Embodiments provide a kind of shift register, gate driver circuit and display floater, this displacement
Depositor includes: control module and output module；Wherein, control module at the first clock signal terminal and
Under the control of signal input part, by the signal of the first clock signal terminal, the signal of reference signal end, signal
The signal change primary nodal point of input and the current potential of secondary nodal point；Output module is for the control at primary nodal point
Under system, the signal of reference signal end is exported by scanning signal output part, under the control of secondary nodal point,
The signal of second clock signal end is exported by described scanning signal output part.So embodiment of the present invention carries
The above-mentioned shift register of confession can realize the normal output of scanning signal by control module and output module,
This shift register only includes control module and output module simultaneously, and its simple in construction is low in energy consumption, and is conducive to
Realize the narrow frame design of display floater.
Obviously, those skilled in the art can carry out various change and modification without deviating from this to the present invention
Bright spirit and scope.So, if the present invention these amendment and modification belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. a shift register, it is characterised in that including: control module and output module；Wherein,
The first input end of described control module and first controls end and is connected with the first clock signal terminal respectively, the
Two inputs and second control end and are connected with signal input part respectively, and the 3rd input and four-input terminal are respectively
Being connected with reference signal end, the first outfan is connected with primary nodal point, and the second outfan is connected with secondary nodal point；
Described control module is under the control of described first clock signal terminal and described signal input part, by institute
State the signal of the first clock signal terminal, the signal of described reference signal end, the signal of described signal input part change
Become described primary nodal point and the current potential of described secondary nodal point；
The first input end of described output module is connected with described reference signal end, the second input and when second
Clock signal end is connected, and first controls end is connected with described primary nodal point, and second controls end is connected with secondary nodal point,
Outfan is connected with scanning signal output part；Described output module is used under the control of described primary nodal point,
The signal of described reference signal end is exported by described scanning signal output part；Control at described secondary nodal point
Under system, the signal of described second clock signal end is exported by described scanning signal output part.
2. shift register as claimed in claim 1, it is characterised in that described control module, including:
First input block, the second input block and control unit；Wherein,
The input of described first input block is connected with described first clock signal terminal respectively with controlling end, defeated
Go out end to be connected with described primary nodal point；Described first input block is for the control at described first clock signal terminal
Under system, the signal of described first clock signal terminal is exported described primary nodal point；
The input of described second input block is connected with described signal input part respectively with controlling end, outfan
It is connected with described secondary nodal point；Described second input block is used under the control of described signal input part, will
The signal of described signal input part exports described secondary nodal point；
The first input end of described control unit and the second input are connected with described reference signal end respectively, the
One outfan and first controls end and is connected with described primary nodal point respectively, and the second outfan and second controls end and divides
It is not connected with described secondary nodal point；Described control unit is under the control of described primary nodal point, by described
The signal of reference signal end exports described secondary nodal point；Under the control of described secondary nodal point, by described ginseng
The signal examining signal end exports described primary nodal point.
3. shift register as claimed in claim 2, it is characterised in that described first input block,
Including: the first switching transistor；
The grid of described first switching transistor is connected with described first clock signal terminal respectively with source electrode, drain electrode
It is connected with described primary nodal point.
4. shift register as claimed in claim 2, it is characterised in that described second input block,
Including: second switch transistor；
The grid of described second switch transistor is connected with described signal input part respectively with source electrode, drain electrode and institute
State secondary nodal point to be connected.
5. shift register as claimed in claim 2, it is characterised in that described control unit, including:
3rd switching transistor and the 4th switching transistor；Wherein,
The grid of described 3rd switching transistor is connected with described primary nodal point, source electrode and described reference signal end
Being connected, drain electrode is connected with described secondary nodal point；
The grid of described 4th switching transistor is connected with described secondary nodal point, source electrode and described reference signal end
Being connected, drain electrode is connected with described primary nodal point.
6. the shift register as described in any one of claim 1-5, it is characterised in that described output mould
Block, including: the first output unit and the second output unit；Wherein,
The input of described first output unit is connected with described reference signal end, controls end and described first segment
Point is connected, and outfan is connected with described scanning signal output part；Described first output unit is for described the
Under the control of one node, the signal of described reference signal end is exported by described scanning signal output part；
The input of described second output unit is connected with described second clock signal end, controls end and described the
Two nodes are connected, and outfan is connected with described scanning signal output part；Described second output unit is in institute
State under the control of secondary nodal point, by the signal of described second clock signal end by described scanning signal output part
Output.
7. shift register as claimed in claim 6, it is characterised in that described first output unit,
Including: the 5th switching transistor and storage electric capacity；Wherein,
The grid of described 5th switching transistor is connected with described primary nodal point, source electrode and described reference signal end
Being connected, drain electrode is connected with described scanning signal output part；
Described storage electric capacity is connected between described reference signal end and described primary nodal point.
8. shift register as claimed in claim 6, it is characterised in that described second output unit,
Including: the 6th switching transistor；
The grid of described 6th switching transistor is connected with described secondary nodal point, and source electrode is believed with described second clock
Number end be connected, drain electrode be connected with described scanning signal output part.
9. a gate driver circuit, it is characterised in that include that the multiple of cascade appoint such as claim 1-8
One described shift register, the scanning signal output part of each described shift register is all to corresponding
Grid line input scanning signal；In addition to afterbody shift register, the scanning of remaining every grade shift register
Signal output part also inputs to the signal input part of the next stage shift register being adjacent and triggers signal.
10. a display floater, it is characterised in that include gate driver circuit as claimed in claim 9.
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| CN201610545458.4A CN105976749A (en) | 2016-07-12 | 2016-07-12 | Shift register, grid driving circuit and display panel |
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Application publication date: 20160928 |