CN111785199B - Scanning driving circuit, display panel and display device - Google Patents
Scanning driving circuit, display panel and display device Download PDFInfo
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- CN111785199B CN111785199B CN202010663798.3A CN202010663798A CN111785199B CN 111785199 B CN111785199 B CN 111785199B CN 202010663798 A CN202010663798 A CN 202010663798A CN 111785199 B CN111785199 B CN 111785199B
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The invention discloses a scanning driving circuit, a display panel and a display device. The scanning driving circuit comprises a first output control module, a second output control module, a first output module and a second output module; the first output control module is used for controlling the first output module to output a second power supply signal provided by the second power supply signal input end according to a first clock signal provided by the first clock signal input end, an input signal provided by the input signal end, a second clock signal provided by the second clock signal input end and a first power supply signal provided by the first power supply signal input end; the second output control module is used for controlling the second output module to output a second clock signal according to the first clock signal and the input signal. The phenomenon of competition hazard caused by mutual control of the first output control module and the second output control module can be avoided, so that the phenomenon of abnormity of scanning signals output by the scanning driving circuit is reduced, and the reliability of the scanning driving circuit is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a scanning driving circuit, a display panel and a display device.
Background
The display panel is provided with a scanning driving circuit for providing scanning signals for the pixel units and controlling the pixel units in the display panel to drive line by line. In the prior art, a scanning driving circuit has a phenomenon of competitive risk, which results in poor reliability of the scanning driving circuit, and further causes a problem in a driving process of a pixel unit of a display panel.
Disclosure of Invention
The invention provides a scanning driving circuit, a display panel and a display device, which are used for avoiding the competition hazard phenomenon of the scanning driving circuit and improving the reliability of the scanning driving circuit.
In a first aspect, an embodiment of the present invention provides a scan driving circuit, including a first output control module, a second output control module, a first output module, and a second output module;
the first output control module is electrically connected with a first clock signal input end, an input signal end, a second clock signal input end, a first power signal input end and the first output module, the first output module is electrically connected with a second power signal input end, and the first output control module is used for controlling the first output module to output a second power signal provided by the second power signal input end according to a first clock signal provided by the first clock signal input end, an input signal provided by the input signal end, a second clock signal provided by the second clock signal input end and a first power signal provided by the first power signal input end;
the second output control module is electrically connected with the first clock signal input end, the input signal end and the second output module, the second output module is electrically connected with the second clock signal input end, and the second output control module is used for controlling the second output module to output the second clock signal according to the first clock signal and the input signal.
Optionally, the first output control module comprises a first transistor and a second transistor;
the grid electrode of the first transistor is electrically connected with the input signal end, the first electrode of the first transistor is electrically connected with the second clock signal input end, and the second electrode of the first transistor and the second electrode of the second transistor are electrically connected with the first output module; the grid electrode of the second transistor is electrically connected with the first clock signal input end, and the first pole of the second transistor is electrically connected with the first power supply signal input end.
Optionally, the first output module includes a third transistor and a first capacitor;
a gate of the third transistor and a first pole of the first capacitor are electrically connected to a second pole of the first transistor and a second pole of the second transistor, a first pole of the third transistor and a second pole of the first capacitor are electrically connected to the second power supply signal input terminal, and a second pole of the third transistor is used as a scan signal output terminal of the scan driver circuit.
Optionally, the second output control module comprises a fourth transistor;
the gate of the fourth transistor is electrically connected to the first clock signal input terminal, the first electrode of the fourth transistor is electrically connected to the input signal terminal, and the second electrode of the fourth transistor is electrically connected to the second output module.
Optionally, the second output module comprises a fifth transistor and a second capacitor;
a gate of the fifth transistor and a first pole of the second capacitor are electrically connected to a second pole of the fourth transistor, the first pole of the fifth transistor is electrically connected to the second clock signal input terminal, and the second pole of the fifth transistor and a second pole of the second capacitor are electrically connected to a second pole of the third transistor.
Optionally, the scan driving circuit further comprises a sixth transistor;
a gate of the sixth transistor is electrically connected to the first power signal input terminal, and a second pole of the fourth transistor and a gate of the fifth transistor are electrically connected through the sixth transistor.
Optionally, the scan driving circuit further comprises a seventh transistor;
a gate of the seventh transistor is electrically connected to a gate of the fifth transistor, a first pole of the seventh transistor is electrically connected to the first power signal input terminal, and a second pole of the seventh transistor is electrically connected to the second pole of the fourth transistor.
Optionally, the fourth transistor is a double-gate transistor.
In a second aspect, an embodiment of the present invention further provides a display panel, including a first clock signal line, a second clock signal line, a first power signal line, a second power signal line, an input signal line, and at least two scan driving circuits provided in any embodiment of the present invention;
a first clock signal input terminal of the scan driving circuit is electrically connected to the first clock signal line, a second clock signal input terminal of the scan driving circuit is electrically connected to the second clock signal line, a first power signal input terminal of the scan driving circuit is electrically connected to the first power signal line, and a second power signal input terminal of the scan driving circuit is electrically connected to the second power signal line;
at least two scanning driving circuits are connected in a cascade mode, and the input signal end of the first stage of scanning driving circuit is electrically connected with the input signal line; the scanning signal output end of the previous stage of scanning driving circuit is electrically connected with the input signal end of the next stage of scanning driving circuit.
In a third aspect, an embodiment of the present invention further provides a display device including the display panel provided in any embodiment of the present invention.
The technical scheme of the invention is that the first output control module is electrically connected with the first clock signal input end, the input signal end, the second clock signal input end and the first power signal input end, the second output control module is electrically connected with the first clock signal input end and the input signal end, and the normal work of the scanning drive circuit is realized on the basis of avoiding the connection relation between the first output control module and the second output control module, thereby avoiding the competition risk phenomenon caused by mutual control of the first output control module and the second output control module, further avoiding the phenomenon that the first output module is mistakenly controlled by the first output control module to output the first scanning signal when the second output control module controls the second output module to output the second scanning signal, further reducing the abnormal phenomenon of the scanning signal output by the scanning drive circuit, the reliability of the scan driving circuit is improved.
Drawings
FIG. 1 is a schematic diagram of a conventional scan driving circuit;
FIG. 2 is a timing diagram of the light-emitting control circuit of FIG. 1;
fig. 3 is a schematic structural diagram of a scan driving circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of another exemplary scan driving circuit according to the present invention;
fig. 6 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of another exemplary scan driving circuit according to the present invention;
FIG. 8 is a timing diagram of the scan driving circuit provided in FIG. 7;
FIG. 9 is a schematic diagram of another exemplary scan driving circuit according to the present invention;
FIG. 10 is a schematic diagram of another exemplary scan driving circuit according to the present invention;
FIG. 11 is a schematic diagram of another exemplary scan driving circuit according to the present invention;
fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic structural diagram of a conventional scan driving circuit. As shown in fig. 1, the scan driving circuit includes 8T2C, and specifically includes a first thin film transistor M1, a second thin film transistor M2, a third thin film transistor M3, a fourth thin film transistor M4, a fifth thin film transistor M5, a sixth thin film transistor M6, a seventh thin film transistor M7, an eighth thin film transistor M8, a first storage capacitor Cs1, and a second storage capacitor Cs 2. Wherein the gate of the first thin film transistor M1 and the gate of the fifth thin film transistor M5 are electrically connected to the first clock signal line ECK1, the first pole of the first thin film transistor M1 is electrically connected to the initialization signal line EIN, the second pole of the first thin film transistor M1 is electrically connected to the first pole of the second thin film transistor M2, the gate of the fourth thin film transistor M4 and the first pole of the eighth thin film transistor M8, the gate of the second thin film transistor M2 is electrically connected to the second clock signal line ECK2, the second pole of the second thin film transistor M2 is electrically connected to the first pole of the third thin film transistor M3, the second pole of the third thin film transistor M3 is electrically connected to the first power signal line VGH, the gate of the third thin film transistor M3 is electrically connected to the second pole of the fourth thin film transistor M4, the second pole of the fifth thin film transistor M5, the first storage capacitor Cs1 and the gate of the sixth thin film transistor M6, a first pole of the fourth thin film transistor M4 is electrically connected to the first clock signal line ECK1, a first pole of the fifth thin film transistor M5 is electrically connected to the second power signal line VGL, a first pole of the sixth thin film transistor M6 and a second pole of the first storage capacitor Cs1 are electrically connected to the first power signal line VGH, a second pole of the sixth thin film transistor M6 is electrically connected to the second pole of the seventh thin film transistor M7 and the second pole of the second storage capacitor Cs2 and serves as a scan signal input terminal SOUT of the scan driving circuit, a gate of the seventh thin film transistor M7 and a first pole of the second storage capacitor Cs2 are electrically connected to the second pole of the eighth thin film transistor M8, a first pole of the seventh thin film transistor M7 is electrically connected to the second clock signal line ECK2, and a gate of the eighth thin film transistor M8 is electrically connected to the second power signal line ECK VGL. The thin film transistors in the scan driver circuit provided in fig. 1 are all illustrated by taking P-type thin film transistors as examples.
Fig. 2 is a timing diagram corresponding to the light-emitting control circuit of fig. 1. The first power signal provided by the first power signal input terminal VGH is at a high level, and the second power signal provided by the second power signal input terminal VGL is at a low level. The eighth thin film transistor M8 is continuously in the on state. Eck1 is a timing of the first clock signal supplied from the first clock signal line Eck1, Eck2 is a timing of the second clock signal supplied from the second clock signal line Eck2, Ein is a timing of the initialization signal supplied from the initialization signal line Ein, and Sout is a timing of the scan signal output from the scan signal output terminal Sout. The operation of the scan driving circuit is described with reference to fig. 1 and 2.
In the first stage t11, Eck1 is low, Eck2 is high, Ein is low, the second power signal is low, the first thin film transistor M1, the fourth thin film transistor M4, and the fifth thin film transistor M5 are turned on, and the second thin film transistor M2 is turned off. The initialization signal is transmitted to the gate of the seventh thin film transistor M7 through the first thin film transistor M1 and the eighth thin film transistor M8, controls the seventh thin film transistor M7 to be turned on, and the scan signal output terminal SOUT outputs the second clock signal at a high level. The low levels of the first clock signal and the second power signal may be transmitted to the gate of the sixth thin film transistor M6, the sixth thin film transistor M6 is turned on, and the scan signal output terminal SOUT outputs the first power signal as a high level.
In the second stage t12, Eck1 is at a high level, Eck2 is at a low level, Ein is at a high level, the first thin film transistor M1 and the fifth thin film transistor M5 are turned off, and the second thin film transistor M2 is turned on. The gate of the seventh thin film transistor M7 is in a floating state, the holding function of the second storage capacitor Cs2 keeps the potential of the gate of the seventh thin film transistor M7 at the previous stage at a low level, the seventh thin film transistor M7 outputs the second clock signal, and the scan signal output terminal SOUT outputs the second clock signal at a low level. Meanwhile, the fourth tft M4 is turned on by the holding action of the second storage capacitor Cs2, the first clock signal is transmitted to the gate of the sixth tft M6 through the fourth tft M4, and is at a high level, so that the sixth tft M6 is controlled to be turned off.
In the third stage t13, Eck1 is low, Eck2 is high, Ein is high, the first thin film transistor M1 and the fifth thin film transistor M5 are turned on, and the second thin film transistor M2 and the fourth thin film transistor M4 are turned off. The initialization signal is transmitted to the gate of the seventh thin film transistor M7 through the first thin film transistor M1 and the eighth thin film transistor M8, and controls the seventh thin film transistor M7 to be turned off, so that the scan signal output terminal SOUT cannot output the second clock signal. The fifth thin film transistor M5 transmits the second power signal to the gate of the sixth thin film transistor M6, controls the sixth thin film transistor M6 to be turned on, and the scan signal output terminal SOUT outputs the first power signal at a high level.
As can be seen from fig. 1 and 2, the gate of the first thin film transistor M1 is electrically connected to the first clock line ECK1, the gate of the fourth thin film transistor M4 is electrically connected to the second pole of the first thin film transistor M1, and the first pole of the fourth thin film transistor M1 is electrically connected to the first clock line ECK 1. The first thin film transistor M1 and the second thin film transistor M2 thus form a phenomenon in which the gate and the source/drain are controlled with each other. At the beginning of the second phase t12, if there is a delay in the first clock signal, which causes the input signal to change from low to high before the first clock signal, or the threshold voltage of the fourth tft M4 is biased positive with respect to the threshold voltage of the first tft M1, the difficulty of turning off the first tft M1 is greater than that of turning off the fourth tft M4, and the fourth tft M4 turns off before the first tft M1. The gate of the sixth thin film transistor M6 maintains the low level of the previous stage due to the maintaining effect of the first storage capacitor Cs1, the sixth thin film transistor M6 is turned on by mistake in the second stage t12, meanwhile, the seventh thin film transistor M7 outputs the second clock signal, the output of the scan signal output terminal SOUT is abnormal, and the reliability of the scan driving circuit is poor, so that the driving process of the pixel unit of the display panel is prone to be problematic.
In view of the above technical problems, an embodiment of the present invention provides a scan driving circuit. Fig. 3 is a schematic structural diagram of a scan driving circuit according to an embodiment of the present invention. As shown in fig. 3, the scan driving circuit includes a first output control module 110, a second output control module 120, a first output module 130, and a second output module 140; the first output control module 110 is electrically connected to the first clock signal input terminal CK1, the input signal terminal EN, the second clock signal input terminal CK2, the first power signal input terminal VL and the first output module 130, the first output module 130 is electrically connected to the second power signal input terminal VH, and the first output control module 110 is configured to control the first output module 130 to output the second power signal input terminal VH according to the first clock signal provided by the first clock signal input terminal CK1, the input signal provided by the input signal terminal EN, the second clock signal provided by the second clock signal input terminal CK2 and the first power signal provided by the first power signal input terminal VL; the second output control module 120 is electrically connected to the first clock signal input terminal CK1, the input signal terminal EN, and the second output module 140, the second output module 140 is electrically connected to the second clock signal input terminal CK2, and the second output control module 120 is configured to control the second output module 140 to output the second clock signal according to the first clock signal and the input signal.
Specifically, the first power signal provided by the first power signal input terminal VL may be low level, and the second power signal provided by the second power signal input terminal VH may be high level. The first clock signal provided by the first clock signal input terminal CK1 and the second clock signal provided by the second clock signal input terminal CK2 may be signals with opposite high and low levels. In the operation process of the scan driving circuit, the first output control module 110 controls the first output module 130 to output the second power signal at a high level, and the second output control module 120 controls the second output module 140 to output the second clock signal, where the second clock signal may be at a high level or a low level. The first output control module 110 and the second output control module 120 are electrically connected to the first clock signal input terminal CK1 at the same time, and the first output control module 110 and the second output control module 120 are not connected to each other, so that a risk competition phenomenon caused by mutual control of the first output control module 110 and the second output control module 120 can be avoided, and further, when the second output control module 120 controls the second output module 140 to output the second scan signal, the first output control module 110 erroneously controls the first output module 130 to output the first scan signal can be avoided, thereby reducing a phenomenon that the scan signal output by the scan driving circuit is abnormal, and improving reliability of the scan driving circuit.
Fig. 4 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention. As shown in fig. 4, the first output control module 110 includes a first transistor T1 and a second transistor T2; a gate of the first transistor T1 is electrically connected to the input signal terminal EN, a first pole of the first transistor T1 is electrically connected to the input terminal of the second clock signal CK2, and a second pole of the first transistor T1 and a second pole of the second transistor T1 are electrically connected to the first output block 130; the gate of the second transistor T2 is electrically connected to the first clock signal input terminal CK1, and the first pole of the second transistor T2 is electrically connected to the first power signal input terminal VL.
Specifically, it is exemplarily shown in fig. 4 that the first transistor T1 and the second transistor T2 are P-type transistors. When the input signal provided by the input signal terminal EN is at a low level, the first transistor T1 is turned on, and the second clock signal provided by the second clock signal input terminal CK2 is transmitted to the first output module 130 through the first transistor T1 to control whether the first output module 130 outputs the first scan signal. When the first clock signal provided by the first clock signal input terminal CK1 is at a low level, the second transistor T2 is turned on, and the first power signal provided by the first power signal input terminal VL is transmitted to the first output module 130 for controlling the first output module 130 to output the first scan signal. When the input signal and the first clock signal are simultaneously at a low level, the first transistor T1 and the second transistor T2 are simultaneously turned on, and at this time, the first power signal and the second clock signal simultaneously control whether the first output module 130 outputs the first scan signal.
Fig. 5 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention. As shown in fig. 5, the first output module 130 includes a third transistor T3 and a first capacitor C1; a gate of the third transistor T3 and a first pole of the first capacitor C1 are electrically connected to a second pole of the first transistor T1 and a second pole of the second transistor T2, a first pole of the third transistor T3 and a second pole of the first capacitor C1 are electrically connected to the second power signal input terminal VH, and a second pole of the third transistor T3 serves as a scan signal output terminal OUT of the scan driving circuit.
Specifically, it is exemplarily shown in fig. 5 that the third transistor T3 is a P-type transistor. When the input signal is at a high level, the first clock signal is at a low level, and the second clock signal is at a high level, the first transistor T1 is turned off, the second transistor T2 is turned on, the first power signal is transmitted to the gate of the third transistor T3 through the second transistor T2, the third transistor T3 is controlled to be turned on, and the scan signal output terminal OUT outputs the second power signal at a high level. At this time, the second control module 120 outputs the input signal to the second output module 140 under the control of the first clock signal, and controls the second output module 140 not to output the second clock signal, i.e. the output of the scan signal output terminal OUT is at a high level.
When the input signal is at a low level, the first clock signal is at a low level, and the second clock signal is at a high level, the first transistor T1 and the second transistor T2 are turned on, and the sum of the potentials of the first power signal and the second clock signal controls the state of the third transistor T3. Since the first power supply signal is at a low level and the second clock signal is at a high level, the sum of the first power supply signal and the second clock signal is greater than the low level, and the third transistor T3 is controlled to be turned off. At this time, the second control module 120 outputs the input signal to the second output module 140 under the control of the first clock signal, and controls the second output module 140 to output the second clock signal at a high level, i.e., the output of the scan signal output terminal OUT is at a high level.
When the input signal is at a high level, the first clock signal is at a high level, and the second clock signal is at a low level, the first transistor T1 and the second transistor T2 are turned off, the gate of the third transistor T3 is in a floating state, and the gate of the third transistor T3 is kept at the previous stage potential by the holding action of the first capacitor C1.
Fig. 6 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention. As shown in fig. 6, the second output control module 120 includes a fourth transistor T4; a gate of the fourth transistor T4 is electrically connected to the first clock signal input terminal CK1, a first pole of the fourth transistor T4 is electrically connected to the input signal terminal EN, and a second pole of the fourth transistor T4 is electrically connected to the second output module 140.
Specifically, it is exemplarily shown in fig. 6 that the fourth transistor T4 is a P-type transistor. When the first clock signal provided by the first clock signal input terminal CK1 is at a low level, the fourth transistor T4 is turned on, and the input signal provided by the input signal terminal EN is transmitted to the second output module 140 through the fourth transistor T4, so as to control whether the second output module 140 outputs the second clock signal provided by the second clock signal input terminal CK 2. In addition, the fourth transistor T4 and the first and second transistors T1 and T2 are not connected to each other, so that a race risk phenomenon caused by mutual control of the fourth transistor T4 and the first and second transistors T1 and T2 can be avoided, and further, a phenomenon that a scan signal output by the scan signal output terminal OUT is abnormal due to misconduction of the first and second transistors T1 and T2 in the operation process of the scan driving circuit can be reduced, thereby improving the reliability of the scan driving circuit.
Fig. 7 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention. As shown in fig. 7, the second output module 140 includes a fifth transistor T5 and a second capacitor C2; a gate of the fifth transistor T5 and a first pole of the second capacitor C2 are electrically connected to a second pole of the fourth transistor T4, a first pole of the fifth transistor T5 is electrically connected to the second clock signal input terminal CK2, and a second pole of the fifth transistor T5 and a second pole of the second capacitor C2 are electrically connected to a second pole of the third transistor T3.
In particular, it is exemplarily shown in fig. 7 that the fifth transistor T5 is a P-type transistor. When the input signal is at a low level and the first clock signal is at a low level, the fourth transistor T4 is turned on, the input signal controls the fifth transistor T5 to be turned on through the fourth transistor T4, and the fifth transistor T5 outputs the second clock signal, i.e., the scan signal output terminal OUT outputs the second clock signal. When the first clock signal is at a high level, the gate of the fifth transistor T5 is in a floating state, and the gate of the fifth transistor T5 is kept at the previous stage potential by the holding action of the second capacitor C2.
Fig. 8 is a timing diagram of the scan driving circuit provided in fig. 7. Where Vl is a timing of the first power signal provided from the first power signal input terminal Vl, Vh is a timing of the second power signal provided from the second power signal input terminal Vh, CK1 is a timing of the first clock signal provided from the first clock signal line CK1, CK2 is a timing of the second clock signal provided from the second clock signal line CK2, EN is a timing of the input signal provided from the input signal line EN, and out is a timing of the scan signal output from the scan driving circuit. The operation of the lighting control circuit is explained in conjunction with fig. 7 and 8.
In the first phase t21, en is high, ck1 is low, ck2 is high, Vl is low, and Vh is high. The second transistor T2 and the fourth transistor T4 are turned on, the first transistor T1 is turned off, the input signal is transmitted to the gate of the fifth transistor T5 through the fourth transistor T4, the fifth transistor T5 is controlled to be turned off, and the fifth transistor T5 cannot transmit the second clock signal to the scan signal output terminal OUT. The second transistor T2 is turned on, so that the first power signal is transmitted to the gate of the third transistor T3 through the second transistor T2, controlling the third transistor T3 to be turned on, the third transistor T3 transmits the second power signal to the scan signal output terminal OUT, and the scan signal output terminal OUT outputs a high level.
In the second phase t22, en is high, ck1 is high, ck2 is low, Vl is low, and Vh is high. The first transistor T1, the second transistor T2, and the fourth transistor T4 are all turned off, the gate of the third transistor T3 and the gate of the fifth transistor T5 are all in a floating state, and the gate of the third transistor T3 is maintained at a low level by the maintaining function of the first capacitor C1, so that the third transistor T3 is turned on, and the scan signal output terminal OUT continues to output a high level. The holding function of the second capacitor C2 maintains the gate of the fifth transistor T5 at a high level, so that the fifth transistor T5 is turned off and the fifth transistor T5 cannot transmit the second clock signal to the scan signal output terminal OUT.
In the third stage t23, en is low, ck1 is low, ck2 is high, Vl is low, and Vh is high. The first transistor T1, the second transistor T2, and the fourth transistor T4 are all turned on, the input signal is transmitted to the gate of the fifth transistor T5 through the fourth transistor T4, the fifth transistor T5 is controlled to be turned on, the second clock signal is output through the fifth transistor T5, and the scan signal output terminal OUT outputs the second clock signal at a high level. Meanwhile, the first transistor T1 transmits the second clock signal to the gate of the third transistor T3, and the second transistor T2 transmits the first power supply signal to the gate of the third transistor T3, where the gate potential of the third transistor T3 is the sum of the second clock signal and the first power supply signal. Since the second clock signal is at a high level, the first power signal is at a low level, and the gate potential of the third transistor T3 is greater than the low-level potential of the first power signal, the third transistor T3 is controlled to be turned off, and the scan signal output terminal OUT cannot output the second power signal. Illustratively, the first power signal may be-7V, and the potential when the second clock signal is high may be 7V. At this time, the gate potential of the third transistor T3 may be 0V, and the third transistor T3 is turned off.
In the fourth phase t24, en is high, ck1 is high, ck2 is low, Vl is low, and Vh is high. The first transistor T1, the second transistor T2, and the fourth transistor T4 are all turned off, the gate of the third transistor T3 and the gate of the fifth transistor T5 are all in a floating state, and the sustain action of the first capacitor C1 maintains the gate of the third transistor T3, so that the third transistor T3 is turned off. The holding function of the second capacitor C2 maintains the gate of the fifth transistor T5 at a low level, so that the fifth transistor T5 is turned on, the fifth transistor T5 transmits the second clock signal to the scan signal output terminal OUT, and the scan signal output terminal OUT outputs the second clock signal at a low level.
In the above process, in the process from the third stage T23 to the fourth stage T24, when the first transistor T1, the second transistor T2, and the fourth transistor T4 are all turned on and turned off, the first transistor T1, the second transistor T2, and the fourth transistor T4 do not affect each other, so that a competitive risk phenomenon caused by mutual control among different transistors can be avoided, and further, the mis-on actions of the first transistor T1 and the second transistor T2 in the working process of the scan driving circuit can be reduced, the abnormal phenomenon of the scan signal output by the scan driving circuit is reduced, and the reliability of the scan driving circuit is improved.
Fig. 9 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention. As shown in fig. 9, the scan driving circuit further includes a sixth transistor T6; a gate of the sixth transistor T6 is electrically connected to the first power signal input terminal VL, and a second pole of the fourth transistor T4 and a gate of the fifth transistor T5 are electrically connected through the sixth transistor T6.
Specifically, since the gate of the sixth transistor T6 is electrically connected to the first power signal input terminal VL, the sixth transistor T6 is always in a conductive state. The second pole of the fourth transistor T4 and the gate of the fifth transistor T5 are electrically connected through the sixth transistor T6, so that the gate of the fifth transistor T5 can be lowered to a low level, and particularly, when the gate potential of the fifth transistor T5 is low due to the coupling effect of the second capacitor C2, the second pole potential of the fourth transistor T4 is driven to be low, which causes the phenomenon that the fourth transistor T4 is damaged due to the overlarge gate-source voltage difference of the fourth transistor T4.
Fig. 10 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention. As shown in fig. 10, the scan driving circuit further includes a seventh transistor T7; a gate of the seventh transistor T7 is electrically connected to the gate of the fifth transistor T5, a first pole of the seventh transistor T7 is electrically connected to the first power signal input terminal VL, and a second pole of the seventh transistor T7 is electrically connected to the second pole of the fourth transistor T4.
Specifically, when the scan signal output from the scan signal output terminal OUT is at a low level in the fourth stage T24, the coupling action of the second capacitor C2 couples the gate of the fifth transistor T5 to a low level, so as to control the seventh transistor T7 to be turned on, and at this time, the first power signal provided from the first power signal input terminal VL is transmitted to the second pole of the fourth transistor T4 through the seventh transistor T7 and transmitted to the gate of the fifth transistor T5 through the sixth transistor T6, so that the probability that the leakage of the fourth transistor T4 causes the input signal provided from the input signal terminal EN to leak to the gate of the fifth transistor T5, which causes the false turn-off of the fifth transistor T5 can be reduced, and thus the stability of the scan driving circuit outputting the scan signal at the low level in the fourth stage T24 can be further improved, the reliability of the scan driving circuit is further improved.
Fig. 11 is a schematic structural diagram of another scan driving circuit according to an embodiment of the present invention. As shown in fig. 11, the fourth transistor T4 is a double gate transistor.
In particular, the double-gate transistor may improve a leakage phenomenon of the transistor. In the fourth stage T24 of the operation of the scan driving circuit, the fourth transistor T4 is a dual-gate transistor, which can reduce the leakage of the fourth transistor T4, thereby reducing the probability of the input signal provided by the input signal terminal EN leaking to the gate of the fifth transistor T5, causing the false turn-off of the fifth transistor T5, further improving the stability of the scan driving circuit outputting the low-level scan signal in the fourth stage T24, and improving the reliability of the scan driving circuit.
The embodiment of the invention also provides a display panel. Fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present invention. As shown in fig. 12, the display panel includes a first clock signal line 20, a second clock signal line 30, a first power signal line 40, a second power signal line 50, an input signal line 60, and at least two scan driving circuits 10 provided in any of the embodiments of the present invention; a first clock signal input terminal of the scan driving circuit 10 is electrically connected to the first clock signal line 20, a second clock signal input terminal is electrically connected to the second clock signal line 30, a first power signal input terminal is electrically connected to the first power signal line 40, and a second power signal input terminal is electrically connected to the second power signal line 50; at least two scanning driving circuits 10 are connected in cascade, and the input signal end of the first scanning driving circuit 10 is electrically connected with an input signal line 60; the scanning signal output end of the previous stage scanning driving circuit 10 is electrically connected with the input signal end of the next stage scanning driving circuit 10.
Specifically, the display panel may be, for example, an organic light emitting diode display panel, a liquid crystal display panel, an electronic paper display panel, or the like. Each stage of the scan driving circuit 10 is electrically connected to a scan line 70 on the display panel, and transmits a scan signal to each scan line 70. The first stage scan driving circuit 10 shifts the input signal on the input signal line 60 and outputs it through its scan signal output terminal. The next-stage scan driving circuit 10 shifts and outputs the scan signal output from the previous-stage scan driving circuit 10. Therefore, the display panel provided by the embodiment of the present invention realizes the function of outputting the scanning signals line by line, and the stability of the scanning signals output by each stage of the scanning driving circuit 10 is good.
With continued reference to fig. 12, on the basis of the above embodiments, the scan driving circuit 10 is optionally disposed on both sides of the display panel. Illustratively, the scan driving circuits 10 located at the left side of the display panel are cascade-connected, sequentially transmitting scan signals to odd-numbered scan lines. The scan driving circuits 10 located on the right side of the display panel are connected in cascade and sequentially transmit scan signals to even number of scan lines. The arrangement of the embodiment of the invention is beneficial to reducing the frame of one side of the display panel occupied by the scanning driving circuit 10, thereby being beneficial to reducing the frame width of the display panel.
The embodiment of the invention also provides a display device. Fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present invention. As shown in fig. 13, the display device includes a display panel 1 provided in any embodiment of the present invention. The display device can be a mobile phone, a tablet computer, intelligent wearable equipment, an information inquiry machine in a hall of a public place and the like. The display device comprises the display panel 1 provided by any embodiment of the invention, and the technical principle and the generated technical effect are similar, and are not described again here.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in some detail by the above embodiments, the invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the invention, and the scope of the invention is determined by the scope of the appended claims.
Claims (10)
1. A scanning drive circuit is characterized by comprising a first output control module, a second output control module, a first output module and a second output module;
the first output control module is electrically connected with a first clock signal input end, an input signal end, a second clock signal input end, a first power signal input end and the first output module, the first output module is electrically connected with a second power signal input end, and the first output control module is used for controlling the first output module to output a second power signal provided by the second power signal input end according to a first clock signal provided by the first clock signal input end, an input signal provided by the input signal end, a second clock signal provided by the second clock signal input end and a first power signal provided by the first power signal input end;
the second output control module is electrically connected with the first clock signal input end, the input signal end and the second output module, the second output module is electrically connected with the second clock signal input end, and the second output control module is used for controlling the second output module to output the second clock signal according to the first clock signal and the input signal.
2. The scan driving circuit according to claim 1, wherein the first output control module includes a first transistor and a second transistor;
the grid electrode of the first transistor is electrically connected with the input signal end, the first electrode of the first transistor is electrically connected with the second clock signal input end, and the second electrode of the first transistor and the second electrode of the second transistor are electrically connected with the first output module; the grid electrode of the second transistor is electrically connected with the first clock signal input end, and the first pole of the second transistor is electrically connected with the first power supply signal input end.
3. The scan driving circuit according to claim 2, wherein the first output module includes a third transistor and a first capacitor;
a gate of the third transistor and a first pole of the first capacitor are electrically connected to a second pole of the first transistor and a second pole of the second transistor, a first pole of the third transistor and a second pole of the first capacitor are electrically connected to the second power supply signal input terminal, and a second pole of the third transistor is used as a scan signal output terminal of the scan driver circuit.
4. The scan driving circuit of claim 3, wherein the second output control module comprises a fourth transistor;
a gate of the fourth transistor is electrically connected to the first clock signal input terminal, a first electrode of the fourth transistor is electrically connected to the input signal terminal, and a second electrode of the fourth transistor is electrically connected to the second output module.
5. The scan driving circuit according to claim 4, wherein the second output module comprises a fifth transistor and a second capacitor;
a gate of the fifth transistor and a first pole of the second capacitor are electrically connected to a second pole of the fourth transistor, the first pole of the fifth transistor is electrically connected to the second clock signal input terminal, and the second pole of the fifth transistor and a second pole of the second capacitor are electrically connected to a second pole of the third transistor.
6. The scan driving circuit according to claim 5, further comprising a sixth transistor;
a gate of the sixth transistor is electrically connected to the first power signal input terminal, and a second pole of the fourth transistor and a gate of the fifth transistor are electrically connected through the sixth transistor.
7. The scan driving circuit according to claim 6, further comprising a seventh transistor;
a gate of the seventh transistor is electrically connected to a gate of the fifth transistor, a first pole of the seventh transistor is electrically connected to the first power signal input terminal, and a second pole of the seventh transistor is electrically connected to the second pole of the fourth transistor.
8. The scan driver circuit according to claim 7, wherein the fourth transistor is a double-gate transistor.
9. A display panel comprising a first clock signal line, a second clock signal line, a first power supply signal line, a second power supply signal line, an input signal line, and at least two scan driver circuits according to any one of claims 1 to 8;
a first clock signal input terminal of the scan driving circuit is electrically connected to the first clock signal line, a second clock signal input terminal of the scan driving circuit is electrically connected to the second clock signal line, a first power signal input terminal of the scan driving circuit is electrically connected to the first power signal line, and a second power signal input terminal of the scan driving circuit is electrically connected to the second power signal line;
at least two scanning driving circuits are connected in a cascade mode, and the input signal end of the first stage of scanning driving circuit is electrically connected with the input signal line; the scanning signal output end of the scanning driving circuit of the previous stage is electrically connected with the input signal end of the scanning driving circuit of the next stage.
10. A display device characterized by comprising the display panel according to claim 9.
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| KR100826997B1 (en) * | 2006-07-21 | 2008-05-06 | 재단법인서울대학교산학협력재단 | Shift registers for gate driver of flat panel displays |
| CN104134430B (en) * | 2014-07-04 | 2016-08-17 | 京东方科技集团股份有限公司 | A kind of shift register, gate driver circuit and display device |
| CN104952406B (en) * | 2015-06-08 | 2017-08-01 | 京东方科技集团股份有限公司 | Shift register and its driving method, gate driving circuit and display device |
| CN106097978B (en) * | 2016-08-19 | 2018-08-03 | 京东方科技集团股份有限公司 | Shifting deposit unit, shift register, gate driving circuit and display device |
| CN107039014B (en) * | 2017-05-26 | 2019-03-05 | 京东方科技集团股份有限公司 | Shift register cell, its driving method, gate driving circuit and display panel |
| CN107863057B (en) * | 2017-10-31 | 2020-12-18 | 上海天马微电子有限公司 | Shift register, driving method thereof, driving control circuit and related device |
| CN107978278B (en) * | 2018-01-19 | 2019-12-24 | 昆山国显光电有限公司 | Scanning circuit, organic light emitting display device and driving method thereof |
| CN109741700B (en) * | 2019-01-10 | 2022-03-18 | 京东方科技集团股份有限公司 | Shift register unit and driving method |
| CN110675836B (en) * | 2019-10-18 | 2021-08-27 | 合肥维信诺科技有限公司 | Scanning circuit, driving method thereof and display panel |
| CN110706656B (en) * | 2019-10-21 | 2021-02-02 | 京东方科技集团股份有限公司 | Shift register, driving method thereof, driving circuit and display device |
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