CN107978278B - Scanning circuit, organic light emitting display device and driving method thereof - Google Patents
Scanning circuit, organic light emitting display device and driving method thereof Download PDFInfo
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- CN107978278B CN107978278B CN201810055616.7A CN201810055616A CN107978278B CN 107978278 B CN107978278 B CN 107978278B CN 201810055616 A CN201810055616 A CN 201810055616A CN 107978278 B CN107978278 B CN 107978278B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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Abstract
The invention provides a scanning circuit, an organic light emitting display device and a driving method thereof, wherein the scanning circuit comprises a first driving circuit, a second driving circuit, an output unit and an isolation transistor, wherein: the first driving circuit generates a first-stage voltage according to signals of the first input end, the second input end, the third input end and the first power supply; the second driving circuit generates a second-stage voltage according to the first-stage voltage, the second input end and signals of a second power supply; the output unit generates an output signal according to the signals of the first-stage voltage, the second-stage voltage, the first power supply and the third input end; the isolation transistor is connected between a first power supply and the output unit. The invention overcomes the problem that the power consumption of the organic light-emitting display device is increased due to larger leakage current between the first power supply and the output signal.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a scan circuit, an organic light emitting display device, and a driving method thereof.
Background
In recent years, many types of display devices have been developed at home and abroad, such as liquid crystal display devices, plasma display devices, electrowetting display devices, electrophoretic display devices, organic light emitting display devices, and the like. The organic light emitting display device utilizes the recombination of electron hole pairs in a specific material to emit light with a specific wavelength to display an image, has the advantages of fast response, low power consumption, light weight, thinness, wide color gamut and the like, and is one of the most concerned technologies in the current flat panel display technology.
As shown in fig. 1, an organic light emitting display device generally includes a display region and a non-display region disposed at a periphery of the display region. The display area is provided with a plurality of scan lines S1, S2 … Sn and data lines D1, D2 … Dm intersecting the scan lines to define a plurality of pixel units 100. The non-display region is provided with a scan driver 200, a data driver 300, an enable signal controller (EM controller or emission control driver) 400, and a timing controller 500. The scan driver 200 is connected to the scan lines for generating scan signals to be inputted to the pixel units, thereby controlling the writing operation of the data signals. The data driver 300 is connected to the data lines for providing data signals to the pixel units 100. The EM controller 400 is connected to EM traces EM1, EM2 … EMn for providing enable signals to the pixel cells 100. The timing controller 500 is used to provide a clock signal to the pixel unit 100. Among them, the scan driver 200 includes a plurality of stage circuits (i.e., a multi-stage scan circuit) connected to the pixel rows through a plurality of scan lines. Each scanning circuit supplies a scanning signal to its corresponding scanning line, and each scanning circuit includes a plurality of Thin Film Transistors (TFTs).
The inventors found that the power consumption of the organic light emitting display device is increased due to the large leakage current of the TFT, which in turn affects the service life of the panel.
Disclosure of Invention
The invention aims to provide a scanning circuit, an organic light-emitting display device and a driving method thereof, and aims to solve the problem that the conventional organic light-emitting display device is high in power consumption.
To solve the above technical problem, the present invention provides a scan circuit, which includes a first driving circuit, a second driving circuit, an output unit, and an isolation transistor, wherein:
the first driving circuit generates a first-stage voltage according to signals of the first input end, the second input end, the third input end and the first power supply;
the first drive circuit includes a first transistor, a second transistor, and a third transistor, wherein:
the first transistor, the second transistor, and the third transistor are P-type thin film transistors;
the grid electrode of the first transistor is connected with the second input end, the source electrode of the first transistor is connected with the drain electrode of the second transistor, and the drain electrode of the first transistor is connected with the first input end;
the grid electrode of the second transistor is connected with the third input end, and the source electrode of the second transistor is connected with the source electrode of the third transistor;
the drain electrode of the third transistor is connected with the first power supply, and the source electrode of the third transistor is connected with the second driving circuit;
the second driving circuit generates a second-stage voltage according to the first-stage voltage, the second input end and signals of a second power supply;
the second drive circuit includes a fourth transistor and a fifth transistor, wherein:
the fourth transistor and the fifth transistor are P-type thin film transistors;
the grid electrode of the fourth transistor is connected with the source electrode of the first transistor, the source electrode of the fourth transistor is connected with the grid electrode of the first transistor, and the drain electrode of the fourth transistor is connected with the grid electrode of the third transistor;
a gate of the fifth transistor is connected to the second input terminal, a source of the fifth transistor is connected to a gate of the third transistor, and a drain of the fifth transistor is connected to a second power supply;
the output unit comprises a sixth transistor and a seventh transistor, the output unit controls the sixth transistor and the seventh transistor to be switched on and off according to the first-stage voltage and the second-stage voltage, and the sixth transistor and the seventh transistor are connected between a first power supply and a third output end to generate an output signal;
the isolation transistor is connected between a first power supply and the sixth transistor.
Optionally, in the scanning circuit, the output unit further includes a first capacitor, a second capacitor, and an output end, where:
the sixth transistor and the seventh transistor are P-type thin film transistors;
the grid electrode of the sixth transistor is connected with the drain electrode of the fourth transistor, the source electrode of the sixth transistor is connected with the isolation transistor, and the drain electrode of the sixth transistor is connected with the source electrode of the seventh transistor;
the source electrode of the seventh transistor is connected with the output end, and the drain electrode of the seventh transistor is connected with the third input end;
one end of the first capacitor is connected with the grid electrode of the sixth transistor, and the other end of the first capacitor is connected with the source electrode of the sixth transistor;
one end of the second capacitor is connected with the grid electrode of the seventh transistor, and the other end of the second capacitor is connected with the source electrode of the seventh transistor;
the output signal generated by the output unit is output from the output terminal.
Optionally, in the scanning circuit, the isolation transistor is a P-type thin film transistor, a gate of the isolation transistor is connected to the third input terminal, a source of the isolation transistor is connected to the first power supply, and a drain of the isolation transistor is connected to a source of the sixth transistor.
Optionally, in the scanning circuit, the second driving circuit further includes an eighth transistor, the eighth transistor is a P-type thin film transistor, a gate of the eighth transistor is connected to a source of the fourth transistor, a source of the eighth transistor is connected to a gate of the seventh transistor, and a drain of the eighth transistor is connected to a gate of the fourth transistor.
Optionally, in the scanning circuit, the gate of the sixth transistor inputs the first-stage voltage, and the gate of the seventh transistor inputs the second-stage voltage.
Optionally, in the scan circuit, the first input terminal receives an output signal or a start signal of a previous scan circuit, the second input terminal of the odd scan circuit receives a first clock signal, the third input terminal receives a second clock signal, the second input terminal of the even scan circuit receives a second clock signal, and the third input terminal receives the first clock signal.
Optionally, in the scanning circuit, the first clock signal and the second clock signal have the same time period and have non-overlapping phases, and the start signal and the first clock signal have the same time period and have overlapping phases.
Optionally, in the scan circuit, a voltage value of the first power supply is higher than a voltage value of the second power supply.
The present invention also provides an organic light emitting display device including a plurality of scanning circuits as described in any one of the above.
The present invention also provides a driving method of the organic light emitting display device, including:
in the first stage, the start signal and the first clock signal are supplied to a low level, and the second clock signal is supplied to a high level;
in a second phase, the start signal is provided at a low level, and the first clock signal and the second clock signal are provided at a high level;
in a third phase, the start signal and the second clock signal are provided at a low level, the first clock signal is provided at a high level;
in the fourth phase, the first clock signal is supplied at a low level, and the start signal and the second clock signal are supplied at a high level.
In a scan circuit, an organic light emitting display device and a driving method thereof according to the present invention, a sixth transistor provided between a first power supply and an output signal, supplying the voltage of the first power source to the output signal when turned on, turning off when the output signal needs to output a low level to prevent the voltage of the first power source from being coupled with the output signal, but due to the unstable performance or failure condition of the transistor, and the problem of affecting the performance along with the prolonging of the service life of the transistor, it may result in the sixth transistor being turned off incompletely, and therefore an isolation transistor is provided between the first power supply and the sixth transistor, preventing the sixth transistor from being turned off incompletely when it should be turned off, coupling between the first power supply and the output signal, therefore, the problem that the leakage current is large and the power consumption of the organic light-emitting display device is increased due to the fact that the leakage current is provided for the output unit is caused, and the influence on the service life of the screen body is further reduced.
Further, the first to ninth transistors are all P-type thin film transistors or N-type thin film transistors. The P-type thin film transistor is turned on when the gate signal is at a low level, and the N-type thin film transistor is turned on when the gate signal is at a high level. Therefore, it is sufficient to match the selected transistor type with the on potential.
In addition, the first capacitor has a bootstrap effect, the voltage difference between two ends cannot change suddenly, so that the voltage between the grid electrode and the source electrode of the sixth transistor cannot change suddenly and keeps stable, and the sixth transistor is switched on or switched off stably; similarly, the voltage difference between the two ends of the second capacitor can keep the voltage between the gate and the source of the seventh transistor stable, so that the seventh transistor is switched on or off stably.
Drawings
Fig. 1 is a schematic structural view of an organic light emitting display device;
FIG. 2 is a schematic diagram of a scan circuit according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating waveforms of input signals and waveforms of output signals of a scan circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a scan circuit according to another embodiment of the present invention;
shown in the figure: 10-a first drive circuit; 11-a first input; 12-a second input; 13-a third input; 20-a second drive circuit; 30-an output unit; 31-an output terminal; 100-pixel cells; 200-a scan driver; 300-a data driver; 400-enable signal controller; 500-a time schedule controller.
Detailed Description
The scanning circuit, the organic light emitting display device and the driving method thereof according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
FIG. 2 is a schematic diagram of a scan circuit according to an embodiment of the invention. As shown in fig. 2, the scan circuit includes a first drive circuit 10, a second drive circuit 20, an output unit 30, and an isolation transistor M9, wherein: the first driving circuit 10 generates a first stage voltage V1 according to the signals of the first input terminal 11, the second input terminal 12, the third input terminal 13 and the first power supply VGH; the second driving circuit 20 generates a second stage voltage V2 according to the first stage voltage V1, the second input terminal 12 and signals of a second power source VGL; the output unit 30 generates an output signal according to the first stage voltage V1, the second stage voltage V2, the first power supply VGH, and the signal of the third input terminal 13; the isolation transistor M9 is connected between the first power source VGH and the sixth transistor M6.
The inventor researches and finds that, in the scan circuit, the output signal generated by the output unit 30 depends on the first power VGH and other voltages (the first stage voltage V1, the second stage voltage V2 and the third input terminal 13), the output unit 30 includes a sixth transistor M6, the sixth transistor M6 is used for switching the output signal between the first power VGH and other voltages, but due to performance and lifetime problems, the sixth transistor M6 is not completely turned off when the output signal is switched from the first power to other voltages, and a leakage current flowing from the first power to the sixth transistor and supplied to the output unit is large, which causes an increase in power consumption of the organic light emitting display device and further affects the service life of the screen body.
The isolation transistor M9 is connected between the first power supply VGH and the output unit 30, so that the sixth transistor between the first power supply VGH and the output power supply 30 is prevented from being turned off incompletely due to the performance and service life problems, the leakage current is large and is provided for the output unit 30, the problem of power consumption increase of the organic light-emitting display device caused by the leakage current output by the output unit is avoided, and the influence on the service life of the screen body is further reduced.
The first driving circuit 10 includes, for example, a first transistor M1, a second transistor M2, and a third transistor M3, in which: the first transistor M1, the second transistor M2, and the third transistor are P-type thin film transistors; the gate of the first transistor M1 is connected to the second input terminal 12, the source of the first transistor M1 is connected to the drain of the second transistor M2, and the drain of the first transistor M1 is connected to the first input terminal 11; the gate of the second transistor M2 is connected to the third input terminal 13, and the source of the second transistor M2 is connected to the source of the third transistor M3; the drain of the third transistor M3 is connected to the first power source VGH, and the source of the third transistor M3 is connected to the second driving circuit 20.
The second driving circuit 20 includes, for example, a fourth transistor M4 and a fifth transistor M5, in which: the fourth transistor M4 and the fifth transistor M5 are P-type thin film transistors; the gate of the fourth transistor M4 is connected to the source of the first transistor M1, the source of the fourth transistor M4 is connected to the gate of the first transistor M1, and the drain of the fourth transistor M4 is connected to the gate of the third transistor M3; the gate of the fifth transistor M5 is connected to the second input terminal 12, the source of the fifth transistor M5 is connected to the gate of the third transistor M3, and the drain of the fifth transistor M5 is connected to a second power source VGL.
As shown in fig. 2, in the scan circuit, the output unit 30 includes a sixth transistor M6, a seventh transistor M7, a first capacitor C1, a second capacitor C2, and an output terminal 31, the output unit controls the sixth transistor and the seventh transistor to be turned on and off according to the first stage voltage and the second stage voltage, and the sixth transistor and the seventh transistor are connected between a first power supply and a third output terminal to generate an output signal; wherein: the sixth transistor M6 and the seventh transistor M7 are P-type thin film transistors; the gate of the sixth transistor M6 is connected to the drain of the fourth transistor M4, the source of the sixth transistor M6 is connected to the isolation transistor M9, and the drain of the sixth transistor M6 is connected to the source of the seventh transistor M7; the gate of the seventh transistor M7 is connected to the gate of the fourth transistor M4, the source of the seventh transistor M7 is connected to the output terminal 31, and the drain of the seventh transistor M7 is connected to the third input terminal 13; the first capacitor C1 has one end connected to the gate of the sixth transistor M6 and the other end connected to the source of the sixth transistor M6; one end of the second capacitor C2 is connected to the gate of the seventh transistor M7, and the other end is connected to the source of the seventh transistor M7; the output signal generated by the output unit 30 is output from the output terminal 31.
The isolation transistor M9 is, for example, a P-type thin film transistor, the gate of the isolation transistor M9 is connected to the third input terminal 13, the source of the isolation transistor M9 is connected to the first power source VGH, and the drain of the isolation transistor M9 is connected to the source of the sixth transistor M6. The second driving circuit 20 further includes an eighth transistor M8, the eighth transistor M8 is used for dividing voltage and preventing the second-level voltage V2 from being too high, the eighth transistor M8 is a P-type thin film transistor, a gate of the eighth transistor M8 is connected to a source of the fourth transistor M4, a source of the eighth transistor M8 is connected to a gate of the seventh transistor M7, and a drain of the eighth transistor M8 is connected to a gate of the fourth transistor M4.
The gate of the sixth transistor M6 inputs the first stage voltage V1, and the gate of the seventh transistor M7 inputs the second stage voltage V2. As shown in fig. 3, the first input terminal 11 receives the output signal or the start signal SIN of the previous scan circuit, and since the plurality of scan circuits are connected end to end, in the sequential arrangement of the scan circuits, the second input terminal 12 of the odd scan circuit receives the first clock signal SCK1, the third input terminal 13 receives the second clock signal SCK2, the second input terminal 12 of the even scan circuit receives the second clock signal, and the third input terminal receives the first clock signal, i.e., the clock signals of the odd scan circuit and the even scan circuit are opposite in phase, and fig. 3 illustrates the timing of the odd scan circuit. The first clock signal SCK1 and the second clock signal SCK2 have the same period and have non-overlapping phases, and the start signal SIN has the same period and have overlapping phases with the first clock signal SCK 1. The voltage value of the first power supply VGH is higher than that of the second power supply VGL.
In this embodiment, the first to ninth transistors are all P-type thin film transistors. In other embodiments, the first to ninth transistors may also be N-type thin film transistors. The P-type thin film transistor is turned on when the gate signal is at a low level, and the N-type thin film transistor is turned on when the gate signal is at a high level. Therefore, it is sufficient to match the selected transistor type with the on potential.
The present embodiment further provides a scan driver, where the scan driver includes a plurality of scan circuits as described in any of the above, and a first input terminal of each scan circuit is connected to an output unit of a previous scan circuit.
The present embodiment also provides an organic light emitting display device including a plurality of scan circuits as described above.
The present embodiment also provides a driving method of the organic light emitting display device of the above claims, comprising: in the first phase, the start signal SIN and the first clock signal SCK1 are supplied at a low level, and the second clock signal SCK2 is supplied at a high level; in the second phase, the start signal SIN is supplied to a low level, and the first clock signal SCK1 and the second clock signal SCK2 are supplied to a high level; in the third phase, the start signal SIN and the second clock signal SCK2 are provided at a low level, and the first clock signal SCK1 is provided at a high level; in the fourth phase, the first clock signal SCK1 is supplied to a low level, and the start signal SIN and the second clock signal SCK2 are supplied to a high level.
In the first phase P1, when the first clock signal SCK1 is supplied (i.e., low level), the first transistor M1, the fifth transistor M5, the eighth transistor M8 and the isolation transistor M9 are turned on. When the first transistor M1 and the eighth transistor M8 are turned on, the first input terminal 11 and the second stage voltage V2 are electrically connected to each other. In this case, the second stage voltage V2 is set to a low voltage by the start signal SIN supplied to the first input terminal 11. When the second stage voltage V2 is set to a low voltage, the seventh transistor M7 and the fourth transistor M4 are turned on.
When the seventh transistor M7 is turned on, the third input terminal 13 and the output terminal 31 are electrically connected to each other. Here, the third input terminal 13 is set at a high voltage (i.e., the second clock signal SCK2) so that the high voltage is output to the output terminal 31, and the output signal SCAN is as shown in fig. 3. When the fourth transistor M4 is turned on, the second input terminal 12 and the first stage voltage V1 are electrically connected to each other. Then, the voltage (i.e., low voltage) of the first clock signal SCK1 supplied to the second input terminal 12 is supplied to the first stage voltage V1. Further, since the fifth transistor M5 is turned on, the voltage of the second power source VGL is supplied to the first stage voltage V1 where the voltage of the second power source VGL is set to a low level, so that the first stage voltage V1 stably maintains the low voltage.
When a low voltage is supplied to the first stage voltage V1, the sixth transistor M6 and the third transistor M3 are turned on. When the third transistor M3 is turned on, the first power source VGH and the second transistor M2 are electrically connected to each other. Since the second transistor M2 is set in an off state, although the third transistor M3 is turned on, the second stage voltage V2 stably maintains a low voltage. When the sixth transistor M6 is turned on, since the isolation transistor M9 is also turned on, the voltage of the first power source VGH is supplied to the output terminal 31. The voltage of the first power supply VGH is set to a high voltage so that the output terminal 31 stably maintains the high voltage.
In the second phase P2, the supply of the first clock signal SCK1 is stopped. When the supply of the first clock signal SCK1 is stopped, the first transistor M1, the fifth transistor M5, the eighth transistor M8, and the isolation transistor M9 are turned off. At this time, the seventh transistor M7 and the fourth transistor M4 maintain a turn-on state according to the voltage stored in the second capacitor C2. When the seventh transistor M7 remains in the on state, the output terminal 31 and the third input terminal 13 remain electrically connected. Therefore, the output terminal 31 receives a high voltage from the third input terminal 13.
On the other hand, since the fourth transistor M4 maintains the on state, the first stage voltage V1 and the second input terminal 12 are electrically connected to each other. Here, since the supply of the first clock signal SCK1 is stopped, the voltage of the second input terminal 12 is set to a high voltage, and thus the first stage voltage V1 is set at a high voltage. When the high voltage is supplied to the first stage voltage V1, the sixth transistor M6 is turned off.
In the third stage P3, the supply of the start signal SIN is stopped, and the second clock signal SCK2 is supplied to the third input terminal 13. At this time, since the seventh transistor M7 is set in a turned-on state, the second clock signal SCK2 supplied to the third input terminal 13 is supplied to the output terminal 31, and the output signal SCAN is outputted at a low level. In this case, the output terminal 31 outputs the second clock signal SCK2 as a scan signal to the scan line S1 of the organic light emitting display device. In addition, at this time, if the sixth transistor M6 is turned off incompletely, a leakage current may be output to the output terminal 31, which may cause a high-level leakage current in the scan line, which may affect the power consumption of the entire display device, and at this time, the isolation transistor M9 is in an off state, which may effectively further apply the turn-off to cut off the leakage current.
In the fourth stage P4, after the scan signal is output to the scan line S1, the first clock signal SCK1 is supplied, and the supply of the second clock signal SCK2 is stopped. When the first clock signal SCK1 is supplied, the first transistor M1, the fifth transistor M5, the eighth transistor M8, and the isolation transistor M9 are turned on. When the first transistor M1 is turned on, the first input terminal 11 and the second stage voltage V2 are electrically connected to each other. At this time, the start signal SIN is not supplied to the first input terminal 11, so that the first input terminal 11 is set at a high voltage. Accordingly, when the first transistor M1 is turned on, a high voltage is supplied to the second stage voltage V2, so that the seventh transistor M7 and the fourth transistor M4 are turned off. When the fifth transistor M5 is turned on, the second power source VGL is supplied to the first stage voltage V1, so that the third transistor M3 and the sixth transistor M6 are turned on. When the sixth transistor M6 is turned on, the voltage of the first power supply VGH is supplied to the output terminal 31. Then, the sixth transistor M6 and the third transistor M3 maintain a turned-on state according to the voltage charged in the first capacitor C1, so that the output terminal 31 stably receives the voltage of the first power supply VGH.
In addition, since the function of the fourth transistor M4 can be replaced by the ninth transistor M9 in the above process, the fourth transistor M4 can be omitted, as shown in fig. 4, and the on/off states of the transistors in each stage are similar to the above analysis and are not repeated.
The second scan circuit receives an output signal (i.e., a scan signal) of the first scan circuit in synchronization with the second clock signal SCK 2. The scan driver using the plurality of stage circuits according to the first embodiment sequentially supplies a plurality of scan signals to a plurality of scan lines. Further, the plurality of stage circuits according to the first embodiment output the plurality of scan signals to the plurality of scan lines using only the first clock signal SCK1 and the second clock signal SCK 2. That is, the plurality of stage circuits according to the present invention do not receive an additional initialization signal, so that the width of the scan signal can be set to be large (e.g., 1H).
In a scan circuit, an organic light emitting display device and a driving method thereof according to the present invention, a sixth transistor provided between a first power supply and an output signal, supplying the voltage of the first power source to the output signal when turned on, turning off when the output signal needs to output a low level to prevent the voltage of the first power source from being coupled with the output signal, but due to the unstable performance or failure condition of the transistor, and the problem of affecting the performance along with the prolonging of the service life of the transistor, it may result in the sixth transistor being turned off incompletely, and therefore an isolation transistor is provided between the first power supply and the sixth transistor, preventing the sixth transistor from being turned off incompletely when it should be turned off, coupling between the first power supply and the output signal, therefore, the problem that the leakage current is large and the power consumption of the organic light-emitting display device is increased due to the fact that the leakage current is provided for the output unit is caused, and the influence on the service life of the screen body is further reduced.
Further, the first to ninth transistors are all P-type thin film transistors or N-type thin film transistors. The P-type thin film transistor is turned on when the gate signal is at a low level, and the N-type thin film transistor is turned on when the gate signal is at a high level. Therefore, it is sufficient to match the selected transistor type with the on potential.
In addition, the first capacitor has a bootstrap effect, the voltage difference between two ends cannot change suddenly, so that the voltage between the grid electrode and the source electrode of the sixth transistor cannot change suddenly and keeps stable, and the sixth transistor is switched on or switched off stably; similarly, the voltage difference between the two ends of the second capacitor can keep the voltage between the gate and the source of the seventh transistor stable, so that the seventh transistor is switched on or off stably.
In summary, the above embodiments have described the different configurations of the scan circuit in detail, and it is needless to say that the present invention includes but is not limited to the configurations listed in the above embodiments, and any modifications based on the configurations provided by the above embodiments are within the scope of the present invention. One skilled in the art can take the contents of the above embodiments to take a counter-measure.
Claims (9)
1. A scanning circuit, comprising a first drive circuit, a second drive circuit, an output unit, and an isolation transistor, wherein:
the first driving circuit generates a first-stage voltage according to signals of the first input end, the second input end, the third input end and the first power supply;
the first drive circuit includes a first transistor, a second transistor, and a third transistor, wherein:
the first transistor, the second transistor, and the third transistor are P-type thin film transistors;
the grid electrode of the first transistor is connected with the second input end, the source electrode of the first transistor is connected with the drain electrode of the second transistor, and the drain electrode of the first transistor is connected with the first input end;
the grid electrode of the second transistor is connected with the third input end, and the source electrode of the second transistor is connected with the source electrode of the third transistor;
the drain electrode of the third transistor is connected with the first power supply, and the source electrode of the third transistor is connected with the second driving circuit;
the second driving circuit generates a second-stage voltage according to the first-stage voltage, the second input end and signals of a second power supply;
the second drive circuit includes a fourth transistor and a fifth transistor, wherein:
the fourth transistor and the fifth transistor are P-type thin film transistors;
the grid electrode of the fourth transistor is connected with the source electrode of the first transistor, the source electrode of the fourth transistor is connected with the grid electrode of the first transistor, and the drain electrode of the fourth transistor is connected with the grid electrode of the third transistor;
a gate of the fifth transistor is connected to the second input terminal, a source of the fifth transistor is connected to a gate of the third transistor, and a drain of the fifth transistor is connected to a second power supply;
the output unit comprises a sixth transistor and a seventh transistor, the output unit controls the sixth transistor and the seventh transistor to be switched on and off according to the first-stage voltage and the second-stage voltage, and the sixth transistor and the seventh transistor are connected between a first power supply and a third output end to generate an output signal;
the isolation transistor is connected between a first power supply and the sixth transistor;
the second driving circuit further comprises an eighth transistor, the eighth transistor is a P-type thin film transistor, the gate of the eighth transistor is connected with the source of the fourth transistor, the source of the eighth transistor is connected with the gate of the seventh transistor, and the drain of the eighth transistor is connected with the gate of the fourth transistor.
2. The scan circuit of claim 1, wherein the output unit further comprises a first capacitor, a second capacitor, and an output terminal, wherein:
the sixth transistor and the seventh transistor are P-type thin film transistors;
the grid electrode of the sixth transistor is connected with the drain electrode of the fourth transistor, the source electrode of the sixth transistor is connected with the isolation transistor, and the drain electrode of the sixth transistor is connected with the source electrode of the seventh transistor;
the source electrode of the seventh transistor is connected with the output end, and the drain electrode of the seventh transistor is connected with the third input end;
one end of the first capacitor is connected with the grid electrode of the sixth transistor, and the other end of the first capacitor is connected with the source electrode of the sixth transistor;
one end of the second capacitor is connected with the grid electrode of the seventh transistor, and the other end of the second capacitor is connected with the source electrode of the seventh transistor;
the output signal generated by the output unit is output from the output terminal.
3. The scan circuit of claim 2, wherein the isolation transistor is a P-type thin film transistor, a gate of the isolation transistor is connected to the third input terminal, a source of the isolation transistor is connected to the first power supply, and a drain of the isolation transistor is connected to a source of the sixth transistor.
4. The scan circuit according to claim 3, wherein a gate of the sixth transistor is input with the first-stage voltage, and a gate of the seventh transistor is input with the second-stage voltage.
5. The scan circuit of claim 1, wherein the first input terminal receives an output signal or a start signal of a previous scan circuit, the second input terminal of an odd scan circuit receives a first clock signal, the third input terminal receives a second clock signal, the second input terminal of an even scan circuit receives a second clock signal, and the third input terminal receives a first clock signal.
6. The scan circuit of claim 5, wherein the first clock signal and the second clock signal have a same time period and have non-overlapping phases, the start signal having a same time period and having overlapping phases with the first clock signal.
7. The scan circuit of claim 1, wherein a voltage value of the first power supply is higher than a voltage value of the second power supply.
8. An organic light emitting display device comprising a plurality of scanning circuits according to any one of claims 1 to 7.
9. A method of driving the organic light emitting display device according to claim 8, comprising:
in the first stage, the start signal and the first clock signal are supplied to a low level, and the second clock signal is supplied to a high level;
in a second phase, the start signal is provided at a low level, and the first clock signal and the second clock signal are provided at a high level;
in a third phase, the start signal and the second clock signal are provided at a low level, the first clock signal is provided at a high level;
in the fourth phase, the first clock signal is supplied at a low level, and the start signal and the second clock signal are supplied at a high level.
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| CN201810055616.7A CN107978278B (en) | 2018-01-19 | 2018-01-19 | Scanning circuit, organic light emitting display device and driving method thereof |
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| CN111540295A (en) * | 2020-04-27 | 2020-08-14 | 昆山国显光电有限公司 | Shifting register unit, grid driving circuit and display device |
| CN111785199B (en) * | 2020-07-10 | 2022-08-23 | 昆山国显光电有限公司 | Scanning driving circuit, display panel and display device |
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| KR20080006037A (en) * | 2006-07-11 | 2008-01-16 | 삼성전자주식회사 | Shift register, display device including shift register, driving apparatus of shift register and display device |
| KR101573460B1 (en) * | 2009-04-30 | 2015-12-02 | 삼성디스플레이 주식회사 | Gate driving circuit |
| KR101962432B1 (en) * | 2012-09-20 | 2019-03-27 | 삼성디스플레이 주식회사 | Stage Circuit and Organic Light Emitting Display Device Using the same |
| CN103198783B (en) * | 2013-04-01 | 2015-04-29 | 京东方科技集团股份有限公司 | Shifting register unit, shifting register and display device |
| CN103928056B (en) * | 2014-03-06 | 2017-02-08 | 厦门天马微电子有限公司 | Shifting register, gate driving circuit, array substrate, display panel and device |
| CN105139795B (en) * | 2015-09-22 | 2018-07-17 | 上海天马有机发光显示技术有限公司 | A kind of gate scanning circuit and its driving method, gated sweep cascade circuit |
| CN105810142B (en) * | 2016-05-20 | 2019-09-27 | 上海天马有机发光显示技术有限公司 | Shifting deposit unit and its driving method, shift-register circuit, display device |
| CN107358923B (en) * | 2017-07-12 | 2018-09-18 | 深圳市华星光电半导体显示技术有限公司 | Scan drive circuit and display device |
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