CN103928056B - Shifting register, gate driving circuit, array substrate, display panel and device - Google Patents
Shifting register, gate driving circuit, array substrate, display panel and device Download PDFInfo
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- CN103928056B CN103928056B CN201410079598.8A CN201410079598A CN103928056B CN 103928056 B CN103928056 B CN 103928056B CN 201410079598 A CN201410079598 A CN 201410079598A CN 103928056 B CN103928056 B CN 103928056B
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Abstract
The invention discloses a shifting register which comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a voltage division component, wherein a grid of the fifth transistor is electrically connected with a drain of the third transistor through the voltage division component. The embodiment of the invention at least achieves one of the following effects: the shifting register can be adopted to prevent output signal's wave form distortion caused by leak current so as to raise display quality of a display device, minimize the number of photomasks and reduce the influence of process capability on yield, and then capacity is raised and cost is decreased.
Description
Technical field
The present invention relates to display technology field, more particularly, to a kind of shift register, gate driver circuit, tft array base
Plate, display floater and display device.
Background technology
Recently, Display Technique quickly grows, and display device also becomes more and more popular, but actually used middle discovery, display dress
TFT in the tft array substrate put（Thin Film Transistor, thin film transistor (TFT)）There is leakage problem, and then lead
Cause the bad display of display device, have impact on the display quality of display device.
Content of the invention
In view of this, the embodiment of the present invention provides a kind of shift register, gate driver circuit, tft array substrate, display
Panel and display device.
In a first aspect, the embodiment of the present invention provides a kind of shift register, including：The first transistor, transistor seconds,
Three transistors, the 4th transistor, the 5th transistor, sectional pressure element, the first electric capacity and the second electric capacity；
The grid electrical connection outfan of described the first transistor, drain electrode electrical connection the first level signal line, source electrode electricity respectively
Connect the drain electrode of described transistor seconds and the grid of described 4th transistor；
The grid of described transistor seconds electrically connects the first clock cable, and source electrode electrically connects second electrical level holding wire；
The grid of described third transistor electrically connects described first clock cable, and source electrode electrically connects input, and drain electrode is logical
Cross described second electric capacity and electrically connect described outfan；
The drain electrode of described 4th transistor electrically connects described first level signal line, and source electrode electrically connects described outfan, grid
Pole electrically connects described first level signal line by described first electric capacity；
The drain electrode of described 5th transistor electrically connects described outfan, and source electrode electrically connects second clock holding wire, and grid leads to
Cross the drain electrode that described sectional pressure element is electrically connected to described third transistor.
Second aspect, the embodiment of the present invention also provides a kind of gate driver circuit, including：The first party that n level is connected step by step
The shift register in face, wherein, n is positive integer；
The input of the 1st grade of shift register receives initial signal, and the input electrical connection of m level shift register is described
The outfan of m-1 level shift register, wherein, m be more than or equal to 2 and less than or equal to n positive integer.
The third aspect, the embodiment of the present invention also provides a kind of tft array substrate, including the grid of second aspect as described above
Drive circuit.
Fourth aspect, the embodiment of the present invention also provides a kind of display floater, including the tft array of the third aspect as described above
Substrate.
5th aspect, the embodiment of the present invention also provides a kind of display device, including the display surface of fourth aspect as described above
Plate.
Shift register provided in an embodiment of the present invention, gate driver circuit, tft array substrate, display floater and aobvious
In showing device, the grid of the 5th transistor is electrically connected to the drain electrode of described third transistor by described sectional pressure element.The present invention
Embodiment is at least up to one of following effect：The shift register of the present invention can prevent the output signal being caused by leakage current
Wave distortion, thus improving the display quality of display device, reduce light shield mask plate quantity, reduce technological ability to yield
Impact, thus improving production capacity, reduces cost.
Brief description
By reading the detailed description that non-limiting example is made made with reference to the following drawings, other of the present invention
Feature, objects and advantages will become more apparent upon：
Fig. 1 is the internal structure schematic diagram of the shift register of prior art；
Fig. 2 is the level that the shift register in Fig. 1 is 5 volts and second electrical level signal when the level value of the first level signal
When being worth for -5 volt, the oscillogram of the output signal of outfan OUT；
Fig. 3 is the electricity that the shift register in Fig. 1 is 10 volts and second electrical level signal when the level value of the first level signal
When level values are -5 volt, the oscillogram of the output signal of outfan OUT；
Fig. 4 is a kind of internal structure schematic diagram of shift register of the embodiment of the present invention one；
Fig. 5 is the oscillogram of each signal with regard to the shift register in Fig. 4；
Fig. 6 is the electricity that the shift register in Fig. 4 is 10 volts and second electrical level signal when the level value of the first level signal
When level values are -5 volt, the oscillogram of the output signal of outfan OUT；
Fig. 7 is a kind of structured flowchart of gate driver circuit of the embodiment of the present invention two；
Fig. 8 a is the structural representation of the tft array substrate of monolateral driving of the embodiment of the present invention three；
Fig. 8 b is the structural representation of the tft array substrate of bilateral driving of the embodiment of the present invention three.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention, rather than limitation of the invention.It also should be noted that, in order to just
Part related to the present invention rather than full content is illustrate only in description, accompanying drawing.
During display device work, the gate driver circuit in display device will be scanned action, seriatim to control
Each scan line in tft array substrate processed is so that data signal can be transferred to each display in tft array substrate
Unit.Such scanning motion is to be completed by the shift register in gate driver circuit.
Fig. 1 is the internal structure schematic diagram of the shift register of prior art.Referring to Fig. 1, shift register includes：First
The grid electrical connection outfan OUT of PMOS P1, drain electrode electrical connection the first level signal line VG1, source electrode is electrically connected second
The drain electrode of PMOS P2 and the grid of the 4th PMOS P4；The grid of the second PMOS P2 electrically connects the first clock cable CK1,
Source electrode electrically connects second electrical level holding wire VG2；The grid of the 3rd PMOS P3 electrically connects the first clock cable CK1, source electrode electricity
Connect input IN, drain electrode electrically connects outfan OUT by the second electric capacity C2；Drain electrode electrical connection first electricity of the 4th PMOS P4
Flat holding wire VG1, source electrode electrically connects outfan OUT, and grid passes through the first electric capacity C1 and electrically connects the first level signal line VG1；The
The drain electrode electrical connection outfan OUT of five PMOS P5, source electrode electrically connects second clock holding wire CK2, and grid is electrically connected to the 3rd
The drain electrode of PMOS P3.Wherein, the first level signal line VG1 exports the first level signal, and the first level signal is constant height
Level signal, its level value is 5V to 20V；Second electrical level holding wire VG2 exports second electrical level signal, and second electrical level signal is perseverance
Fixed low level signal, its level value is -20V to -5V.
Fig. 2 is the level that the shift register in Fig. 1 is 5 volts and second electrical level signal when the level value of the first level signal
When being worth for -5 volt, the oscillogram of the output signal of outfan OUT.As shown in Fig. 2 it was discovered by researchers that working as the electricity of drive signal
Level values（The i.e. absolute value of the difference of level value of the level value of the first level signal and second electrical level signal）During for 10 volts, obtain
The waveform comparison of output signal is normal.But, research worker has done the level value studying and increased drive signal further.Figure
3 be shift register in Fig. 1 when the level value that the level value of the first level signal is 10 volts and second electrical level signal be -5 volts
When, the oscillogram of the output signal of outfan OUT.The relatively oscillogram of Fig. 3 and Fig. 2, research worker is it has furthermore been found that work as first
The level value of level signal is the level value of 10 volts and second electrical level signal when being -5 volt, that is, when the level value of drive signal increases
During to 15 volts, because leakage current is consequently increased, so that distortion in the waveform of output signal that outfan OUT obtains（Ginseng
See a in Fig. 3）.
To sum up, if research worker through research it has furthermore been found that the grid of the 5th PMOS P5 in Fig. 1 is passed through wire is electric
Connect and be changed to the drain electrode of the 3rd PMOS P3：The grid of the 5th PMOS P5 is electrically connected to the 3rd PMOS by sectional pressure element
The drain electrode of P3, then can prevent leakage current from causing the wave distortion of the output signal of shift register, thus improving display quality.
Wherein, sectional pressure element can be at least one transistor（Below for convenience of description, the embodiment of the present invention with a transistor is only
Example is illustrating, but the embodiment of the present invention is not limited to the quantity of transistor, only need to meet at least one transistor, and those are extremely
A few transistor is all applied in control signal and turns on）, that is,：The source electrode of this transistor or drain electrode and the 5th PMOS
The grid electrical connection of pipe P5, drain electrode or source electrode are electrically connected with the drain electrode of the 3rd PMOS P3, and grid is applied in a control
Signal, and the conducting of this control signal controlling transistor；Or, sectional pressure element can also be permissible for the diode of conducting, diode
By grid and source electrode（Or drain electrode）The audion of short circuit is formed.Related is described in detail below.
Embodiment one
The embodiment of the present invention one provides a kind of shift register.Fig. 4 is a kind of shift register of the embodiment of the present invention one
Internal structure schematic diagram.As shown in figure 4, shift register includes：The first transistor M1, transistor seconds M2, the 3rd crystal
Pipe M3, the 4th transistor M4, the 5th transistor M5, sectional pressure element（Not shown）, the first electric capacity C1 and the second electric capacity C2, wherein,
The grid of the 5th transistor M5 is electrically connected to the drain electrode of described third transistor M3 by sectional pressure element；Further, partial pressure unit
Part is the 6th transistor M6；
Specifically, the grid electrical connection outfan OUT of the first transistor M1, drain electrode electrical connection the first level signal line VG1,
Source electrode is electrically connected the drain electrode of transistor seconds M2 and the grid of the 4th transistor M4；The grid electrical connection of transistor seconds M2
First clock cable CK1, source electrode electrically connects second electrical level holding wire VG2；During the grid electrical connection first of third transistor M3
Clock holding wire CK1, source electrode electrically connects input IN, and drain electrode electrically connects outfan OUT by the second electric capacity C2；4th transistor M4
Drain electrode electrically connect the first level signal line VG1, source electrode electrically connects outfan OUT, and grid passes through the first electric capacity C1 electrical connection the
One level signal line VG1；The drain electrode electrical connection outfan OUT of the 5th transistor M5, source electrode electrically connects second clock holding wire
CK2；The grid of the 6th transistor M6 is applied in a three level signal VGP, the drain electrode of drain electrode electrical connection third transistor M3, source
Pole electrically connects the grid of the 5th transistor M5.
It should be noted that the input IN of shift register is used for receiving initial signal, initial signal is pulse signal,
The high value of initial signal is 5 volts to 15 volts, and the low level value of initial signal is -15 volts to -5 volts；Shift register defeated
Go out to hold OUT can be connected with scan line, for providing drive signal for corresponding scan line（Alternatively referred to as trigger）.
Specifically, the capacitance of the first electric capacity C1 can be 0.11 pico farad, and the capacitance of the second electric capacity C2 can be 0.12
Pico farad.Additionally, for the ease of the operation principle analyzing shift register, defining at the grid of the 5th transistor M5 is first segment
Point N1.
Alternatively, the first clock cable CK1 exports the first clock signal, during second clock holding wire CK2 output second
Clock signal, the first clock signal and second clock signal are pulse signal.
Further, the first clock signal and second clock signal inversion signal each other.
Further, the high value of the first clock signal and second clock signal is 5 volts to 15 volts, the first clock letter
Number and the low level value of second clock signal be -15 volts to -5 volts.
Alternatively, the first level signal line VG1 exports the first level signal VGH, second electrical level holding wire VG2 output second
Level signal VGL, the level value of the first level signal VGH is 5 volts to 20 volts, and the level value of second electrical level signal VGL is -20 volts
Arrive -5 volts.
It should be noted that in the present embodiment, the first level signal VGH and second electrical level signal VGL are constant
Level signal is that is to say, that when shift register normal work, give the level of first mono- high level of level signal VGH
Value, given mono- low level level value of second electrical level signal VGL, and the level value of this two level signals all keeps constant
（I.e. constant）.
Further, referring to Fig. 4, the first transistor M1, transistor seconds M2, third transistor M3, the 4th transistor M4,
5th transistor M5 is PMOS, and the 6th transistor M6 is PMOS, now, in order that the 6th transistor M6 conducting, can
So that three level signal VGP is identical with second electrical level signal VGL.So, because the grid of the 5th transistor M5 passes through the 6th
Transistor M6 be connected to third transistor M3 drain electrode so that, when third transistor M3 has leakage current, this leakage current passes through
6th transistor M6 and by the 6th transistor M6 partial pressure so that flowing to the electric current of node N1（It is applied to the electricity of node N1
Buckling is little）, so can prevent leakage current from causing the wave distortion of the output signal of shift register, thus improve display effect
Really, and, due to now, the transistor in shift register, all using PMOS, so, in manufacturing process, can subtract
The quantity of few light shield mask plate, reduces the impact to yield for the technological ability, thus improving production capacity, improves yield, reduces cost.
Alternatively, the 6th transistor M6 can also be NMOS tube, now, in order that the 6th transistor M6 conducting, can make
Three level signal VGP is identical with the first level signal VGH.In the same manner, because the grid of the 5th transistor M5 passes through the 6th crystal
Pipe M6 be connected to third transistor M3 drain electrode so that, when there is leakage current in third transistor M3, this leakage current pass through the 6th
Transistor M6 and by the 6th transistor M6 partial pressure, can prevent leakage current from causing the waveform of the output signal of shift register to lose
Very, thus improve display effect.In addition, in the present embodiment, for the 6th transistor M6 adopt NMOS tube or
PMOS, the operation principle of corresponding shift register is similar, and can produce identical technique effect.Below just with all
Transistor be all PMOS shift register（I.e. shown in Fig. 4）As a example further illustrating its operation principle, but this reality
Apply example and only PMOS is adopted for citing with the 6th transistor M6, and unrestricted.
Fig. 5 is the oscillogram of each signal with regard to the shift register in Fig. 4.As shown in figure 5, when CKV1 represents first
First clock signal of clock holding wire CK1 output；CKV2 represents the second clock signal of second clock holding wire CK2 output；STV
Represent the initial signal of input IN reception；SN1 represents the level signal of primary nodal point N1；SOUT represents the defeated of outfan OUT
Go out signal.
As shown in Figure 4 and Figure 5, while each signal in Figure 5 is applied to shift register, the first level signal
VGH passes through the first level signal line VG1 and applies constant high level signal to shift register, and second electrical level signal VGL passes through
Second electrical level holding wire VG2 applies constant low level signal to shift register, and three level signal VGP is to the 6th transistor
The grid of M6 applies and second electrical level signal VGL identical signal.
Referring to Fig. 4 and Fig. 5, within the T1 time period, the first clock signal CKV1 is low level, and is applied to transistor seconds
M2 and the grid of third transistor M3, make transistor seconds M2 and the conducting of third transistor M3, now, three level signal VGP
Low level make the 6th transistor M6 conducting, the low level of initial signal STV passes sequentially through third transistor M3 and the 6th crystal
Pipe M6 is applied to the grid of the 5th transistor M5, makes the 5th transistor M5 conducting, and the high level of second clock signal CKV2 passes through
5th transistor M5 transmits to outfan OUT；Second electrical level signal VGL（I.e. constant low level signal）By transistor seconds
M2 is applied to the grid of the 4th transistor M4, makes the 4th transistor M4 conducting, and by the current potential at the grid of the 4th transistor M4
It is stored in the first electric capacity C1, and now the current potential at the grid of the 4th transistor M4 is low level, the first level signal VGH
（I.e. constant high level signal）Transmitted to outfan OUT by the 4th transistor M4, therefore, the outfan of shift register
Output signal SOUT of OUT is the high level part of second clock signal CKV2 and the superposition of the first level signal VGH, Yi Jiyi
Output signal SOUT of the outfan OUT of bit register is high level, now, the current potential of level signal SN1 of primary nodal point N1
It is in level c, that is, between high level b and low level d, and the current potential of primary nodal point N1 is stored in the second electric capacity C2.
Within the T2 time period, the first clock signal CKV1 is high level, controls transistor seconds M2 and third transistor M3
Close, the current potential at the grid of the 4th transistor M4 being stored within the T1 time period due to the first electric capacity C1 can make the 4th crystal
Pipe M4 continues conducting, and the high level of the first level signal VGH continues through the 4th transistor M4 and transmits to outfan OUT；Due to
The low level of three level signal VGP makes the 6th transistor M6 continue conducting, and the second electric capacity C2 stored within the T1 time period
The current potential of primary nodal point N1 makes the 5th transistor M5 continue conducting, and the high level of second clock signal CKV2 continues through the 5th
Transistor M5 transmits to outfan OUT, therefore, within the T2 time period, output signal SOUT of outfan OUT and primary nodal point N1
The waveform of level signal SN1 identical with the T1 time period, that is, output signal SOUT be high level, primary nodal point N1 level letter
The current potential of number SN1 is still in level c i.e. between high level b and low level d, and is stored in first within the T2 time period
The current potential of the current potential at the grid of the 4th transistor M4 in electric capacity C1 and the primary nodal point N1 being stored in the second electric capacity C2 does not have
Change.
Within the T3 time period, the first clock signal CKV1 is high level, controls transistor seconds M2 and third transistor M3
Close, because the low level of three level signal VGP makes the 6th transistor M6 continue conducting, the second electric capacity C2 is in the T2 time period
The current potential of the primary nodal point N1 of interior storage makes the 5th transistor M5 continue conducting, and the low level of second clock signal CKV2 is passed through
5th transistor M5 is applied to the grid of the first transistor M1 so that the first transistor M1 turns on, the height of the first level signal VGH
Level is applied to the grid of the 4th transistor M4 by the first transistor M1, and controls the 4th transistor M4 to close, and concurrently disinfects
It is stored in the current potential at the grid of the 4th transistor M4 in the first electric capacity C1, therefore, the now output signal of outfan OUT
SOUT is only second clock signal CKV2, as low level, and now, the current potential of primary nodal point N1 is entered one by original level c
Step is pulled low to level d, is also still in low level level, and the current potential of primary nodal point N1 within the T3 time period is stored in the
In two electric capacity C2.
Within the T4 time period, the first clock signal CKV1 is high level, controls transistor seconds M2 and third transistor M3
Close, due at the grid of the 4th transistor M4 that within the T3 time period, is stored in the T2 time period in the first electric capacity C1
Current potential is eliminated（I.e. electronegative potential is eliminated）, therefore, the 4th transistor M4 is also switched off；Low electricity due to three level signal VGP
Flat make the 6th transistor M6 continue conducting, the current potential of the primary nodal point N1 that the second electric capacity C2 stored within the T3 time period makes the
Five transistor M5 continue conducting, and the high level of second clock signal CKV2 is transmitted to outfan OUT by the 5th transistor M5, defeated
Go out to hold output signal SOUT of OUT to be changed into high level, now, the current potential of primary nodal point N1 is driven high, with the T1 time period in and T2
Waveform in time period is identical, and the current potential of primary nodal point N1 is in level c i.e. between high level b and low level d, and will be
In the T4 time period, the current potential of primary nodal point N1 is stored in the second electric capacity C2.
Can be obtained by Fig. 5 and foregoing description, the low level signal of initial signal STV is through the first clock signal CKV1
Or just export low level output signal SOUT from outfan OUT after the half period duration of second clock signal CKV2, also
It is to say, output signal SOUT of outfan OUT first clock CKV1 or second clock signal more delayed than initial signal STV
The half period duration of CKV2, it is achieved thereby that the function of displacement.
Fig. 6 is the electricity that the shift register in Fig. 4 is 10 volts and second electrical level signal when the level value of the first level signal
When level values are -5 volt, the oscillogram of the output signal of outfan OUT.Compared with Fig. 3, the output of the shift register shown in Fig. 6
The waveform of the output signal of end OUT is normal, and this shows that the shift register of the present invention can prevent the output being caused by leakage current
The wave distortion of signal.Fig. 6 is the result obtained by the 6th transistor M6 adopts PMOS, when the 6th transistor M6 adopts NMOS
Guan Shi, also can obtain same result, will not be described here.
It should be noted that referring in the present embodiment that sectional pressure element is that the 6th transistor is only for example, and unrestricted,
It is true that sectional pressure element can also be multiple 6th transistors, and those multiple 6th transistors are all applied in the 3rd level letter
Number and turn on, the embodiment of the present invention is not limited to the quantity of the 6th transistor, and sectional pressure element only need to meet including at least
One the 6th transistor, and those at least one the 6th transistors are all applied in three level signal and turn on；Or, point
Pressure element can also be the diode of conducting, and diode can be equivalent diode, usual equivalent diode can by grid and
Source electrode（Or drain electrode）The audion of short circuit is formed.
Embodiment two
The embodiment of the present invention two provides a kind of gate driver circuit, and this gate driver circuit includes the shifting that n level is connected step by step
Bit register, and n is positive integer.Wherein said shift register adopts the shift register described in above-described embodiment one.
Fig. 7 is a kind of structured flowchart of gate driver circuit of the embodiment of the present invention two.Referring to Fig. 7, gate driver circuit
The shift register (SR1-SRn) connected step by step including n level, wherein, n is positive integer；Specifically, the 1st grade of shift register SR1
Input IN1 receive initial signal, the input IN10 of the 10th grade of shift register SR10 electrically connects the 9th grade of shift register
The outfan OUT9 of SR9, it should be noted that the input IN10 of the 10th grade of shift register SR10 in the present embodiment is electrically connected
Meet the outfan OUT9 of the 9th grade of shift register SR9, this is only for example, and non-limiting, in real work, only need to meet with
Lower condition：The input INm of m level shift register SRm electrically connects the defeated of described m-1 level shift register SR m-1
Go out and hold OUTm-1, wherein, m be more than or equal to 2 and less than or equal to n positive integer.In Fig. 7, OUT1 represents the 1st grade of shift register
Outfan, INn and OUTn represent input and the outfan of n-th grade of shift register respectively.Shiftings at different levels in the present embodiment
Bit register adopts the shift register described in above-described embodiment one.
It should be noted that the initial signal that the input IN1 of the 1st grade of shift register receives is pulse signal, initiate
The high value of signal is 5 volts to 15 volts, and the low level value of initial signal is -15 volts to -5 volts.Additionally, above-mentioned every grade of displacement is posted
The outfan of storage can be connected with the scan line of corresponding line, thus providing drive signal for the scan line of corresponding line.
Furthermore it is possible to carry out to the gate driver circuit of the shift register comprising described in above-described embodiment one according to demand
Control with realize just sweeping or counter sweep, the present embodiment is without limitation.
Embodiment three
The embodiment of the present invention three provides a kind of tft array substrate, and this tft array substrate includes gate driver circuit.Wherein,
Described gate driver circuit adopts the gate driver circuit described in above-described embodiment two.It should be noted that in tft array substrate
TFT be not limited to A-Si（Non-crystalline silicon）Type, LTPS（Low Temperature Poly-silicon, low temperature polycrystalline silicon）Type or
Oxide type it is preferable that the TFT in tft array substrate can adopt LTPS type, due to the material behavior of LTPS, lead by its electronics
Electric rate is higher, can improve the performance of tft array substrate further, thus improving display effect.
Monolateral driving can be realized to the scan line on tft array substrate by above-mentioned gate driver circuit it is also possible to reality
Existing bilateral driving.Fig. 8 a is the structural representation of the tft array substrate of monolateral driving of the embodiment of the present invention three.Referring to Fig. 8 a,
Tft array substrate 10 includes scan line 12 and the gate driver circuit 11 being located at scan line 12 one end by rows（In Fig. 8 a
Gate driver circuit is located at the left end of scan line, and in other embodiments, gate driver circuit can also be located at scan line
Right-hand member）, the outfan of each horizontal scanning line 12 and corresponding shift register in gate driver circuit 11（In figure is not shown）Electricity
Connect, realizing gate driver circuit 11 provides drive signal for each horizontal scanning line 12.Above-mentioned type of drive is monolateral driving.
Fig. 8 b is the structural representation of the tft array substrate of bilateral driving of the embodiment of the present invention three.Referring to Fig. 8 b, TFT
Array base palte 10 includes scan line 12 by rows and is located at scan line 12 two ends（In figure is left end and right-hand member）Grid drive
Galvanic electricity road 11, the outfan of each horizontal scanning line 12 and corresponding shift register in the gate driver circuit 11 at two ends（In figure
Not shown）Electrical connection, the gate driver circuit 11 realizing two ends provides drive signal for the scan line 12 of corresponding line simultaneously.Above-mentioned
Type of drive is bilateral driving.
Example IV
The embodiment of the present invention four provides a kind of display floater（Not shown）, this display floater includes tft array substrate.Its
In, described tft array substrate adopts the tft array substrate described in above-described embodiment three.Generally, display floater can also include with
The color membrane substrates that tft array substrate is oppositely arranged, display floater can also include liquid crystal layer, positioned at tft array substrate and color film
Between substrate.
Embodiment five
The embodiment of the present invention five provides a kind of display device（Not shown）, this display device includes display floater.Wherein, institute
State display floater and adopt the display floater described in above-described embodiment four.It should be noted that display device according to the present invention is not
It is limited to LCD（Liquid Crystal Display, liquid crystal display）、OLED（Organic Light-Emitting Diode,
Organic light-emitting diode display）With Electronic Paper etc..
To sum up, shift register provided in an embodiment of the present invention, gate driver circuit, tft array substrate, display floater with
And in display device, the grid of the 5th transistor is electrically connected to the drain electrode of described third transistor by sectional pressure element.The present invention
Embodiment is at least up to one of following effect：The shift register of the present invention can prevent the output signal being caused by leakage current
Wave distortion, thus improving the display quality of display device, reduce light shield mask plate quantity, reduce technological ability to yield
Impact, thus improving production capacity, reduces cost.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious changes,
Readjust and substitute without departing from protection scope of the present invention.Therefore although being carried out to the present invention by above example
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
Other Equivalent embodiments more can be included, and the scope of the present invention is determined by scope of the appended claims.
Claims (11)
1. a kind of shift register, including：The first transistor, transistor seconds, third transistor, the 4th transistor, the 5th crystalline substance
Body pipe, sectional pressure element, the first electric capacity and the second electric capacity；
The grid electrical connection outfan of described the first transistor, drain electrode electrical connection the first level signal line, source electrode is electrically connected
The drain electrode of described transistor seconds and the grid of described 4th transistor；
The grid of described transistor seconds electrically connects the first clock cable, and source electrode electrically connects second electrical level holding wire；
The grid of described third transistor electrically connects described first clock cable, and source electrode electrically connects input, and institute is passed through in drain electrode
State the second electric capacity and electrically connect described outfan；
The drain electrode of described 4th transistor electrically connects described first level signal line, and source electrode electrically connects described outfan, and grid leads to
Cross described first electric capacity and electrically connect described first level signal line；
The drain electrode of described 5th transistor electrically connects described outfan, and source electrode electrically connects second clock holding wire, and grid passes through institute
State the drain electrode that sectional pressure element is electrically connected to described third transistor, wherein, when described shift register normal work, described point
Pressure element conductive.
2. shift register according to claim 1 is it is characterised in that described first clock cable exports the first clock
Signal, described second clock holding wire exports second clock signal, and described first clock signal and second clock signal are arteries and veins
Rush signal.
3. shift register according to claim 2 is it is characterised in that described first clock signal and second clock signal
Inversion signal each other.
4. shift register according to claim 3 is it is characterised in that described first clock signal and second clock signal
High value be 5 volts to 15 volts, the low level value of described first clock signal and second clock signal is -15 volts to -5
Volt.
5. the shift register according to any one of claim 1-4 is it is characterised in that described first level signal line is defeated
Go out the first level signal, described second electrical level holding wire exports second electrical level signal, and the level value of described first level signal is 5
Lie prostrate 20 volts, the level value of described second electrical level signal is -20 volts to -5 volts.
6. shift register according to claim 5 is it is characterised in that described sectional pressure element is the 6th transistor, described
The grid of the 6th transistor is applied in a three level signal, and drain electrode electrically connects the drain electrode of described third transistor, and source electrode is electrically connected
Connect the grid of described 5th transistor；
Or, described sectional pressure element is the diode of conducting.
7. shift register according to claim 6 it is characterised in that described the first transistor, transistor seconds, the 3rd
Transistor, the 4th transistor, the 5th transistor are PMOS, wherein,
Described 6th transistor is PMOS, and described three level signal is identical with described second electrical level signal；Or, described
Six transistors are NMOS tube, and described three level signal is identical with described first level signal.
8. a kind of gate driver circuit, the shift LD as any one of claim 1-7 connected step by step including n level
Device, wherein, n is positive integer；
The input of the 1st grade of shift register receives initial signal, and the input of m level shift register electrically connects described m-
The outfan of 1 grade of shift register, wherein, m be more than or equal to 2 and less than or equal to n positive integer.
9. a kind of tft array substrate, including gate driver circuit as claimed in claim 8.
10. a kind of display floater, including tft array substrate as claimed in claim 9.
A kind of 11. display devices, including display floater as claimed in claim 10.
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| CN104795106B (en) * | 2015-04-14 | 2019-04-05 | 上海天马有机发光显示技术有限公司 | Shift register and driving method, driving circuit, array substrate and display device |
| CN108039150B (en) | 2017-11-16 | 2020-05-19 | 武汉华星光电半导体显示技术有限公司 | Shift register circuit and shift register unit |
| CN107978278B (en) * | 2018-01-19 | 2019-12-24 | 昆山国显光电有限公司 | Scanning circuit, organic light emitting display device and driving method thereof |
| CN108776797A (en) * | 2018-07-03 | 2018-11-09 | 京东方科技集团股份有限公司 | A kind of fingerprint recognition circuit and its driving method, display device |
| CN113035109B (en) * | 2021-02-25 | 2024-05-17 | 福建华佳彩有限公司 | GIP driving circuit of embedded display screen and control method thereof |
| CN113052095B (en) * | 2021-03-30 | 2022-11-15 | 厦门天马微电子有限公司 | Display panel and display device |
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| CN102479552A (en) * | 2010-11-25 | 2012-05-30 | 上海天马微电子有限公司 | PMOS dynamic shift register unit and dynamic shift register |
| CN103295641A (en) * | 2012-06-29 | 2013-09-11 | 上海天马微电子有限公司 | Shift register and drive method thereof |
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| JP5719103B2 (en) * | 2009-06-26 | 2015-05-13 | 株式会社ジャパンディスプレイ | Display device |
| KR101389120B1 (en) * | 2010-03-02 | 2014-04-25 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Pulse signal output circuit and shift register |
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| CN102479552A (en) * | 2010-11-25 | 2012-05-30 | 上海天马微电子有限公司 | PMOS dynamic shift register unit and dynamic shift register |
| CN103295641A (en) * | 2012-06-29 | 2013-09-11 | 上海天马微电子有限公司 | Shift register and drive method thereof |
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