CN113035109B - GIP driving circuit of embedded display screen and control method thereof - Google Patents

GIP driving circuit of embedded display screen and control method thereof Download PDF

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Publication number
CN113035109B
CN113035109B CN202110212006.5A CN202110212006A CN113035109B CN 113035109 B CN113035109 B CN 113035109B CN 202110212006 A CN202110212006 A CN 202110212006A CN 113035109 B CN113035109 B CN 113035109B
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transistor
gate
drain
electrode
source
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CN113035109A (en
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谢建峰
熊克
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Fujian Huajiacai Co Ltd
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Fujian Huajiacai Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

The invention relates to the technical field of GIP driving circuits, in particular to a GIP driving circuit of an embedded display screen and a control method thereof, wherein the GIP driving circuit comprises a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a transistor T10, a transistor T11, a transistor T12, a transistor T13, a transistor T14, a transistor T15, a transistor T16, a transistor T17, a transistor T18, a transistor T19, a transistor T20, a transistor T21 and a capacitor C1, wherein the source electrode of the transistor T1 is respectively and electrically connected with the grid electrode of the transistor T2, the drain electrode of the transistor T3, the drain electrode of the transistor T7, the grid electrode of the transistor T21, the drain electrode of the transistor T9, the drain electrode of the transistor T18, the grid electrode of the transistor T4 and one end of the capacitor C1, so that the display quality of the display screen can be improved.

Description

GIP driving circuit of embedded display screen and control method thereof
Technical Field
The invention relates to the technical field of GIP (gate-in-plane) driving circuits, in particular to a GIP driving circuit of an embedded display screen and a control method thereof.
Background
The output waveform of the GIP (i.e., GATE IN PANEL) driving circuit of the display screen is influenced by the leakage of the TFT, so that the output waveform of the GIP is distorted, and the distortion of the GIP waveform causes problems of the on and off of the TFT in the display area of the display screen, so that abnormal display of the display screen is caused.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: the GIP driving circuit and the control method thereof for the embedded display screen are provided, so that the output waveform of the GIP is not distorted, and the display effect of the display screen is not distorted.
In order to solve the technical problems, the first technical scheme adopted by the invention is as follows:
A GIP driving circuit of an embedded display screen comprises a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a transistor T10, a transistor T11, a transistor T12, a transistor T13, a transistor T14, a transistor T15, a transistor T16, a transistor T17, a transistor T18, a transistor T19, a transistor T20, a transistor T21 and a capacitor C1, wherein the grid electrode of the transistor T1 is electrically connected with the grid electrode of the transistor T13, the grid electrode of the transistor T1 and the grid electrode of the transistor T13 are connected with a first grid electrode wiring, the drain electrode of the transistor T1 is respectively connected with the source electrode of the transistor T13, the source electrode of the transistor T14, the drain electrode of the transistor T7, the source electrode of the transistor T17, the drain electrode of the transistor T18, the source electrode of the transistor T3, the drain electrode of the transistor T15, the drain electrode of the transistor T21, the drain electrode of the transistor T16 and the source electrode of the transistor T9, the source of the transistor T1 is electrically connected with the gate of the transistor T2, the drain of the transistor T3, the drain of the transistor T7, the gate of the transistor T21, the drain of the transistor T9, the drain of the transistor T18, the gate of the transistor T4 and one end of the capacitor C1, the gate of the transistor T3 is electrically connected with the drain of the transistor T2, the gate of the transistor T15, the gate of the transistor T12, the drain of the transistor T8 and the gate of the transistor T6, the source of the transistor T2 is electrically connected with the source of the transistor T15, the source of the transistor T12, the source of the transistor T8, the source of the transistor T16, the source of the transistor T10 and the source of the transistor T6, the source of the transistor T21 is electrically connected with the source of the transistor T19 and the drain of the transistor T20, and the gate of the transistor T8 is electrically connected with the gate of the transistor T9, the grid electrode of the transistor T16 and the grid electrode of the transistor T10 are electrically connected, the drain electrode of the transistor T10 is electrically connected with the drain electrode of the transistor T6, the other end of the capacitor C1, the source electrode of the transistor T4 and the source electrode of the transistor T5 respectively, the drain electrode of the transistor T10, the drain electrode of the transistor T6, the other end of the capacitor C1, the source electrode of the transistor T4 and the source electrode of the transistor T5 are all connected with the second grid electrode wiring, the grid electrode of the transistor T14 is electrically connected with the grid electrode of the transistor T7, and the grid electrode of the transistor T14 and the grid electrode of the transistor T7 are all connected with the third grid electrode wiring.
The second technical scheme adopted by the invention is as follows:
A control method of a GIP drive circuit of an embedded display screen comprises the following steps:
s1, at a first moment, a high level is input to a gate of a control transistor T1 and a gate of a control transistor T13;
s2, at a second moment, the drain electrode of the control transistor T4 inputs a high level;
And S3, at a third moment, the high level is input to the gate of the control transistor T7 and the gate of the transistor T14.
The invention has the beneficial effects that:
By electrically connecting the gate of the transistor T1 with the gate of the transistor T13, the gate of the transistor T1 and the gate of the transistor T13 are both connected to the first gate trace, the source of the transistor T1 is electrically connected to the gate of the transistor T2, the drain of the transistor T3, the drain of the transistor T7, the gate of the transistor T21, the drain of the transistor T9, the drain of the transistor T18, the gate of the transistor T4 and one end of the capacitor C1, the drain of the transistor T10 is electrically connected to the drain of the transistor T6, the other end of the capacitor C1, the source of the transistor T4 and the source of the transistor T5, respectively, and the drain of the transistor T6, the other end of the capacitor C1, the source of the transistor T4 and the source of the transistor T5 are both connected to the second gate trace, and the gate of the transistor T14 and the gate of the transistor T14 are both connected to the third gate trace, so that the Q-point of the GIP driving circuit (i.e., the drain of the transistor T1, the source of the transistor T7, the drain of the transistor 1 and the drain of the transistor 1 are improved, the drain of the transistor 1 are all the display is improved, and the display is no current is reduced, and the display is no current is generated.
Drawings
FIG. 1 is a schematic diagram showing a GIP driving circuit of an embedded display according to the invention;
FIG. 2 is a schematic diagram showing a structure of a GIP driving circuit of an in-cell display according to the present invention;
FIG. 3 is a schematic diagram showing a structure of a GIP driving circuit of an in-cell display according to the present invention;
FIG. 4 is a schematic diagram showing a structure of a GIP driving circuit of an in-cell display according to the present invention;
FIG. 5 is a schematic diagram showing a structure of a GIP driving circuit of an in-cell display according to the present invention;
FIG. 6 is a schematic diagram showing a structure of a GIP driving circuit of an in-cell display according to the present invention;
FIG. 7 is a schematic diagram showing a structure of a GIP driving circuit of an in-cell display according to the present invention;
FIG. 8 is a timing waveform diagram of a GIP driving circuit of an in-cell display according to the invention;
FIG. 9 is a timing diagram of a GIP driving circuit of an in-cell display according to the invention;
FIG. 10 is a timing diagram of a GIP driving circuit of an in-cell display according to the invention;
FIG. 11 is a timing waveform diagram of a GIP driving circuit of an in-cell display according to the invention;
FIG. 12 is a flowchart showing steps of a method for controlling a GIP driving circuit of an in-cell display according to the present invention.
Detailed Description
In order to describe the technical contents, the achieved objects and effects of the present invention in detail, the following description will be made with reference to the embodiments in conjunction with the accompanying drawings.
Referring to fig. 1, the present invention provides a technical solution:
A GIP driving circuit of an embedded display screen comprises a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a transistor T10, a transistor T11, a transistor T12, a transistor T13, a transistor T14, a transistor T15, a transistor T16, a transistor T17, a transistor T18, a transistor T19, a transistor T20, a transistor T21 and a capacitor C1, wherein the grid electrode of the transistor T1 is electrically connected with the grid electrode of the transistor T13, the grid electrode of the transistor T1 and the grid electrode of the transistor T13 are connected with a first grid electrode wiring, the drain electrode of the transistor T1 is respectively connected with the source electrode of the transistor T13, the source electrode of the transistor T14, the drain electrode of the transistor T7, the source electrode of the transistor T17, the drain electrode of the transistor T18, the source electrode of the transistor T3, the drain electrode of the transistor T15, the drain electrode of the transistor T21, the drain electrode of the transistor T16 and the source electrode of the transistor T9, the source of the transistor T1 is electrically connected with the gate of the transistor T2, the drain of the transistor T3, the drain of the transistor T7, the gate of the transistor T21, the drain of the transistor T9, the drain of the transistor T18, the gate of the transistor T4 and one end of the capacitor C1, the gate of the transistor T3 is electrically connected with the drain of the transistor T2, the gate of the transistor T15, the gate of the transistor T12, the drain of the transistor T8 and the gate of the transistor T6, the source of the transistor T2 is electrically connected with the source of the transistor T15, the source of the transistor T12, the source of the transistor T8, the source of the transistor T16, the source of the transistor T10 and the source of the transistor T6, the source of the transistor T21 is electrically connected with the source of the transistor T19 and the drain of the transistor T20, and the gate of the transistor T8 is electrically connected with the gate of the transistor T9, the grid electrode of the transistor T16 and the grid electrode of the transistor T10 are electrically connected, the drain electrode of the transistor T10 is electrically connected with the drain electrode of the transistor T6, the other end of the capacitor C1, the source electrode of the transistor T4 and the source electrode of the transistor T5 respectively, the drain electrode of the transistor T10, the drain electrode of the transistor T6, the other end of the capacitor C1, the source electrode of the transistor T4 and the source electrode of the transistor T5 are all connected with the second grid electrode wiring, the grid electrode of the transistor T14 is electrically connected with the grid electrode of the transistor T7, and the grid electrode of the transistor T14 and the grid electrode of the transistor T7 are all connected with the third grid electrode wiring.
From the above description, the beneficial effects of the invention are as follows:
By electrically connecting the gate of the transistor T1 with the gate of the transistor T13, the gate of the transistor T1 and the gate of the transistor T13 are both connected to the first gate trace, the source of the transistor T1 is electrically connected to the gate of the transistor T2, the drain of the transistor T3, the drain of the transistor T7, the gate of the transistor T21, the drain of the transistor T9, the drain of the transistor T18, the gate of the transistor T4 and one end of the capacitor C1, the drain of the transistor T10 is electrically connected to the drain of the transistor T6, the other end of the capacitor C1, the source of the transistor T4 and the source of the transistor T5, respectively, and the drain of the transistor T6, the other end of the capacitor C1, the source of the transistor T4 and the source of the transistor T5 are both connected to the second gate trace, and the gate of the transistor T14 and the gate of the transistor T14 are both connected to the third gate trace, so that the Q-point of the GIP driving circuit (i.e., the drain of the transistor T1, the source of the transistor T7, the drain of the transistor 1 and the drain of the transistor 1 are improved, the drain of the transistor 1 are all the display is improved, and the display is no current is reduced, and the display is no current is generated.
Further, the drain of the transistor T4 is connected to a clock signal.
Further, the gate of the transistor T11 is electrically connected to the drain of the transistor T11, the gate of the transistor T11 and the drain of the transistor T11 are both connected to the first voltage, the gate of the transistor T12 is connected to the second voltage, the gate of the transistor T19 is electrically connected to the drain of the transistor T19, the gate of the transistor T19 and the drain of the transistor T19 are both connected to the first voltage, the gate of the transistor T20 is electrically connected to the drain of the transistor T20, and the gate of the transistor T20 and the drain of the transistor T20 are both connected to the second voltage.
Further, the drain electrode of the transistor T17 is connected to the negative electrode of the power supply, and the source electrode of the transistor T2, the source electrode of the transistor T15, the source electrode of the transistor T12, the source electrode of the transistor T8, the source electrode of the transistor T16, the source electrode of the transistor T10 and the source electrode of the transistor T6 are all connected to the positive electrode of the power supply.
Further, the transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, and T21 are all N-channel MOS transistors.
From the above description, the output waveform of the GIP driving circuit can be further stabilized by the N-channel MOS transistor, so that the cost for improving the GIP process is saved, and the display effect of the display screen is optimized.
Referring to fig. 12, another technical solution provided by the present invention is as follows:
A control method of a GIP drive circuit of an embedded display screen comprises the following steps:
s1, at a first moment, a high level is input to a gate of a control transistor T1 and a gate of a control transistor T13;
s2, at a second moment, the drain electrode of the control transistor T4 inputs a high level;
And S3, at a third moment, the high level is input to the gate of the control transistor T7 and the gate of the transistor T14.
From the above description, the beneficial effects of the invention are as follows:
By electrically connecting the gate of the transistor T1 with the gate of the transistor T13, the gate of the transistor T1 and the gate of the transistor T13 are both connected to the first gate trace, the source of the transistor T1 is electrically connected to the gate of the transistor T2, the drain of the transistor T3, the drain of the transistor T7, the gate of the transistor T21, the drain of the transistor T9, the drain of the transistor T18, the gate of the transistor T4 and one end of the capacitor C1, the drain of the transistor T10 is electrically connected to the drain of the transistor T6, the other end of the capacitor C1, the source of the transistor T4 and the source of the transistor T5, respectively, and the drain of the transistor T6, the other end of the capacitor C1, the source of the transistor T4 and the source of the transistor T5 are both connected to the second gate trace, and the gate of the transistor T14 and the gate of the transistor T14 are both connected to the third gate trace, so that the Q-point of the GIP driving circuit (i.e., the drain of the transistor T1, the source of the transistor T7, the drain of the transistor 1 and the drain of the transistor 1 are improved, the drain of the transistor 1 are all the display is improved, and the display is no current is reduced, and the display is no current is generated.
Further, the step S1 further includes the following steps:
the drain of the control transistor T4 inputs a low level.
Further, the step S3 further includes the following steps:
The gate of the control transistor T11 inputs a high level.
Referring to fig. 1 to 11, a first embodiment of the present invention is as follows:
Referring to fig. 1, a GIP driving circuit of an embedded display includes a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a transistor T10, a transistor T11, a transistor T12, a transistor T13, a transistor T14, a transistor T15, a transistor T16, a transistor T17, a transistor T18, a transistor T19, a transistor T20, a transistor T21, and a capacitor C1, wherein a gate of the transistor T1 is electrically connected to a gate of the transistor T13, and a gate of the transistor T1 and a gate of the transistor T13 are both connected to a first gate trace, a drain of the transistor T1 is respectively connected to a source of the transistor T13, a source of the transistor T14, a drain of the transistor T7, a source of the transistor T17, a drain of the transistor T18, a source of the transistor T3, a drain of the transistor T15, a drain of the transistor T21, a drain of the transistor T16, and a source of the transistor T9, the source of the transistor T1 is electrically connected with the gate of the transistor T2, the drain of the transistor T3, the drain of the transistor T7, the gate of the transistor T21, the drain of the transistor T9, the drain of the transistor T18, the gate of the transistor T4 and one end of the capacitor C1, the gate of the transistor T3 is electrically connected with the drain of the transistor T2, the gate of the transistor T15, the gate of the transistor T12, the drain of the transistor T8 and the gate of the transistor T6, the source of the transistor T2 is electrically connected with the source of the transistor T15, the source of the transistor T12, the source of the transistor T8, the source of the transistor T16, the source of the transistor T10 and the source of the transistor T6, the source of the transistor T21 is electrically connected with the source of the transistor T19 and the drain of the transistor T20, and the gate of the transistor T8 is electrically connected with the gate of the transistor T9, the grid electrode of the transistor T16 and the grid electrode of the transistor T10 are electrically connected, the drain electrode of the transistor T10 is electrically connected with the drain electrode of the transistor T6, the other end of the capacitor C1, the source electrode of the transistor T4 and the source electrode of the transistor T5 respectively, the drain electrode of the transistor T10, the drain electrode of the transistor T6, the other end of the capacitor C1, the source electrode of the transistor T4 and the source electrode of the transistor T5 are all connected with the second grid electrode wiring, the grid electrode of the transistor T14 is electrically connected with the grid electrode of the transistor T7, and the grid electrode of the transistor T14 and the grid electrode of the transistor T7 are all connected with the third grid electrode wiring.
The drain of the transistor T4 is connected to a clock signal.
The gate of the transistor T11 is electrically connected with the drain of the transistor T11, the gate of the transistor T11 and the drain of the transistor T11 are both connected with the first voltage, the gate of the transistor T12 is connected with the second voltage, the gate of the transistor T19 is electrically connected with the drain of the transistor T19, the gate of the transistor T19 and the drain of the transistor T19 are both connected with the first voltage, the gate of the transistor T20 is electrically connected with the drain of the transistor T20, and the gate of the transistor T20 and the drain of the transistor T20 are both connected with the second voltage.
The drain electrode of the transistor T17 is connected to the negative electrode of the power supply, and the source electrode of the transistor T2, the source electrode of the transistor T15, the source electrode of the transistor T12, the source electrode of the transistor T8, the source electrode of the transistor T16, the source electrode of the transistor T10 and the source electrode of the transistor T6 are all connected to the positive electrode of the power supply.
The transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, and T21 are all N-channel MOS transistors.
In this scheme, each stage of GIP circuit has 21 TFTs, 1 capacitor C1, FW is dc high voltage, 15V is set, bw and VGL are dc low voltage, and-10V is set. For the Q point, the TFTs that pull up the voltage have the transistors T1, T4, and T13, and the TFTs that pull down the voltage have the transistors T3, T9, T15, and T16. According to the scheme, the voltage of the QB node is controlled, so that the transistor T3 and the transistor T9 do not generate electric leakage, a leakage path is not generated at the point Q, electric leakage is not generated at the point Q, and the waveform of G (n) cannot be distorted.
The 21T1C circuit is exemplified by the circuit connection relationship of the scheme, in the scheme, the GIP of a single side of 4 STVs (the starting voltage waveforms of the GIP actions) is taken as an example, STV1 is used as the starting voltages of G1 and G3, and STV3 is used as the starting voltages of G5 and G7.
Referring to fig. 2, when n=1, the GIP output waveform is the first Gate Line waveform, denoted as G [1]. P3 is the P-point voltage of the GIP circuit when n=3, i.e., the gates of the transistors T5, T17, T18 in the GIP circuit of G1 are connected to P3 of G3. The signal connected to the gate of the transistor T12 is V2, and the signal connected to the gate of the transistor T11 is V1.
Referring to fig. 3, when n=3, the GIP output waveform is the third Gate Line waveform, denoted as G [3]. P1 is the P-point voltage of the GIP circuit when n=1, i.e., the gates of the transistors T5, T17, T18 in the GIP circuit of G3 are connected to P1 of G1. The signal connected to the gate of the transistor T12 is V1, and the signal connected to the gate of the transistor T11 is V2.
Referring to fig. 4, when n=5, the GIP output waveform is the fifth Gate Line waveform, denoted as G [5]. P3 is the P-point voltage of the GIP circuit when n=3, i.e., the gates of the transistors T5, T17, T18 in the GIP circuit of G5 are connected to P3 of G3. The signal connected to the gate of the transistor T12 is V2, and the signal connected to the gate of the transistor T11 is V1.
Referring to fig. 5, when n=7, the GIP output waveform is a seventh Gate Line waveform, denoted as G [7]. P5 is the P-point voltage of the GIP circuit when n=5, i.e., the gates of the transistors T5, T17, T18 in the GIP circuit of G7 are connected to P5 of G5. The signal connected to the gate of the transistor T12 is V1, and the signal connected to the gate of the transistor T11 is V2.
In summary, the signals given by the transistors T12 with odd numbers GIP on one side and the gate signals of the transistors T11 are different, and herein, it can be simply understood that the odd-side GIP circuit is divided into odd-numbered and even-numbered stages GIP, which corresponds to the odd-numbered stage G1, the signal connected to the gate of the transistor T12 is V2, and the signal connected to the gate of the transistor T11 is V1. G3 is an even number stage, the signal to which the gate of transistor T12 is connected is V1, and the gate of transistor T11 is connected is a V2 signal. G5 is an odd number of stages, the signal to which the gate of transistor T12 is connected is V2, and the gate of transistor T11 is connected is the V1 signal. G7 is an even number stage, the signal to which the gate of transistor T12 is connected is V1, and the gate of transistor T11 is connected is a V2 signal. The corresponding V1, V2 signals are sequentially and repeatedly transmitted to the gates of the transistors T12 and T11.
Referring to fig. 6, when n=4i+5 (i≡1), the gate connection relationship of the transistors T5, T17 and T18 of GIP starts from stage 9. The P point of G7, P7 is connected with the gates of transistors T5, T17 and T18 of G9, the P point of G11, P11 is connected with the gates of transistors T5, T17 and T18 of G13, and the principle of connecting P point of G n-2, P n-2 with the gates of transistors T5, T17 and T18 in the GIP circuit of G n is circulated downwards. It should be noted here that when n=4i+5 (i+.1), the signal of the gate connection of the transistor T12 in all GIP circuits is V2 and the gate connection of the transistor T11 is V1 signal.
Referring to fig. 7, when n=4i+7 (i≡1), the gate connection relationship of the transistors T5, T17 and T18 of GIP starts from the 11 th stage. The connection of this circuit is the same as in fig. 1, but it should be noted that the signal connected to the gate of the transistor T12 is V1 and the signal connected to the gate of the transistor T11 is V2.
The driving process of the first frame GIP is described below (please analyze in conjunction with fig. 8 and 9):
In fig. 8, in the first frame, V1 is a high voltage, v1=h, and V2 is a low voltage, v2=l. When n=4i+1, i is equal to or greater than 0, reference is made to the GIP circuit diagram of fig. 7, in which the signals connected to the gates of the transistors T12 in all GIP circuits are V2 and the signals connected to the gates of the transistors T11 are V1.
In the GIP circuit diagram of fig. 6, reference is made to the timing chart of fig. 8 (n=4i+1, i+.0). At time T1, vg [ n-8] (i.e., G (n-8)) is at a high potential, and transistors T1, T13, T2, T4, T21 are turned on, and the Q point is charged to FW high potential, where CK (n) is at a low potential state and G [ n ] outputs a low potential. The QB node is charged to a high potential (less than FW) and the P [ n ] node is pulled to a potential VGL state by VGL due to the turn-on of transistor T2. V1 is always high for one frame, T11 is on, but since transistor T2 is more capable of pulling than transistor T11, pn is still pulled to low VGL by transistor T2. V2 is always low for one frame, and the transistor T12 is always in an off state.
At time T2, CK (n) is high, Q [ n ] is high, transistor T4 is kept in an on state, CK (n) transfers voltage to G [ n ] through transistor T4, G [ n ] changes from low to high, and meanwhile, due to capacitive coupling effect of capacitor C1, the potential at the point Q is changed from FW to FW+FW, so that transistor T4 is turned on better. Also, since the Q [ n ] node potential is at this point highest, transistor T21 is turned on best, and QB [ n ] node is charged to FW level.
At time T2, the transistors T3 and T9 are turned off, the Gate voltages of the transistors T3 and T9 are low VGL, and at this time, since the potential of the QB [ n ] node is FW, vgs=vgl-fw= -25V of the transistors T3 and T9, and as is known from the characteristic curve Vgs-Ids of the TFT, ids is particularly small and negligible at vgs= -25V voltage, and the Q point has no leakage path.
At time T3, vg [ n+8] (i.e., G (n+8)) is high, transistor T14, transistor T7 are turned on, the Qn and QB [ n ] node voltages are pulled to BW low voltage level, and transistor T2, transistor T4, transistor T21 are turned off. At this time, since the transistor T2 is turned off, V1 is always in a high potential state, the transistor T11 is also always in an on state, and P [ n ] is charged to a high potential at this time. P [ n ] charges to a high potential, transistor T6 turns on, and transistor T6 pulls G [ n ] to a low potential state.
When n=4i+3, i+.0, reference is made to the GIP circuit of fig. 7, where the signals connected to the gates of the transistors T12 in all GIP circuits are V1 and the signals connected to the gates of the transistors T11 are V2. Since V1 is connected to T12 at this time, transistor T12 is always on, transistor T11 is always off, and the P [ n ] voltage is always pulled to VGL by transistors T2 and T12. At this time, the Qn is reliable P n-2 to pull the voltage to VGL potential, and the charge of the Qn node is discharged.
The driving process of the second frame GIP is described below (please analyze in conjunction with fig. 10 and 11):
The second frame is different from the first frame in that V1 is at a low voltage level and V2 is at a high voltage level. In the second frame, when n=4i+1 (i++0), still referring to the circuit of FIG. 6, compared to the first frame, since V1 is now connected to the gate of transistor T11, transistor T11 is in the off state, V2 is connected to transistor T12, and transistor T12 is in the on state, so that Pn is pulled all the way to VGL low. At this point, P [ n-2] can pull the Q [ n ] point to VGL low. In the second frame, when n=4i+3 (i.gtoreq.0), referring to the circuit of FIG. 7, since V2 is high, transistor T11 is always on in the second frame, and when transistor T2 is off, P [ n ] charges to high, turning transistor T6 on, transistor T6 pulls down G [ n ] to VGL low, and G [ n ] turns off better than in the first frame. Since V1 is low, the transistor T12 is always in an off state in the second frame. The other timing driving processes are the same as the first frame and will not be described here.
Referring to fig. 2 to 12, a second embodiment of the present invention is as follows:
Referring to fig. 12, a control method of a GIP driving circuit of an embedded display screen includes the following steps:
s1, at a first moment, a high level is input to a gate of a control transistor T1 and a gate of a control transistor T13;
s2, at a second moment, the drain electrode of the control transistor T4 inputs a high level;
And S3, at a third moment, the high level is input to the gate of the control transistor T7 and the gate of the transistor T14.
Step S1 further comprises the steps of:
the drain of the control transistor T4 inputs a low level.
Step S3 further comprises the steps of:
The gate of the control transistor T11 inputs a high level.
In this scheme, each stage of GIP circuit has 21 TFTs, 1 capacitor C1, FW is dc high voltage, 15V is set, bw and VGL are dc low voltage, and-10V is set. For the Q point, the TFTs that pull up the voltage have the transistors T1, T4, and T13, and the TFTs that pull down the voltage have the transistors T3, T9, T15, and T16. According to the scheme, the voltage of the QB node is controlled, so that the transistor T3 and the transistor T9 do not generate electric leakage, a leakage path is not generated at the point Q, electric leakage is not generated at the point Q, and the waveform of G (n) cannot be distorted.
The 21T1C circuit is exemplified by the circuit connection relationship of the scheme, in the scheme, the GIP of a single side of 4 STVs (the starting voltage waveforms of the GIP actions) is taken as an example, STV1 is used as the starting voltages of G1 and G3, and STV3 is used as the starting voltages of G5 and G7.
Referring to fig. 2, when n=1, the GIP output waveform is the first Gate Line waveform, denoted as G [1]. P3 is the P-point voltage of the GIP circuit when n=3, i.e., the gates of the transistors T5, T17, T18 in the GIP circuit of G1 are connected to P3 of G3. The signal connected to the gate of the transistor T12 is V2, and the signal connected to the gate of the transistor T11 is V1.
Referring to fig. 3, when n=3, the GIP output waveform is the third Gate Line waveform, denoted as G [3]. P1 is the P-point voltage of the GIP circuit when n=1, i.e., the gates of the transistors T5, T17, T18 in the GIP circuit of G3 are connected to P1 of G1. The signal connected to the gate of the transistor T12 is V1, and the signal connected to the gate of the transistor T11 is V2.
Referring to fig. 4, when n=5, the GIP output waveform is the fifth Gate Line waveform, denoted as G [5]. P3 is the P-point voltage of the GIP circuit when n=3, i.e., the gates of the transistors T5, T17, T18 in the GIP circuit of G5 are connected to P3 of G3. The signal connected to the gate of the transistor T12 is V2, and the signal connected to the gate of the transistor T11 is V1.
Referring to fig. 5, when n=7, the GIP output waveform is a seventh Gate Line waveform, denoted as G [7]. P5 is the P-point voltage of the GIP circuit when n=5, i.e., the gates of the transistors T5, T17, T18 in the GIP circuit of G7 are connected to P5 of G5. The signal connected to the gate of the transistor T12 is V1, and the signal connected to the gate of the transistor T11 is V2.
In summary, the signals given by the transistors T12 with odd numbers GIP on one side and the gate signals of the transistors T11 are different, and herein, it can be simply understood that the odd-side GIP circuit is divided into odd-numbered and even-numbered stages GIP, which corresponds to the odd-numbered stage G1, the signal connected to the gate of the transistor T12 is V2, and the signal connected to the gate of the transistor T11 is V1. G3 is an even number stage, the signal to which the gate of transistor T12 is connected is V1, and the gate of transistor T11 is connected is a V2 signal. G5 is an odd number of stages, the signal to which the gate of transistor T12 is connected is V2, and the gate of transistor T11 is connected is the V1 signal. G7 is an even number stage, the signal to which the gate of transistor T12 is connected is V1, and the gate of transistor T11 is connected is a V2 signal. The corresponding V1, V2 signals are sequentially and repeatedly transmitted to the gates of the transistors T12 and T11.
Referring to fig. 6, when n=4i+5 (i≡1), the gate connection relationship of the transistors T5, T17 and T18 of GIP starts from stage 9. The P point of G7, P7 is connected with the gates of transistors T5, T17 and T18 of G9, the P point of G11, P11 is connected with the gates of transistors T5, T17 and T18 of G13, and the principle of connecting P point of G n-2, P n-2 with the gates of transistors T5, T17 and T18 in the GIP circuit of G n is circulated downwards. It should be noted here that when n=4i+5 (i+.1), the signal of the gate connection of the transistor T12 in all GIP circuits is V2 and the gate connection of the transistor T11 is V1 signal.
Referring to fig. 7, when n=4i+7 (i≡1), the gate connection relationship of the transistors T5, T17 and T18 of GIP starts from the 11 th stage. The connection of this circuit is the same as in fig. 1, but it should be noted that the signal connected to the gate of the transistor T12 is V1 and the signal connected to the gate of the transistor T11 is V2.
The driving process of the first frame GIP is described below (please analyze in conjunction with fig. 8 and 9):
In fig. 8, in the first frame, V1 is a high voltage, v1=h, and V2 is a low voltage, v2=l. When n=4i+1, i is equal to or greater than 0, reference is made to the GIP circuit diagram of fig. 7, in which the signals connected to the gates of the transistors T12 in all GIP circuits are V2 and the signals connected to the gates of the transistors T11 are V1.
In the GIP circuit diagram of fig. 6, reference is made to the timing chart of fig. 8 (n=4i+1, i+.0). At time T1, vg [ n-8] (i.e., G (n-8)) is at a high potential, and transistors T1, T13, T2, T4, T21 are turned on, and the Q point is charged to FW high potential, where CK (n) is at a low potential state and G [ n ] outputs a low potential. The QB node is charged to a high potential (less than FW) and the P [ n ] node is pulled to a potential VGL state by VGL due to the turn-on of transistor T2. V1 is always high for one frame, T11 is on, but since transistor T2 is more capable of pulling than transistor T11, pn is still pulled to low VGL by transistor T2. V2 is always low for one frame, and the transistor T12 is always in an off state.
At time T2, CK (n) is high, Q [ n ] is high, transistor T4 is kept in an on state, CK (n) transfers voltage to G [ n ] through transistor T4, G [ n ] changes from low to high, and meanwhile, due to capacitive coupling effect of capacitor C1, the potential at the point Q is changed from FW to FW+FW, so that transistor T4 is turned on better. Also, since the Q [ n ] node potential is at this point highest, transistor T21 is turned on best, and QB [ n ] node is charged to FW level.
At time T2, the transistors T3 and T9 are turned off, the Gate voltages of the transistors T3 and T9 are low VGL, and at this time, since the potential of the QB [ n ] node is FW, vgs=vgl-fw= -25V of the transistors T3 and T9, and as is known from the characteristic curve Vgs-Ids of the TFT, ids is particularly small and negligible at vgs= -25V voltage, and the Q point has no leakage path.
At time T3, vg [ n+8] (i.e., G (n+8)) is high, transistor T14, transistor T7 are turned on, the Qn and QB [ n ] node voltages are pulled to BW low voltage level, and transistor T2, transistor T4, transistor T21 are turned off. At this time, since the transistor T2 is turned off, V1 is always in a high potential state, the transistor T11 is also always in an on state, and P [ n ] is charged to a high potential at this time. P [ n ] charges to a high potential, transistor T6 turns on, and transistor T6 pulls G [ n ] to a low potential state.
When n=4i+3, i+.0, reference is made to the GIP circuit of fig. 7, where the signals connected to the gates of the transistors T12 in all GIP circuits are V1 and the signals connected to the gates of the transistors T11 are V2. Since V1 is connected to T12 at this time, transistor T12 is always on, transistor T11 is always off, and the P [ n ] voltage is always pulled to VGL by transistors T2 and T12. At this time, the Qn is reliable P n-2 to pull the voltage to VGL potential, and the charge of the Qn node is discharged.
The driving process of the second frame GIP is described below (please analyze in conjunction with fig. 10 and 11):
The second frame is different from the first frame in that V1 is at a low voltage level and V2 is at a high voltage level. In the second frame, when n=4i+1 (i++0), still referring to the circuit of FIG. 6, compared to the first frame, since V1 is now connected to the gate of transistor T11, transistor T11 is in the off state, V2 is connected to transistor T12, and transistor T12 is in the on state, so that Pn is pulled all the way to VGL low. At this point, P [ n-2] can pull the Q [ n ] point to VGL low. In the second frame, when n=4i+3 (i.gtoreq.0), referring to the circuit of FIG. 7, since V2 is high, transistor T11 is always on in the second frame, and when transistor T2 is off, P [ n ] charges to high, turning transistor T6 on, transistor T6 pulls down G [ n ] to VGL low, and G [ n ] turns off better than in the first frame. Since V1 is low, the transistor T12 is always in an off state in the second frame. The other timing driving processes are the same as the first frame and will not be described here.
In summary, according to the GIP driving circuit and the control method thereof for an embedded display panel provided by the present invention, the gate of the transistor T1 is electrically connected to the gate of the transistor T13, the gates of the transistor T1 and the transistor T13 are both connected to the first gate trace, the source of the transistor T1 is electrically connected to the gate of the transistor T2, the drain of the transistor T3, the drain of the transistor T7, the gate of the transistor T21, the drain of the transistor T9, the drain of the transistor T18, the gate of the transistor T4 and one end of the capacitor C1, the drain of the transistor T10 is electrically connected to the drain of the transistor T6, the other end of the capacitor C1, the source of the transistor T4 and the source of the transistor T5, and the drain of the transistor T10, the drain of the capacitor C1, the other end of the source of the transistor T4 and the source of the transistor T5 are all connected to the second gate trace, the gate of the transistor T14 is electrically connected with the gate of the transistor T7, and the gate of the transistor T14 and the gate of the transistor T7 are both connected with the third gate wiring, so that the Q-point (i.e., the source of the transistor T1, the drain of the transistor T3, the source of the transistor T7, the gate of the transistor T21, the drain of the transistor T9, the source of the transistor T18, the gate of the transistor T4 and the common endpoint of one end of the capacitor C1) voltage of the GIP driving circuit becomes stable, no leakage occurs in the pulled-down TFT, the output waveform of the GIP is improved, the cost of improving the GIP material is saved, and the display quality of the display screen is improved.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent changes made by the specification and drawings of the present invention, or direct or indirect application in the relevant art, are included in the scope of the present invention.

Claims (4)

1. The GIP driving circuit of the embedded display screen is characterized by comprising a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a transistor T10, a transistor T11, a transistor T12, a transistor T13, a transistor T14, a transistor T15, a transistor T16, a transistor T17, a transistor T18, a transistor T19, a transistor T20, a transistor T21 and a capacitor C1, wherein the grid electrode of the transistor T1 is electrically connected with the grid electrode of the transistor T13, the grid electrode of the transistor T1 and the grid electrode of the transistor T13 are connected with a first grid electrode wiring, the drain electrode of the transistor T1 is respectively connected with the source electrode of the transistor T13, the source electrode of the transistor T14, the drain electrode of the transistor T7, the source electrode of the transistor T17, the drain electrode of the transistor T18, the source electrode of the transistor T3, the drain electrode of the transistor T15, the drain electrode of the transistor T21, the drain electrode of the transistor T16 and the source electrode of the transistor T9, the source of the transistor T1 is electrically connected with the gate of the transistor T2, the drain of the transistor T3, the drain of the transistor T7, the gate of the transistor T21, the drain of the transistor T9, the drain of the transistor T18, the gate of the transistor T4 and one end of the capacitor C1, the gate of the transistor T3 is electrically connected with the drain of the transistor T2, the gate of the transistor T15, the drain of the transistor T12, the drain of the transistor T8 and the gate of the transistor T6, the source of the transistor T2 is electrically connected with the source of the transistor T15, the source of the transistor T12, the source of the transistor T8, the source of the transistor T16, the source of the transistor T10 and the source of the transistor T6, the source of the transistor T21 is electrically connected with the source of the transistor T19 and the drain of the transistor T20, and the gate of the transistor T8 is electrically connected with the gate of the transistor T9, the grid electrode of the transistor T16 and the grid electrode of the transistor T10 are electrically connected, the drain electrode of the transistor T10 is electrically connected with the drain electrode of the transistor T6, the other end of the capacitor C1, the source electrode of the transistor T4 and the source electrode of the transistor T5 respectively, the drain electrode of the transistor T10, the drain electrode of the transistor T6, the other end of the capacitor C1, the source electrode of the transistor T4 and the source electrode of the transistor T5 are all connected with the second grid electrode wiring, the grid electrode of the transistor T14 is electrically connected with the grid electrode of the transistor T7, and the grid electrode of the transistor T14 and the grid electrode of the transistor T7 are all connected with the third grid electrode wiring;
The drain electrode of the transistor T4 is connected with a clock signal;
when n=1, the gate of the transistor T5, the gate of the transistor T17 and the gate of the transistor T18 are all connected to the gate signal P [3] of the transistor;
When n is an odd number greater than 1, the gate of the transistor T5, the gate of the transistor T17 and the gate of the transistor T18 are all connected with the gate signal P [ n-2] of the transistor;
Wherein n is the number of stages of the GIP circuit, and the P point is the gate voltage of the transistor T3;
The gate of the transistor T11 is electrically connected with the drain of the transistor T11, the gate of the transistor T11 and the drain of the transistor T11 are both connected with a first voltage, the gate of the transistor T12 is connected with a second voltage, the gate of the transistor T19 is electrically connected with the drain of the transistor T19, the gate of the transistor T19 and the drain of the transistor T19 are both connected with the first voltage, the gate of the transistor T20 is electrically connected with the drain of the transistor T20, and the gate of the transistor T20 and the drain of the transistor T20 are both connected with the second voltage;
the drain electrode of the transistor T17 is connected to the negative electrode of the power supply, and the source electrode of the transistor T5, the source electrode of the transistor T2, the source electrode of the transistor T15, the source electrode of the transistor T12, the source electrode of the transistor T8, the source electrode of the transistor T16, the source electrode of the transistor T10 and the source electrode of the transistor T6 are all connected to the negative electrode of the power supply;
the source of the transistor T14 is connected to the low voltage signal BW, and the source of the transistor T13 is connected to the high voltage signal FW;
the transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, and T21 are all N-channel MOS transistors.
2. A control method of the GIP driving circuit of the in-cell display screen of claim 1, comprising the steps of:
s1, at a first moment, a high level is input to a gate of a control transistor T1 and a gate of a control transistor T13;
s2, at a second moment, the drain electrode of the control transistor T4 inputs a high level;
And S3, at a third moment, the high level is input to the gate of the control transistor T7 and the gate of the transistor T14.
3. The method of controlling a GIP driving circuit of an in-cell display according to claim 2, wherein the step S1 further comprises the steps of:
the drain of the control transistor T4 inputs a low level.
4. The method of controlling a GIP driving circuit of an in-cell display according to claim 2, wherein the step S3 further comprises the steps of:
The gate of the control transistor T11 inputs a high level.
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