CN114170989A - GIP circuit for improving stability of display screen and driving method thereof - Google Patents
GIP circuit for improving stability of display screen and driving method thereof Download PDFInfo
- Publication number
- CN114170989A CN114170989A CN202210027491.3A CN202210027491A CN114170989A CN 114170989 A CN114170989 A CN 114170989A CN 202210027491 A CN202210027491 A CN 202210027491A CN 114170989 A CN114170989 A CN 114170989A
- Authority
- CN
- China
- Prior art keywords
- point
- potential
- vgl
- low potential
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 12
- 239000003990 capacitor Substances 0.000 claims abstract description 5
- 230000008878 coupling Effects 0.000 claims description 8
- 238000010168 coupling process Methods 0.000 claims description 8
- 238000005859 coupling reaction Methods 0.000 claims description 8
- 230000001808 coupling effect Effects 0.000 claims description 4
- 239000010409 thin film Substances 0.000 claims description 2
- 230000002159 abnormal effect Effects 0.000 abstract description 4
- 230000005540 biological transmission Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 5
- 230000000087 stabilizing effect Effects 0.000 description 2
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a GIP circuit for improving the stability of a display screen and a driving method thereof.A GIP of each stage is provided with 16 TFTs from T1 to T16 and 1 capacitor C1, the sizes of T15 and T16 devices are designed to be larger than T14, the sizes of T2 devices are designed to be larger than T8, and the sizes of T12 devices are designed to be larger than T9. When the Q point needs to keep the high level, the T14, the T15 and the T16 can effectively prevent the T3 and the T13 from electric leakage to cause the insufficient high potential level of the Q point, thereby influencing GIP level transmission and finally causing the abnormal picture.
Description
Technical Field
The invention relates to the technical field of display screen driving, in particular to a GIP circuit for improving the stability of a display screen and a driving method thereof.
Background
The problem of leakage of a TFT device of a voltage stabilizing circuit exists in a GIP circuit of an LCD display screen, and if the leakage quantity is large, the problems of wrong charging, GIP level transmission failure, insufficient charging and the like can be caused, so that the display of the display screen is abnormal.
Disclosure of Invention
The invention aims to provide a GIP circuit for improving the stability of a display screen and a driving method thereof.
The technical scheme adopted by the invention is as follows:
a GIP circuit for improving the stability of a display screen comprises transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16 and a capacitor C1;
the gate of T1 is connected with Gn-4, the drain of T1 is connected with VGH, and the source of T1 is connected with a point Q;
the gate of T2 is connected to point Q, the drain of T2 is connected to point P1, and the source of T2 is connected to VGL;
the gate of T3 is connected with point P1, the drain of T3 is connected with point Q, and the source of T3 is connected with point S;
the grid of T4 is connected with the point Q, the drain of T4 is connected with CK (n), and the source of T4 is connected with Gn;
the gate of T5 is connected with point P2, the drain of T5 is connected with Gn, and the source of T5 is connected with VGL;
the gate of T6 is connected with point P1, the drain of T6 is connected with Gn, and the source of T6 is connected with VGL;
the gate of T7 is connected with Gn +4, the drain of T7 is connected with VGL, and the source of T7 is connected with a point Q;
the gate and the drain of the T8 are connected with the V2, and the source of the T8 is connected with the point P1;
the gate and the drain of the T9 are connected with the V1, and the source of the T9 is connected with the point P2;
the gate of T10 is connected with V1, the drain of T10 is connected with point P1, and the source of T10 is VGL;
the gate of T11 is connected with V2, the drain of T11 is connected with point P2, and the source of T11 is connected with VGL;
the gate of T12 is connected to point Q, the drain of T12 is connected to point P2, and the source of T12 is connected to VGL;
the gate of T13 is connected with the point P2, the drain of T13 is connected with the point S, and the source of T13 is connected with the point Q;
the gate of T14 is connected with the point Q, the drain of T14 is connected with the point S, and the source of T14 is connected with VGH;
the gate of T15 is connected with point P1, the drain of T15 is connected with point S, and the source of T15 is connected with VGL;
the gate of T16 is connected with point P2, the drain of T16 is connected with point S, and the source of T16 is connected with VGL;
one plate of C1 is connected to point Q, and the other plate of C1 is connected to Gn.
Further, the device sizes of T15 and T16 are larger than T14, the device size of T2 is larger than T8, and the device size of T12 is larger than T9.
Further, the GIP circuit is disposed on the display panel and located at one side of the display panel.
Further, the display panel is an OLED display panel or an LCD display panel.
Furthermore, the device also comprises a driving IC, and Gn, Gn-4 and Gn +4 are connected with the driving IC.
Further, the transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, and T16 are all thin film transistors.
A driving method of a GIP circuit for improving the stability of a display screen is applied to the GIP circuit for improving the stability of the display screen, the method comprises a positive frame part and a negative frame part, and the method specifically comprises the following steps:
for a positive frame: v1 is set to VGL while V2 is set to VGH;
time t 1: gn-4 outputs high potential, so that the point Q is high potential; the point P1 is at low potential, T11 and T12 are turned on, the point P2 is changed from high potential to low potential, and the point S is at high potential; CKn, CKn +4, Gn +4 and VGL are maintained at a low potential;
time t 2: gn-4 outputs a low potential, CKn is a high potential, so that Gn is a high potential, and the Q point is pulled high due to the capacitive coupling potential of C1; CKn +4, Gn +4 and VGL are maintained at a low potential;
time t 3: CKn outputs low potential, the Q point is lowered due to the capacitance coupling potential of C1, and Gn outputs low potential; gn-4, CKn +4, Gn +4 and VGL are maintained at a low potential;
time t 4: CKn +4 outputs high potential, Gn +4 outputs high potential, so that a point Q is low potential, a point P1 is high potential, a point P2 is low potential, a point S is low potential, and the point Q discharges through T3 and T15; CKn, Gn-4, Gn and VGL are maintained at a low potential;
for negative frames: v1 is set to VGH while V2 is set to VGL;
time t 1: gn-4 outputs high potential to make point Q high potential and make point P2 low potential; t2 and T10 are turned on, and the point P1 is pulled from high potential to low potential; the S point is high potential; CKn, CKn +4, Gn +4 and VGL are maintained at a low potential;
time t 2: gn-4 outputs a low potential, CKn is changed from the low potential to a high potential, Gn is high potential, and the potential of a point Q is pulled high again due to the capacitive coupling effect of C1; CKn +4, Gn +4 and VGL are maintained at a low potential;
time t 3: CKn outputs low potential, the Q point is lowered due to the capacitance coupling potential of C1, and Gn outputs low potential; gn-4, CKn +4, Gn +4 and VGL are maintained at a low potential;
time t 4: CKn +4 outputs high potential, Gn +4 outputs high potential, so that a point Q is changed from high potential to low potential, a point P2 is pulled to high potential, a point S is changed from high potential to low potential, and the point Q is discharged through T13 and T16; CKn, Gn-4, Gn and VGL are maintained at a low potential.
By adopting the technical scheme, the level of the key node of the TFT is pulled up at a specific moment, the problem of abnormal display caused by electric leakage of a TFT device of the voltage stabilizing circuit is prevented, and the stability of the display screen is improved.
Drawings
The invention is described in further detail below with reference to the accompanying drawings and the detailed description;
FIG. 1 is a schematic structural diagram of a GIP circuit for improving the stability of a display panel according to the present invention;
FIG. 2 is a timing diagram of a positive frame of a GIP circuit for improving the stability of a display panel according to the present invention;
FIG. 3 is a negative frame timing diagram of a GIP circuit for improving the stability of a display panel according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
As shown in one of fig. 1 to 3, the present invention discloses a GIP circuit for improving stability of a display screen, which includes transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, and a capacitor C1;
the gate of T1 is connected with Gn-4, the drain of T1 is connected with VGH, and the source of T1 is connected with a point Q;
the gate of T2 is connected to point Q, the drain of T2 is connected to point P1, and the source of T2 is connected to VGL;
the gate of T3 is connected with point P1, the drain of T3 is connected with point Q, and the source of T3 is connected with point S;
the grid of T4 is connected with the point Q, the drain of T4 is connected with CK (n), and the source of T4 is connected with Gn;
the gate of T5 is connected with point P2, the drain of T5 is connected with Gn, and the source of T5 is connected with VGL;
the gate of T6 is connected with point P1, the drain of T6 is connected with Gn, and the source of T6 is connected with VGL;
the gate of T7 is connected with Gn +4, the drain of T7 is connected with VGL, and the source of T7 is connected with a point Q;
the gate and the drain of the T8 are connected with the V2, and the source of the T8 is connected with the point P1;
the gate and the drain of the T9 are connected with the V1, and the source of the T9 is connected with the point P2;
the gate of T10 is connected with V1, the drain of T10 is connected with point P1, and the source of T10 is VGL;
the gate of T11 is connected with V2, the drain of T11 is connected with point P2, and the source of T11 is connected with VGL;
the gate of T12 is connected to point Q, the drain of T12 is connected to point P2, and the source of T12 is connected to VGL;
the gate of T13 is connected with the point P2, the drain of T13 is connected with the point S, and the source of T13 is connected with the point Q;
the gate of T14 is connected with the point Q, the drain of T14 is connected with the point S, and the source of T14 is connected with VGH;
the gate of T15 is connected with point P1, the drain of T15 is connected with point S, and the source of T15 is connected with VGL;
the gate of T16 is connected with point P2, the drain of T16 is connected with point S, and the source of T16 is connected with VGL;
one plate of C1 is connected to point Q, and the other plate of C1 is connected to Gn.
Specifically, as shown in fig. 1, each stage of GIP of the inventive GIP circuit has 16 TFTs T1-T16 and 1 capacitor C1, fig. 2 and 3 are circuit diagrams and timing diagrams, VGH is a dc high voltage, VGL is a dc low voltage, T15 and T16 devices are designed to be larger than T14, T2 devices are designed to be larger than T8, and T12 devices are designed to be larger than T9. The large-sized device can determine the current flow direction, and the current is influenced by the large-sized device under the condition that the two devices are simultaneously started.
When the Q point needs to keep the high level, the T14, the T15 and the T16 can effectively prevent the T3 and the T13 from electric leakage to cause the insufficient high potential level of the Q point, thereby influencing GIP level transmission and finally causing the abnormal picture.
The GIP driving process is as follows:
1. and (3) positive frame: v1= VGL, V2= VGH.
time t 1: gn-4 is high, T1 is turned on, the point Q is pulled to high, and T2, T4, T12 and T14 are turned on; v2 is high potential, T8 is turned on, and since the size of the T2 device is larger than that of T8, P1 point is low potential; t11, T12 turn on, and the point P2 is pulled low. Since T3, T13, T15 and T16 are closed, T14 is opened, and the point S is at a high potential.
time t 2: gn-4 changes to low potential, T1 is closed, CKn changes from low potential to high potential, T4 gives high potential of CKn to Gn, and the potential of Q point is pulled up again due to the capacitive coupling action of C1.
time t 3: the CKn potential changes from high potential to low potential, and the Q point is lowered due to the capacitance coupling potential of C1.
time t 4: gn +4 becomes high potential, T7 is turned on to give the low potential of VGL to a point Q, the point Q is changed from high potential to low potential, T2, T4, T12 and T14 are turned off, the potential P1 is pulled to high potential by T8, T3, T6 and T15 are turned on, and the point Q is discharged through T3 and T15 because the size of the T15 device is larger than that of T14 and the point S is low potential.
2. Negative frame: v1= VGH, V2= VGL.
time t 1: gn-4 is high, T1 is turned on, the point Q is pulled to high, and T2, T4, T12 and T14 are turned on; v1 is high potential, T9 and T10 are turned on, and P2 point is low potential because the size of the T12 device is larger than that of T9; t2, T10 are turned on, and P1 is pulled to a low potential; since T3, T13, T15 and T16 are closed, T14 is opened, and the point S is at a high potential.
time t 2: gn-4 changes to low potential, T1 is closed, CKn changes from low potential to high potential, T4 gives high potential of CKn to Gn, and the potential of Q point is pulled up again due to the capacitive coupling action of C1.
time t 3: the CKn potential changes from high potential to low potential, and the Q point is lowered due to the capacitance coupling potential of C1.
time t 4: gn +4 becomes high potential, T7 is turned on to give low potential of VGL to point Q, point Q is changed from high potential to low potential, T2, T4, T12 and T14 are turned off, point P2 is pulled to high potential by T9, T5, T13 and T16 are turned on, and point Q is discharged through T13 and T16 because T16 is larger than T14 in device size and point S is changed to low potential.
By adopting the technical scheme, T14 exists in the driving process, even if Vth of T3 and T13 drifts from positive voltage to negative voltage, the leaked Vth is still at a HIGH level, display abnormity caused by leakage of T3 and T13 is effectively prevented, and the stability of the display screen is improved.
It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. The embodiments and features of the embodiments in the present application may be combined with each other without conflict. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the detailed description of the embodiments of the present application is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Claims (7)
1. The utility model provides a improve GIP circuit of display screen stability which characterized in that: the circuit comprises transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16 and a capacitor C1;
the gate of T1 is connected with Gn-4, the drain of T1 is connected with VGH, and the source of T1 is connected with a point Q;
the gate of T2 is connected to point Q, the drain of T2 is connected to point P1, and the source of T2 is connected to VGL;
the gate of T3 is connected with point P1, the drain of T3 is connected with point Q, and the source of T3 is connected with point S;
the grid of T4 is connected with the point Q, the drain of T4 is connected with CK (n), and the source of T4 is connected with Gn;
the gate of T5 is connected with point P2, the drain of T5 is connected with Gn, and the source of T5 is connected with VGL;
the gate of T6 is connected with point P1, the drain of T6 is connected with Gn, and the source of T6 is connected with VGL;
the gate of T7 is connected with Gn +4, the drain of T7 is connected with VGL, and the source of T7 is connected with a point Q;
the gate and the drain of the T8 are connected with the V2, and the source of the T8 is connected with the point P1;
the gate and the drain of the T9 are connected with the V1, and the source of the T9 is connected with the point P2;
the gate of T10 is connected with V1, the drain of T10 is connected with point P1, and the source of T10 is VGL;
the gate of T11 is connected with V2, the drain of T11 is connected with point P2, and the source of T11 is connected with VGL;
the gate of T12 is connected to point Q, the drain of T12 is connected to point P2, and the source of T12 is connected to VGL;
the gate of T13 is connected with the point P2, the drain of T13 is connected with the point S, and the source of T13 is connected with the point Q;
the gate of T14 is connected with the point Q, the drain of T14 is connected with the point S, and the source of T14 is connected with VGH;
the gate of T15 is connected with point P1, the drain of T15 is connected with point S, and the source of T15 is connected with VGL;
the gate of T16 is connected with point P2, the drain of T16 is connected with point S, and the source of T16 is connected with VGL;
one plate of C1 is connected to point Q, and the other plate of C1 is connected to Gn.
2. The GIP circuit for improving the stability of the display screen according to claim 1, wherein: the device sizes of T15 and T16 are larger than T14, the device size of T2 is larger than T8, and the device size of T12 is larger than T9.
3. The GIP circuit for improving the stability of the display screen according to claim 1, wherein: the GIP circuit is arranged on the display panel and is positioned on one side of the display panel.
4. The GIP circuit for improving the stability of the display screen according to claim 3, wherein: the display panel is an OLED display panel or an LCD display panel.
5. The GIP circuit for improving the stability of the display screen according to claim 1, wherein: the driver IC is further included, and Gn, Gn-4 and Gn +4 are connected with the driver IC.
6. The GIP circuit for improving the stability of the display screen according to claim 1, wherein: the transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, and T16 are all thin film transistors.
7. A driving method of a GIP circuit for improving stability of a display screen, applied to the GIP circuit for improving stability of the display screen according to any one of claims 1 to 6, wherein: the method comprises a positive frame part and a negative frame part, and specifically comprises the following steps:
for a positive frame: v1 is set to VGL while V2 is set to VGH;
time t 1: gn-4 outputs high potential, so that the point Q is high potential; the point P1 is at low potential, T11 and T12 are turned on, the point P2 is changed from high potential to low potential, and the point S is at high potential; CKn, CKn +4, Gn +4 and VGL are maintained at a low potential;
time t 2: gn-4 outputs a low potential, CKn is a high potential, so that Gn is a high potential, and the Q point is pulled high due to the capacitive coupling potential of C1; CKn +4, Gn +4 and VGL are maintained at a low potential;
time t 3: CKn outputs low potential, the Q point is lowered due to the capacitance coupling potential of C1, and Gn outputs low potential; gn-4, CKn +4, Gn +4 and VGL are maintained at a low potential;
time t 4: CKn +4 outputs high potential, Gn +4 outputs high potential, so that a point Q is low potential, a point P1 is high potential, a point P2 is low potential, a point S is low potential, and the point Q discharges through T3 and T15; CKn, Gn-4, Gn and VGL are maintained at a low potential;
for negative frames: v1 is set to VGH while V2 is set to VGL;
time t 1: gn-4 outputs high potential to make point Q high potential and make point P2 low potential; t2 and T10 are turned on, and the point P1 is pulled from high potential to low potential; the S point is high potential; CKn, CKn +4, Gn +4 and VGL are maintained at a low potential;
time t 2: gn-4 outputs a low potential, CKn is changed from the low potential to a high potential, Gn is high potential, and the potential of a point Q is pulled high again due to the capacitive coupling effect of C1; CKn +4, Gn +4 and VGL are maintained at a low potential;
time t 3: CKn outputs low potential, the Q point is lowered due to the capacitance coupling potential of C1, and Gn outputs low potential; gn-4, CKn +4, Gn +4 and VGL are maintained at a low potential;
time t 4: CKn +4 outputs high potential, Gn +4 outputs high potential, so that a point Q is changed from high potential to low potential, a point P2 is pulled to high potential, a point S is changed from high potential to low potential, and the point Q is discharged through T13 and T16; CKn, Gn-4, Gn and VGL are maintained at a low potential.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202210027491.3A CN114170989A (en) | 2022-01-11 | 2022-01-11 | GIP circuit for improving stability of display screen and driving method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202210027491.3A CN114170989A (en) | 2022-01-11 | 2022-01-11 | GIP circuit for improving stability of display screen and driving method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
CN114170989A true CN114170989A (en) | 2022-03-11 |
Family
ID=80489242
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202210027491.3A Pending CN114170989A (en) | 2022-01-11 | 2022-01-11 | GIP circuit for improving stability of display screen and driving method thereof |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN114170989A (en) |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112331156A (en) * | 2020-11-04 | 2021-02-05 | 武汉华星光电技术有限公司 | GOA circuit and display panel |
CN112735350A (en) * | 2021-01-12 | 2021-04-30 | 福建华佳彩有限公司 | GIP circuit and driving method thereof |
CN112735322A (en) * | 2021-01-22 | 2021-04-30 | 福建华佳彩有限公司 | GIP circuit and driving method |
CN112967654A (en) * | 2021-03-23 | 2021-06-15 | 福建华佳彩有限公司 | GIP circuit and driving method |
CN113035109A (en) * | 2021-02-25 | 2021-06-25 | 福建华佳彩有限公司 | GIP driving circuit of embedded display screen and control method thereof |
CN113611254A (en) * | 2021-08-04 | 2021-11-05 | 福建华佳彩有限公司 | GIP circuit for solving abnormal picture of display screen and driving method thereof |
CN113724668A (en) * | 2021-10-14 | 2021-11-30 | 福建华佳彩有限公司 | Multi-output GIP circuit for improving GIP stability and driving method thereof |
CN113763902A (en) * | 2021-10-14 | 2021-12-07 | 福建华佳彩有限公司 | 16T1C multi-output GIP circuit and driving method thereof |
CN217214119U (en) * | 2022-01-11 | 2022-08-16 | 福建华佳彩有限公司 | GIP circuit for improving stability of display screen |
-
2022
- 2022-01-11 CN CN202210027491.3A patent/CN114170989A/en active Pending
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112331156A (en) * | 2020-11-04 | 2021-02-05 | 武汉华星光电技术有限公司 | GOA circuit and display panel |
CN112735350A (en) * | 2021-01-12 | 2021-04-30 | 福建华佳彩有限公司 | GIP circuit and driving method thereof |
CN112735322A (en) * | 2021-01-22 | 2021-04-30 | 福建华佳彩有限公司 | GIP circuit and driving method |
CN113035109A (en) * | 2021-02-25 | 2021-06-25 | 福建华佳彩有限公司 | GIP driving circuit of embedded display screen and control method thereof |
CN112967654A (en) * | 2021-03-23 | 2021-06-15 | 福建华佳彩有限公司 | GIP circuit and driving method |
CN113611254A (en) * | 2021-08-04 | 2021-11-05 | 福建华佳彩有限公司 | GIP circuit for solving abnormal picture of display screen and driving method thereof |
CN113724668A (en) * | 2021-10-14 | 2021-11-30 | 福建华佳彩有限公司 | Multi-output GIP circuit for improving GIP stability and driving method thereof |
CN113763902A (en) * | 2021-10-14 | 2021-12-07 | 福建华佳彩有限公司 | 16T1C multi-output GIP circuit and driving method thereof |
CN217214119U (en) * | 2022-01-11 | 2022-08-16 | 福建华佳彩有限公司 | GIP circuit for improving stability of display screen |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10013942B2 (en) | GOA circuit, driving method thereof and liduid crystal display device | |
CN103258495B (en) | Shifting deposit unit, shift register and display device | |
CN102867491B (en) | LCD (Liquid Crystal Display) panel drive circuit and method as well as display unit | |
CN204558001U (en) | Power-off ghost shadow eliminates circuit and gate driver circuit | |
US20140078127A1 (en) | Display apparatus and method for generating gate signal thereof | |
WO2016192139A1 (en) | Goa circuit based on oxide semiconductor thin film transistor | |
CN109147641B (en) | Shutdown ghost eliminating circuit, shift register unit and display device | |
JP2020500333A (en) | IGZO thin film transistor GOA circuit and display device | |
KR20160078438A (en) | Array substrate row drive circuit | |
CN107808650B (en) | GOA circuit | |
CN108573668A (en) | Shift register cell and its driving method, gate driving circuit and display device | |
CN109473078B (en) | Common voltage regulating circuit and method, display driving circuit and display device | |
JP6555842B2 (en) | GOA circuit, driving method thereof, and liquid crystal display | |
CN217214119U (en) | GIP circuit for improving stability of display screen | |
WO2020042396A1 (en) | Pixel drive circuit, display panel and display apparatus | |
CN113223471A (en) | GIP circuit with compensation function and compensation method | |
CN114170989A (en) | GIP circuit for improving stability of display screen and driving method thereof | |
CN109256079B (en) | Gate driver circuit and gate driver | |
EP4047591A1 (en) | Shift register unit, driving method, gate drive circuit, and display device | |
CN213844093U (en) | GIP circuit | |
CN113611254A (en) | GIP circuit for solving abnormal picture of display screen and driving method thereof | |
US11100876B2 (en) | Latch circuit based on thin-film transistor, pixel circuit and driving method, display apparatus | |
CN112885282B (en) | GIP circuit suitable for high-resolution display screen and control method thereof | |
CN214541521U (en) | GIP circuit | |
CN112885286B (en) | GIP circuit for reducing display defects and control method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |