CN112735350A - GIP circuit and driving method thereof - Google Patents

GIP circuit and driving method thereof Download PDF

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Publication number
CN112735350A
CN112735350A CN202110034773.1A CN202110034773A CN112735350A CN 112735350 A CN112735350 A CN 112735350A CN 202110034773 A CN202110034773 A CN 202110034773A CN 112735350 A CN112735350 A CN 112735350A
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written
node
low potential
input end
potential
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谢建峰
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Fujian Huajiacai Co Ltd
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Fujian Huajiacai Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention discloses a GIP circuit, wherein the output end of T1 is connected with Qb; the input end of T2 is connected with Qb; the output end of the T2 is connected with Q; the output end of T3 is connected with P; the control end of T4 is connected with Q; the input end of T5 is connected with P, and the control end of T5 is connected with Q; the input end of the T6 is connected with Q, the output end of the T6 is connected with Qb, and the control end of the T6 is connected with P; the input end of T7 is connected with Qb, and the control end of T7 is connected with P; the input end of T8 is connected with P; the input end of the T9 is connected with Q, and the output end of the T9 is connected with Qb; the input end of T10 is connected with Qb; the control end of T11 is connected with P; the input end of the T12 is connected with Q, and the output end of the T12 is connected with Qb; the input end of T13 is connected with Qb; the input end of T15 is connected with P; c1 has a plate connected to Q. According to the technical scheme, the potential of the point Q is improved, so that the potential drop caused by electric leakage due to negative bias of the threshold voltage of the transistor can not occur to the voltage of the point Q, the output waveform of the GIP can not be distorted, and the display effect of the display screen is optimized.

Description

GIP circuit and driving method thereof
Technical Field
The invention relates to the field of LCD (liquid crystal display) screens, in particular to a GIP (gate in-phase) circuit and a driving method thereof.
Background
For a display screen, the waveform transmission of the GIP circuit is very important, and it is related to whether the in-plane pixels can work normally. In fact, due to the uncontrollable factors in the manufacturing process, the threshold voltage of the transistor of the GIP circuit may be less than 0, and at this time, the waveform output of the GIP circuit may be adversely affected, thereby causing abnormal operation of the in-plane pixels and degrading the display quality.
Disclosure of Invention
Therefore, it is desirable to provide a GIP circuit and a driving method thereof to overcome waveform transmission abnormality caused by negative threshold voltage due to process factors, thereby improving the display effect of the display panel.
The present application provides a GIP circuit, comprising a transistor: t1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, and T16, further comprising a capacitance: c1;
the input end of the T1 is connected with FW, the output end of the T1 is connected with a node Qb, and the control end of the T1 is connected with Vg (n-4);
the input end of the T2 is connected with the Qb node, the output end of the T2 is connected with the Q node, and the control end of the T2 is connected with Vg (n-4);
the input end of the T3 is connected with CK (n), the output end of the T3 is connected with a P node, and the control end of the T3 is connected with CK (n);
the input end of the T4 is connected with CK (n), the output end of the T4 is connected with Vg (n), and the control end of the T4 is connected with a node Q;
the input end of the T5 is connected with a P node, the output end of the T5 is connected with VGL, and the control end of the T5 is connected with a Q node;
the input end of the T6 is connected with a node Q, the output end of the T6 is connected with a node Qb, and the control end of the T6 is connected with a node P;
the input end of the T7 is connected with the Qb node, the output end of the T7 is connected with VGL, and the control end of the T7 is connected with the P node;
the input end of the T8 is connected with a P node, the output end of the T8 is connected with VGL, and the control end of the T8 is connected with CK (n + 4);
the input end of the T9 is connected with a node Q, the output end of the T9 is connected with a node Qb, and the control end of the T9 is connected with Vg (n + 4);
the input end of the T10 is connected with the Qb node, the output end of the T10 is connected with the BW, and the control end of the T10 is connected with the Vg (n + 4);
the input end of the T11 is connected with Vg (n), the output end of the T11 is connected with VGL, and the control end of the T11 is connected with a P node;
the input end of the T12 is connected with a node Q, the output end of the T12 is connected with a node Qb, and the control end of the T12 is connected with a CLR;
the input end of the T13 is connected with the Qb node, the output end of the T13 is connected with VGL, and the control end of the T13 is connected with CLR;
the input end of the T14 is connected with Vg (n), the output end of the T14 is connected with VGL, and the control end of the T14 is connected with CLR;
the input end of the T15 is connected with a P node, the output end of the T15 is connected with VGL, and the control end of the T15 is connected with CLR;
the input end of the T16 is connected with Vg (n), the output end of the T16 is connected with VGL, and the control end of the T16 is connected with CK (n + 4);
one polar plate of the C1 is connected with the Q node, and the other polar plate of the C1 is connected with Vg (n).
Further, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, and T16 are thin film transistors, and T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, and T16 are provided on the display panel.
Further, the display panel is an LCD display panel.
Further, a sub-pixel is included, and vg (n) is connected to the sub-pixel.
Further, the device also comprises a driving IC, and CK (n), CK (n +4), Vg (n-4) and Vg (n +4) are connected with the driving IC.
The application also provides a GIP circuit driving method, which is applied to any one GIP circuit and comprises the following steps:
at the stage t1, Vg (n-4) is written with high potential, CK (n) is written with low potential, CK (n +4) is written with high potential, Vg (n) is written with low potential, and Vg (n +4) is written with low potential;
at the stage t2, Vg (n-4) is written with a low potential, CK (n +4) is written with a low potential, Vg (n) is written with a low potential, and Vg (n +4) is written with a low potential;
at the stage t3, Vg (n-4) is written with low potential, CK (n) is written with high potential, CK (n +4) is written with low potential, Vg (n) is written with high potential, and Vg (n +4) is written with low potential;
at the stage t4, Vg (n-4) is written with a low potential, CK (n +4) is written with a low potential, Vg (n) is written with a low potential, and Vg (n +4) is written with a low potential;
at stage t5, Vg (n-4) writes a low potential, CK (n +4) writes a high potential and then writes a low potential, Vg (n) writes a low potential, and Vg (n +4) writes a high potential and then writes a low potential;
at the stage t6, Vg (n-4) is written with a low potential, CK (n) is written with a high potential, CK (n +4) is written with a low potential, Vg (n) is written with a low potential, and Vg (n +4) is written with a low potential.
Further, in the period from t1 to t6, FW continues to be written with the high potential, and VGL continues to be written with the low potential.
Different from the prior art, the technical scheme improves the potential of the point Q, so that the voltage of the point Q cannot be reduced due to electric leakage caused by negative bias of the threshold voltage of the transistor, the output waveform of the GIP cannot be distorted, and the display effect of the display screen is optimized.
Drawings
FIG. 1 is a GIP circuit as described;
fig. 2 is a timing diagram of the GIP circuit.
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 1 to 2, the present embodiment provides a GIP circuit, including transistors: t1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, and T16, further comprising a capacitance: c1; the input end of the T1 is connected with FW, the output end of the T1 is connected with a node Qb, and the control end of the T1 is connected with Vg (n-4); the input end of the T2 is connected with the Qb node, the output end of the T2 is connected with the Q node, and the control end of the T2 is connected with Vg (n-4); the input end of the T3 is connected with CK (n), the output end of the T3 is connected with a P node, and the control end of the T3 is connected with CK (n); the input end of the T4 is connected with CK (n), the output end of the T4 is connected with Vg (n), and the control end of the T4 is connected with a node Q; the input end of the T5 is connected with a P node, the output end of the T5 is connected with VGL, and the control end of the T5 is connected with a Q node; the input end of the T6 is connected with a node Q, the output end of the T6 is connected with a node Qb, and the control end of the T6 is connected with a node P; the input end of the T7 is connected with the Qb node, the output end of the T7 is connected with VGL, and the control end of the T7 is connected with the P node; the input end of the T8 is connected with a P node, the output end of the T8 is connected with VGL, and the control end of the T8 is connected with CK (n + 4); the input end of the T9 is connected with a node Q, the output end of the T9 is connected with a node Qb, and the control end of the T9 is connected with Vg (n + 4); the input end of the T10 is connected with the Qb node, the output end of the T10 is connected with the BW, and the control end of the T10 is connected with the Vg (n + 4); the input end of the T11 is connected with Vg (n), the output end of the T11 is connected with VGL, and the control end of the T11 is connected with a P node; the input end of the T12 is connected with a node Q, the output end of the T12 is connected with a node Qb, and the control end of the T12 is connected with a CLR; the input end of the T13 is connected with the Qb node, the output end of the T13 is connected with VGL, and the control end of the T13 is connected with CLR; the input end of the T14 is connected with Vg (n), the output end of the T14 is connected with VGL, and the control end of the T14 is connected with CLR; the input end of the T15 is connected with a P node, the output end of the T15 is connected with VGL, and the control end of the T15 is connected with CLR; the input end of the T16 is connected with Vg (n), the output end of the T16 is connected with VGL, and the control end of the T16 is connected with CK (n + 4); one polar plate of the C1 is connected with the Q node, and the other polar plate of the C1 is connected with Vg (n). It should be noted that the transistor in the present application may be a P-type transistor or an N-type transistor, that is, in the N-type transistor, an input terminal is a drain, and an output terminal is a source; the input end of the P-type transistor is a source electrode, and the output end of the P-type transistor is a drain electrode; and either transistor control terminal is a gate. Vg (n) is the output voltage, and Vg (n) is connected to a pixel point; CK is a clock signal line.
Vg (n) in this application denotes the nth sub-pixel of a certain row; vg (n +4) and Vg (n-4) in (n +4) and (n +4) are used to represent the start-up period of the pixel points, i.e. how many pixel points are turned on in sequence in each period. A plurality of GIP circuits are arranged in the display panel, each GIP circuit is connected to one sub-pixel through G (n), and CK (n), CK (n +4), Vg (n-4) and Vg (n +4) are connected to a driving IC. A plurality of sub-pixels are arranged on the display panel in an array mode, and a GIP circuit is connected to each sub-pixel. It should be further noted that the gate, i.e., the control terminal in this application, is used to control the transistor to be turned on or off, and when the control terminal writes a high voltage, the transistor is turned on; such as: since FW is continuously written with high voltage, T1 is turned on only when Vg (n-4) inputs high voltage, and the same is true for the turn-on modes of T2, T3, etc.
In this embodiment, each stage of GIP circuit has 16 TFTs, 1 capacitor C1, FW is dc high voltage, here we assume 15V, BW, VGL are dc low voltage, here we assume-10V. In this patent, the high potential of CK (n) and CK (n +4) is FW potential, and the low potential is VGL potential. For the Q point, the transistors for pulling up the voltage are T1, T2, T4, and the transistors for pulling down the voltage are T6, T7, T9, T10, T12, T13. By introducing the voltage of the Qb node, the leakage current of T6, T9 and T12 is suppressed, the Q point has no leakage path, the voltage of the Q point is not attenuated, and the waveform of Vg (n) is not distorted. According to the technical scheme, the potential of the point Q is improved, so that the potential drop caused by electric leakage due to negative bias of the threshold voltage of the transistor can not occur to the voltage of the point Q, the output waveform of the GIP can not be distorted, and the display effect of the display screen is optimized.
The driving process of the GIP circuit is described below with reference to the timing diagram of fig. 2:
at time T1, Vg (n-4) is high, at which time T1 and T2 are turned on, and charging is started at points Q and Qb. At this time, CK (n +4) is high, T8 is on, Q is high, T5 is on, so P is pulled down to VGL through these paths. Since point Q is high, T4 is turned on, vg (n) is low (ck (n) is low).
At time T2, Vg (n-4) is low, at which time T1 and T2 are in an off state, and points Q and Qb remain in a drift state. Here, assuming that the threshold voltages of the transistors T6, T7, T9, T10, T12 and T13 are less than 0, T7, T10 and T13 are analyzed, Vgs of the transistors is 0, and leakage current is generated; for T6, T9, and T12, Vgs of these transistors is smaller than 0 (due to the node Qb), so that the voltage at the Q point does not drop due to the influence of leakage current, and the voltage at the Q point does not decay.
At time T3, the potential of ck (n) changes from low to high, and at this time, due to the existence of the capacitor C1, the potential at the point Q becomes higher due to the capacitive coupling effect, T4 is turned on, and the waveform transmission of vg (n) is better, and at this time, the transmission voltage of vg (n) is FW.
At time T4, the potential of ck (n) changes from high to low, at this time, the potential of the point Q changes back to the original high potential due to the capacitive coupling effect due to the existence of the capacitor C1, and T4 is still in an on state, and the transmission voltage of vg (n) is VGL (the voltage of ck (n) is VGL).
At time T5, Vg (n +4) is high, T9 and T10 are in the on state, and the potential at the point Q is discharged through this path. Since Ck (n +4) is high, T8 is turned on, and the point P is still maintained at VGL level, and the transistors T6, T7 and T11 controlled by point P are all in the off state.
At time T6, at this time, ck (n) changes from low to high, at this time, T3 is turned on, point P changes to high due to the turning on of T3, T6, T7, and T11 are in the on state, and discharge is respectively given to point Q and point vg (n), so that the output waveform of vg (n) is not distorted.
It should be further noted that there are many kinds of transistors, and in this embodiment, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, and T16 may be thin film transistors, MOS transistors (i.e., metal-oxide-semiconductor field effect transistors MOSFET), junction field effect transistors, and the like. Preferably, the T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, and T16 are Thin Film transistors (abbreviated TFTs), and the Thin Film transistors are used as switches to drive liquid crystal pixels, so that the characteristics of high speed, high brightness, and high contrast can be achieved. And the T1, the T2, the T3, the T4, the T5, the T6, the T7, the T8, the T9, the T10, the T11, the T12, the T13, the T14, the T15 and the T16 are arranged on the display panel.
In a preferred embodiment, the GIP circuit is disposed on an LCD Display panel, the LCD is a short for Liquid Crystal Display, and chinese is a Liquid Crystal Display. The LCD display panel has advantages of small size, low power consumption, and high brightness.
Alternatively, in some embodiments, the GIP circuit may be disposed on an OLED display panel, where the OLED is an Organic Light-Emitting Diode (OLED), and the chinese language is an Organic electroluminescent display or an Organic Light-Emitting semiconductor. The OLED display panel has the characteristics of lightness, thinness, high brightness, low power consumption, quick response, high definition, good flexibility, high luminous efficiency and the like, and can meet the new requirements of consumers on display technology.
Some embodiments also provide a GIP circuit driving method, including the steps of: at the stage t1, Vg (n-4) is written with high potential, CK (n) is written with low potential, CK (n +4) is written with high potential, Vg (n) is written with low potential, and Vg (n +4) is written with low potential; at the stage t2, Vg (n-4) is written with a low potential, CK (n +4) is written with a low potential, Vg (n) is written with a low potential, and Vg (n +4) is written with a low potential; at the stage t3, Vg (n-4) is written with low potential, CK (n) is written with high potential, CK (n +4) is written with low potential, Vg (n) is written with high potential, and Vg (n +4) is written with low potential; at the stage t4, Vg (n-4) is written with a low potential, CK (n +4) is written with a low potential, Vg (n) is written with a low potential, and Vg (n +4) is written with a low potential; at stage t5, Vg (n-4) writes a low potential, CK (n +4) writes a high potential and then writes a low potential, Vg (n) writes a low potential, and Vg (n +4) writes a high potential and then writes a low potential; at the stage t6, Vg (n-4) is written with a low potential, CK (n) is written with a high potential, CK (n +4) is written with a low potential, Vg (n) is written with a low potential, and Vg (n +4) is written with a low potential. During the period from t1 to t6, FW is continuously written with high potential, and VGL is continuously written with low potential.
At time T1, Vg (n-4) is high, at which time T1 and T2 are turned on, and charging is started at the Q point and the Qb point. At this time, CK (n +4) is high, T8 is on, Q is high, T5 is on, so P is pulled down to VGL through these paths. Since point Q is high, T4 is turned on, vg (n) is low (ck (n) is low).
At time T2, Vg (n-4) is low, at which time T1 and T2 are in an off state, and points Q and Qb remain in a drift state. Here, assuming that the threshold voltages of the transistors T6, T7, T9, T10, T12 and T13 are less than 0, T7, T10 and T13 are analyzed, Vgs of the transistors is 0, and leakage current is generated; for T6, T9, and T12, Vgs of these transistors is smaller than 0 (due to the node Qb), so that the voltage at the Q point does not drop due to the influence of leakage current, and the voltage at the Q point does not decay.
At time T3, the potential of ck (n) changes from low to high, and at this time, due to the existence of the capacitor C1, the potential at the point Q becomes higher due to the capacitive coupling effect, T4 is turned on, and the waveform transmission of vg (n) is better, and at this time, the transmission voltage of vg (n) is FW.
At time T4, the potential of ck (n) changes from high to low, at this time, the potential of the point Q changes back to the original high potential due to the capacitive coupling effect due to the existence of the capacitor C1, and T4 is still in an on state, and the transmission voltage of vg (n) is VGL (the voltage of ck (n) is VGL).
At time T5, Vg (n +4) is high, T9 and T10 are in the on state, and the potential at the point Q is discharged through this path. Since Ck (n +4) is high, T8 is turned on, and the point P is still maintained at VGL level, and the transistors T6, T7 and T11 controlled by point P are all in the off state.
At time T6, at this time, ck (n) changes from low to high, at this time, T3 is turned on, point P changes to high due to the turning on of T3, T6, T7, and T11 are in the on state, and discharge is respectively given to point Q and point vg (n), so that the output waveform of vg (n) is not distorted. According to the technical scheme, the potential of the point Q is improved, so that the potential drop caused by electric leakage due to negative bias of the threshold voltage of the transistor can not occur to the voltage of the point Q, the output waveform of the GIP can not be distorted, and the display effect of the display screen is optimized.
It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.

Claims (7)

1. A GIP circuit, comprising: t1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, and T16, further comprising a capacitance: c1;
the input end of the T1 is connected with FW, the output end of the T1 is connected with a node Qb, and the control end of the T1 is connected with Vg (n-4);
the input end of the T2 is connected with the Qb node, the output end of the T2 is connected with the Q node, and the control end of the T2 is connected with Vg (n-4);
the input end of the T3 is connected with CK (n), the output end of the T3 is connected with a P node, and the control end of the T3 is connected with CK (n);
the input end of the T4 is connected with CK (n), the output end of the T4 is connected with Vg (n), and the control end of the T4 is connected with a node Q;
the input end of the T5 is connected with a P node, the output end of the T5 is connected with VGL, and the control end of the T5 is connected with a Q node;
the input end of the T6 is connected with a node Q, the output end of the T6 is connected with a node Qb, and the control end of the T6 is connected with a node P;
the input end of the T7 is connected with the Qb node, the output end of the T7 is connected with VGL, and the control end of the T7 is connected with the P node;
the input end of the T8 is connected with a P node, the output end of the T8 is connected with VGL, and the control end of the T8 is connected with CK (n + 4);
the input end of the T9 is connected with a node Q, the output end of the T9 is connected with a node Qb, and the control end of the T9 is connected with Vg (n + 4);
the input end of the T10 is connected with the Qb node, the output end of the T10 is connected with the BW, and the control end of the T10 is connected with the Vg (n + 4);
the input end of the T11 is connected with Vg (n), the output end of the T11 is connected with VGL, and the control end of the T11 is connected with a P node;
the input end of the T12 is connected with a node Q, the output end of the T12 is connected with a node Qb, and the control end of the T12 is connected with a CLR;
the input end of the T13 is connected with the Qb node, the output end of the T13 is connected with VGL, and the control end of the T13 is connected with CLR;
the input end of the T14 is connected with Vg (n), the output end of the T14 is connected with VGL, and the control end of the T14 is connected with CLR;
the input end of the T15 is connected with a P node, the output end of the T15 is connected with VGL, and the control end of the T15 is connected with CLR;
the input end of the T16 is connected with Vg (n), the output end of the T16 is connected with VGL, and the control end of the T16 is connected with CK (n + 4);
one polar plate of the C1 is connected with the Q node, and the other polar plate of the C1 is connected with Vg (n).
2. The GIP circuit according to claim 1, wherein T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15 and T16 are all thin film transistors, and said T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15 and T16 are provided on the display panel.
3. The GIP circuit of claim 2, wherein said display panel is an LCD display panel.
4. The GIP circuit according to claim 1, further comprising a sub-pixel, Vg (n) connected to said sub-pixel.
5. The GIP circuit according to claim 1, further comprising a driver IC to which CK (n), CK (n +4), Vg (n-4) and Vg (n +4) are connected.
6. A GIP circuit driving method applied to the GIP circuit of any one of claims 1 to 5, comprising the steps of:
at the stage t1, Vg (n-4) is written with high potential, CK (n) is written with low potential, CK (n +4) is written with high potential, Vg (n) is written with low potential, and Vg (n +4) is written with low potential;
at the stage t2, Vg (n-4) is written with a low potential, CK (n +4) is written with a low potential, Vg (n) is written with a low potential, and Vg (n +4) is written with a low potential;
at the stage t3, Vg (n-4) is written with low potential, CK (n) is written with high potential, CK (n +4) is written with low potential, Vg (n) is written with high potential, and Vg (n +4) is written with low potential;
at the stage t4, Vg (n-4) is written with a low potential, CK (n +4) is written with a low potential, Vg (n) is written with a low potential, and Vg (n +4) is written with a low potential;
at stage t5, Vg (n-4) writes a low potential, CK (n +4) writes a high potential and then writes a low potential, Vg (n) writes a low potential, and Vg (n +4) writes a high potential and then writes a low potential;
at the stage t6, Vg (n-4) is written with a low potential, CK (n) is written with a high potential, CK (n +4) is written with a low potential, Vg (n) is written with a low potential, and Vg (n +4) is written with a low potential.
7. The GIP circuit driving method as claimed in claim 6, wherein FW is continuously written with high potential and VGL is continuously written with low potential during the period from t1 to t 6.
CN202110034773.1A 2021-01-12 2021-01-12 GIP circuit and driving method thereof Pending CN112735350A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113611254A (en) * 2021-08-04 2021-11-05 福建华佳彩有限公司 GIP circuit for solving abnormal picture of display screen and driving method thereof
CN114170989A (en) * 2022-01-11 2022-03-11 福建华佳彩有限公司 GIP circuit for improving stability of display screen and driving method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113611254A (en) * 2021-08-04 2021-11-05 福建华佳彩有限公司 GIP circuit for solving abnormal picture of display screen and driving method thereof
CN114170989A (en) * 2022-01-11 2022-03-11 福建华佳彩有限公司 GIP circuit for improving stability of display screen and driving method thereof

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