CN213716481U

CN213716481U - GIP circuit

Info

Publication number: CN213716481U
Application number: CN202022779958.9U
Authority: CN
Inventors: 谢建峰; 熊克
Original assignee: Fujian Huajiacai Co Ltd
Current assignee: Fujian Huajiacai Co Ltd
Priority date: 2020-11-26
Filing date: 2020-11-26
Publication date: 2021-07-16
Anticipated expiration: 2030-11-26

Abstract

The utility model discloses a GIP circuit, including transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor T8, transistor T9, transistor T10 and electric capacity; the drain electrode of the transistor T1 is connected FW, and the transistor T1 is connected with the transistor T2; the transistor T2 is connected with the transistor T5, the transistor T4, the transistor T8 and the transistor T6; the transistor T4 is connected with Vg (n) and the transistor T7; the transistor T5 is connected with the transistor T9; the transistor T8 is connected with the transistor T10; transistor T5, transistor T8, and transistor T10 are connected BW. According to the technical scheme, the voltage of the node Q1 is controlled, so that the leakage of the transistor T6 and the leakage of the transistor T8 do not occur, the leakage path of the node Q is eliminated, the leakage of the node Q is avoided, and the output waveform at Vg (n) is not distorted. The display quality of the display screen can be improved, and the appearance of the display screen is improved.

Description

GIP circuit

Technical Field

The utility model relates to a show technical field, especially relate to a GIP circuit.

Background

GIP (Gate in Panel) refers to a Gate circuit on a substrate. The output waveform of the GIP circuit is susceptible to leakage of a transistor (especially, a depletion transistor), thereby causing a situation where the output waveform of the GIP circuit is distorted. The distorted output waveform can cause problems in turning on and off transistors in a display area in the display screen, thereby causing display abnormalities in the display screen.

SUMMERY OF THE UTILITY MODEL

Therefore, it is desirable to provide a GIP circuit and a driving method, which solve the problem that the output waveform of the GIP circuit is susceptible to the leakage of the transistor.

To achieve the above object, the present embodiment provides a GIP circuit including a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a transistor T10, and a capacitor;

the gate of the transistor T1 is connected to Vg (n-4), the drain of the transistor T1 is connected to FW, and the source of the transistor T1 is connected to the drain of the transistor T2;

the gate of the transistor T2 is connected with Vg (n-4), and the source of the transistor T2 is connected with the gate of the transistor T5;

the gate of the transistor T4 is connected to the source of the transistor T2, the drain of the transistor T4 is connected to CKn, and the source of the transistor T4 is connected to Vg (n);

the first plate of the capacitor is connected with the gate of the transistor T4, and the first plate of the capacitor is connected with the source of the transistor T4;

a drain of the transistor T3 is connected to FW, a gate of the transistor T3 is connected to FW or CK (n +5), and a source of the transistor T3 is connected to a drain of the transistor T5, a gate of the transistor T6, a gate of the transistor T7, and a gate of the transistor T9;

the source connection BW of the transistor T5;

the drain of the transistor T6 is connected to the gate of the transistor T4, the source of the transistor T6 is connected to the drain of the transistor T9;

the source connection BW of the transistor T9;

the drain of the transistor T7 is connected to the line between the source of the transistor T4 and vg (n), and the source of the transistor T7 is connected BW;

the gate of the transistor T8 and the gate of the transistor T10 are connected Vg (n +4), the drain of the transistor T8 is connected to the line between the gate of the transistor T4 and the source of the transistor T2, the source of the transistor T8 is connected to the drain of the transistor T10, and the source of the transistor T10 is connected BW.

Further, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, and the transistor T10 are all depletion type transistors.

Further, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, and the transistor T10 are all thin film transistors.

Further, the GIP circuit is disposed on the display panel.

Further, the display panel is an LCD display panel.

Different from the prior art, the above technical solution enables neither the transistor T6 nor the transistor T8 to leak electricity by controlling the voltage of the node Q1, so that the node Q has no leakage path, the node Q has no leakage electricity, and the output waveform at vg (n) is not distorted. The application provides a realize high definition's display screen's solution, can improve the display quality of display screen, promotes the impression of display screen, and then improves the competitiveness of display screen.

Drawings

FIG. 1 is a schematic diagram of the GIP circuit according to one embodiment;

FIG. 2 is a timing diagram of the GIP circuit according to one embodiment;

FIG. 3 is a schematic diagram of the GIP circuit according to the second embodiment;

fig. 4 is a timing diagram of the GIP circuit according to the second embodiment.

Detailed Description

To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.

Referring to fig. 1 to 4, a GIP circuit of the present embodiment includes a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a transistor T10, and a capacitor;

the gate of the transistor T2 is connected to Vg (n-4), and the source of the transistor T2 is connected to the gate of the transistor T5. The gate of the transistor T4 is connected to the source of the transistor T2, the drain of the transistor T4 is connected to CKn, and the source of the transistor T4 is connected to Vg (n);

the source connection BW of the transistor T5;

the source connection BW of the transistor T9;

A Q node, a Q1 node and a Qb node are arranged on the line. The Q-node is disposed between the source of the transistor T2 and the gate of the transistor T5, and is also disposed between the source of the transistor T2 and the gate of the transistor T4. For the Q-node, the transistors pulling up the voltage of the Q-node are a transistor T1, a transistor T2, a transistor T3, and a transistor T4, and the transistors pulling down the voltage are a transistor T6, a transistor T8, a transistor T9, a transistor T10, and a transistor T7.

According to the technical scheme, the voltage of the node Q1 is controlled, so that the leakage of the transistor T6 and the leakage of the transistor T8 do not occur, the leakage path of the node Q is eliminated, the leakage of the node Q is avoided, and the output waveform at Vg (n) is not distorted. The application provides a realize high definition's display screen's solution, can improve the display quality of display screen, promotes the impression of display screen, and then improves the competitiveness of display screen.

Note that FW is written in a dc high voltage, and may be set to any value such as 15V, 14V, or 13V, specifically subject to the requirements of an actual circuit. The BW is written by direct current low voltage which can be set to-10V, -9V, -8V and the like, and the requirements of an actual circuit are specifically taken as the standard.

Note that CKn refers to a clock signal. The value of the high potential of CKn or another data line corresponds to the value of FW potential, and the value of the low potential of CKn or another data line corresponds to the value of BW potential.

It should be noted that there are a plurality of such GIP circuits in the display panel, each GIP circuit is connected with a plurality of gate lines, and the gate lines generally run parallel to the row direction. For example, the GIP circuit shown in the present application is connected to gate line g (n), gate line g (n +4), and gate line g (n-4). The other gate lines are connected to another GIP circuit. In vg (n), g (n) in vg (n) refers to the gate line of the nth row, vg (n) indicates the electrical signal on the gate line of the nth row, g (n +1) refers to the gate line of the n +1 th row, g (n +2) refers to the gate line of the n +2 th row, g (n +3) refers to the gate line of the n +3 th row, and g (n +4) refers to the gate line of the n +4 th row. Alternatively, g (n +1) and g (n) may not be adjacent to each other.

The above-mentioned "gate connection FW or CK (n +5) of the transistor T3" means a method in which the gate of the transistor T3 is connected in two ways. In the first embodiment, the specific structure of the gate connection FW of the transistor T3 is shown in fig. 1, and the timing chart is shown in fig. 2. In the second embodiment, the gate of the transistor T3 is connected to CK (n +5), the specific structure is as shown in fig. 3, and the timing chart is as shown in fig. 4.

Since the depletion type transistor is susceptible to leakage and further causes abnormality in the output waveform of the GIP circuit, in the preferred embodiment, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, and the transistor T10 are all depletion type transistors.

The transistors are various, and the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, and the transistor T10 may be thin film transistors, MOS transistors (i.e., metal-oxide-semiconductor field effect transistors, MOSFETs), junction field effect transistors, or the like.

Preferably, the Transistor T1, the Transistor T2, the Transistor T3, the Transistor T4, the Transistor T5, the Transistor T6, the Transistor T7, the Transistor T8, the Transistor T9, and the Transistor T10 are all Thin Film transistors (abbreviated as TFTs), and the Thin Film transistors are used as switches to drive liquid crystal pixels, so that the characteristics of high speed, high brightness, and high contrast can be achieved.

In a preferred embodiment, the GIP circuit is disposed on an LCD Display panel, the LCD is a short for Liquid Crystal Display, and chinese is a Liquid Crystal Display. The LCD display panel has advantages of small size, low power consumption, and high brightness.

Or in some embodiments, the GIP circuit may be disposed on an OLED display panel, where the OLED is an organic light-Emitting Diode, and the chinese language is an organic electroluminescent display or an organic light-Emitting semiconductor. The OLED display panel has the characteristics of lightness, thinness, high brightness, low power consumption, quick response, high definition, good flexibility, high luminous efficiency and the like, and can meet the new requirements of consumers on display technology.

Referring to fig. 1 and fig. 2, in the first embodiment, the gate of the transistor T3 is connected to FW, and a specific principle is described in conjunction with a GIP circuit driving method based on the GIP circuit:

at the stage t1, FW writes a high potential, BW writes a low potential, Vg (n-4) writes a high potential, Vg (n) writes a low potential, Vg (n +4) writes a low potential, CKn writes a low potential;

at the stage t2, FW writes high potential, BW writes low potential, Vg (n-4) writes low potential, Vg (n) writes high potential, Vg (n +4) writes low potential, CKn writes high potential;

at the stage t3, FW, BW, Vg (n-4), Vg (n) (4), Vg (n) and CKn are respectively written with high, low, high and low potentials, respectively.

Specifically, since FW is always high, the transistor T3 is always in an on state.

During the period T1, Vg (n-4) is high, and the transistor T1 and the transistor T2 are turned on. The Q-node and the Q1-node are charged to a high potential (the value of which approaches the potential value of FW), and the rise of the Q-node potential causes the transistor T4 and the transistor T5 to be turned on, respectively. The transistor T4 is turned on, when CKn is low (see waveform Vg (n) in fig. 2), the voltage at node Vg (n) is low (the value of the low potential approaches the value of BW), the Qb node is pulled to low (the value of the low potential approaches the value of BW), the transistor T6, the transistor T7 and the transistor T9 are turned off, Vg (n +4) is in a low voltage state, and the transistor T8 and the transistor T10 are turned off.

At the stage T2, when Vg (n) is changed from low to high and Vg (n-4) is low, the transistors T1 and T2 are turned off, and the Q node is in floating state. The potential at the point vg (n) is low, and BW becomes high (the value of the high potential is close to the value of FW). Because of the coupling effect of the capacitor, the voltage at the Q-node changes again from the high potential with the original value FW to the high potential with the value FW + FW, at which time the on-state of the transistor T4 is stable, CKn preferably transfers the output waveform to vg (n).

At the stage t3, CKn is at a low potential, and the high potential of the Q node is reduced from FW + FW to FW due to the coupling effect of the capacitor. When Vg (n +4) changes from a low voltage (the value of the low voltage approaches the value of BW potential) to a high voltage FW (the value of the high voltage approaches the value of FW potential), the transistor T8 and the transistor T10 turn on, and the corresponding Q node and Q1 node are pulled directly to a low potential (the value of the low potential approaches the value of BW potential). Since the transistor T3 is in the normally-on state, the Qb node is charged to the high FW potential, the transistor T6 and the transistor T9 are turned on, and the corresponding Q node and the Q1 node are pulled to the low potential (the value of the low potential approaches the value of BW potential), at which the transistor T5 and the transistor T4 are turned off.

During the entire Vg (n) waveform generation process, the Q1 node is always at a higher potential state, and the Qb node and the Vg (n +4) node are always at a low potential state. Vgs of both the transistor T6 and the transistor T8 is negative. Although the voltages at the Q1 node also drop later, the gate-source voltages Vgs of the transistors T6 and T8 are relatively low at time T2, when Vgs of the transistors T6 and T8 is BW-FW-10V-15V-25V. According to the Ids-Vgs curve of the transistor, the leakage of the transistor at Vgs in this range is small, so the leakage of the transistor T6 and the transistor T8 is negligible, and both can be considered as no leakage generation. Because the transistor T6 and the transistor T8 do not leak electricity, the potential of the Q node becomes stable, the transistor T4 is turned on better, the waveform that CKn transmits to vg (n) is not distorted, the waveform of vg (n) is not distorted, and the transistor that controls the display area of the display screen can be turned on better by vg (n).

Referring to fig. 3 and 4, in the second embodiment, i.e. the gate of the transistor T3 is connected to CK (n +5), the drain of the transistor T3 is connected to FW, and the remaining structure is not changed, on the basis of the above GIP circuit, the detailed principle is described in conjunction with the GIP circuit driving method:

due to the characteristics of the transistor, when the transistor is in a state for a long time, such as the transistor T3 is in a normally-on state in the first embodiment, the insulating layer over the gate of the transistor has defects (which may be defective if any material). The gate voltage FW is always high, which attracts carrier electrons in the channel of the transistor into the insulating layer, causing the threshold voltage Vth of the transistor T3 to shift. The Vth shift of the transistor T3 will cause the Qb node voltage to be unstable, which will affect the discharging (from high to low) process of the Qb node. In the second embodiment, the on-voltage signal of the transistor T3 is changed to be a CK type, that is, the on-signal which is always at a high level is changed to be a periodic CK signal, so that the transistor T3 is not always in an on state, but the transistor T6 and the transistor T8 can be controlled not to leak electricity, and the waveform of CKn transmitted to vg (n) is still not distorted.

In the second embodiment, the driving waveforms at the t1 stage, the t2 stage and the t3 stage are respectively consistent with the driving waveforms at the t1 stage, the t2 stage and the t3 stage in the first embodiment, and the voltage change processes at the t1 stage, the t2 stage and the t3 stage in the second embodiment are respectively consistent with the voltage change processes at the t1 stage, the t2 stage and the t3 stage in the first embodiment.

In fig. 4, at the stage T4, CK (n +5) (see Vg (n +5) waveform in fig. 4) changes from low to high, the transistor T3 is turned on, and the Qb node is charged to high (the value of the high approaches that of FW).

It should be noted that, although the above embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, the changes and modifications of the embodiments described herein, or the equivalent structure or equivalent process changes made by the contents of the specification and the drawings of the present invention, directly or indirectly apply the above technical solutions to other related technical fields, all included in the scope of the present invention.

Claims

1. A GIP circuit, comprising a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a transistor T10, and a capacitor;

the source connection BW of the transistor T5;

the source connection BW of the transistor T9;

2. The GIP circuit according to claim 1, wherein the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9 and the transistor T10 are all depletion type transistors.

3. A GIP circuit according to claim 1 or 2, wherein the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9 and the transistor T10 are all thin film transistors.

4. The GIP circuit according to claim 1, wherein the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9 and the transistor T10 are all thin film transistors provided on a display panel.

5. The GIP circuit according to claim 4, wherein said display panel is an LCD display panel.