CN214012479U - Gate circuit for improving display quality - Google Patents
Gate circuit for improving display quality Download PDFInfo
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- CN214012479U CN214012479U CN202023004023.XU CN202023004023U CN214012479U CN 214012479 U CN214012479 U CN 214012479U CN 202023004023 U CN202023004023 U CN 202023004023U CN 214012479 U CN214012479 U CN 214012479U
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Abstract
The utility model provides an promote gate circuit of display quality, including transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor T8, transistor T9, electric capacity C1 and electric capacity C2. The technical scheme enables the transistor T5 and the transistor T7 not to generate electric leakage by controlling the voltage of the node Q'. The Q node has no leakage path, no leakage occurs at the Q node, and the output waveform of the gate line g (n) is not distorted. The application provides a display panel's that realizes high definition solution, can improve display panel's display quality, promotes display panel's impression, and then improves display panel's competitiveness.
Description
Technical Field
The utility model relates to a show technical field, especially relate to a promote grid circuit who shows quality.
Background
In recent years, the display panel has been diversified, and the display panel is developed toward light weight, thinness, low power consumption and low cost due to diversified applications and customer demands of the product. Among them, low cost and low power consumption are relatively important issues,
in order to reduce the manufacturing cost of the display Panel and achieve the purpose of narrow bezel, a Gate In Panel (GIP) technology is usually adopted in the manufacturing process, and a Gate circuit (i.e., GIP circuit) is directly integrated on the flat Panel display Panel. The output waveform of the GIP circuit is susceptible to leakage of the transistor, resulting in a situation where the output waveform of the GIP circuit is distorted. The distorted output waveform may cause problems in turning on and off transistors in a display area within the display panel, thereby causing display anomalies in the display panel.
SUMMERY OF THE UTILITY MODEL
Therefore, it is desirable to provide a gate circuit for improving display quality, so as to solve the problem that the output waveform of the gate circuit is susceptible to the leakage of the transistor.
In order to achieve the above object, the present embodiment provides a gate circuit and a driving method for improving display quality, including a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a capacitor C1, and a capacitor C2;
the control end of the transistor T1 is connected with a gate signal Vg (n-4), the input end of the transistor T1 is connected with a voltage signal FW, the output end of the transistor T1 is respectively connected with the control end of the transistor T3, the control end of the transistor T4 and the input end of the transistor T7, and a first node is arranged on a line connecting the output end of the transistor T1 and the control end of the transistor T4;
the control terminal of the transistor T2 is connected to the first node, the input terminal of the transistor T2 is connected to the voltage signal FW, and the output terminal of the transistor T2 is connected to the input terminal of the transistor T8;
the input end of the transistor T3 is connected with the first plate of the capacitor C2, the second plate of the capacitor C2 is connected with the clock signal CKn, and the output end of the transistor T3 is connected with the voltage signal VGL;
the input end of the transistor T4 is connected with the clock signal CKn, and the output end of the transistor T4 is respectively connected with the gate signal Vg (n) and the input end of the transistor T6;
the first plate of the capacitor C1 is connected with the control end of the transistor T4, and the second plate of the capacitor C1 is connected with the output end of the transistor T4;
a second node is arranged on a line connecting the input end of the transistor T3 and the first plate of the capacitor C2, the control end of the transistor T5 is connected with the second node, the input end of the transistor T5 is connected with the first node, and the output end of the transistor T5 is connected with the input end of the transistor T8;
the control end of the transistor T6 is connected with the second node, and the output end of the transistor T6 is connected with a voltage signal VGL;
the control end of the transistor T7 is connected with a gate signal Vg (n +4), the input end of the transistor T7 is connected with a line connecting the first node and the control end of the transistor T4, the output end of the transistor T7 is connected with the input end of the transistor T9, and the output end of the transistor T2 is also connected with a line connecting the output end of the transistor T7 and the input end of the transistor T9;
the control end of the transistor T8 is connected with the second node, and the output end of the transistor T8 is connected with a voltage signal VGL;
the control end of the transistor T9 is connected to the gate signal Vg (n +4), and the output end of the transistor T9 is connected to the voltage signal VGL.
Further, an input terminal of the transistor T1, an input terminal of the transistor T2, an input terminal of the transistor T3, an input terminal of the transistor T4, an input terminal of the transistor T5, an input terminal of the transistor T6, an input terminal of the transistor T7, an input terminal of the transistor T8, and an input terminal of the transistor T9 are all drains.
Further, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, and the transistor T9 are all thin film transistors.
Further, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, the capacitor C1, and the capacitor C2 are all disposed on the display panel.
Further, the display panel is an LCD display panel.
Different from the prior art, the technical scheme enables the transistor T5 and the transistor T7 not to leak electricity by controlling the voltage of the node Q'. The Q node has no leakage path, no leakage occurs at the Q node, and the output waveform of the gate line g (n) is not distorted. The application provides a display panel's that realizes high definition solution, can improve display panel's display quality, promotes display panel's impression, and then improves display panel's competitiveness.
Drawings
Fig. 1 is a schematic structural diagram of a gate circuit according to the present embodiment;
fig. 2 is a timing diagram of the gate circuit according to the present embodiment.
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 1 to 2, the present embodiment provides a gate circuit for improving display quality, which includes a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a capacitor C1, and a capacitor C2. The control terminal of the transistor T1 is connected with a gate signal Vg (n-4), the input terminal of the transistor T1 is connected with a voltage signal FW, and the output terminal of the transistor T1 is connected with the control terminal of the transistor T3, the control terminal of the transistor T4 and the input terminal of the transistor T7 respectively. A first node is provided on a line connecting the output terminal of the transistor T1 and the control terminal of the transistor T4, and the first node may serve as a connection point of another transistor. The control terminal of the transistor T2 is connected to the first node, the input terminal of the transistor T2 is connected to the voltage signal FW, and the output terminal of the transistor T2 is connected to the input terminal of the transistor T8. The input end of the transistor T3 is connected to the first plate of the capacitor C2, the second plate of the capacitor C2 is connected to the clock signal CKn, and the output end of the transistor T3 is connected to the voltage signal VGL. The input terminal of the transistor T4 is connected to the clock signal CKn, and the output terminal of the transistor T4 is connected to the gate signal vg (n) and the input terminal of the transistor T6, respectively. The first plate of the capacitor C1 is connected to the control terminal of the transistor T4, and the second plate of the capacitor C1 is connected to the output terminal of the transistor T4. A second node is provided on a line connecting the input terminal of the transistor T3 and the first plate of the capacitor C2, and the second node may serve as a connection point for other transistors. The control terminal of the transistor T5 is connected to the second node, the input terminal of the transistor T5 is connected to the first node, and the output terminal of the transistor T5 is connected to the input terminal of the transistor T8. The control terminal of the transistor T6 is connected to the second node, and the output terminal of the transistor T6 is connected to the voltage signal VGL. The control terminal of the transistor T7 is connected to the gate signal Vg (n +4), the input terminal of the transistor T7 is connected to the line connecting the first node and the control terminal of the transistor T4, and the output terminal of the transistor T7 is connected to the input terminal of the transistor T9. The output terminal of the transistor T2 is also connected to the line connecting the output terminal of the transistor T7 and the input terminal of the transistor T9. The control terminal of the transistor T8 is connected to the second node, and the output terminal of the transistor T8 is connected to the voltage signal VGL. The control end of the transistor T9 is connected to the gate signal Vg (n +4), and the output end of the transistor T9 is connected to the voltage signal VGL.
The transistor T1 and the transistor T4 pull up the voltage of the Q node, and the transistor T5, the transistor T6, the transistor T7, the transistor T8, and the transistor T9 pull down the voltage of the Q node. The technical scheme enables the transistor T5 and the transistor T7 not to generate electric leakage by controlling the voltage of the node Q'. The Q node has no leakage path, no leakage occurs at the Q node, and the output waveform of the gate line g (n) is not distorted. The application provides a display panel's that realizes high definition solution, can improve display panel's display quality, promotes display panel's impression, and then improves display panel's competitiveness.
In this embodiment, the input terminal of the transistor T1, the input terminal of the transistor T2, the input terminal of the transistor T3, the input terminal of the transistor T4, the input terminal of the transistor T5, the input terminal of the transistor T6, the input terminal of the transistor T7, the input terminal of the transistor T8, and the input terminal of the transistor T9 are all drains. An output terminal of the transistor T1, an output terminal of the transistor T2, an output terminal of the transistor T3, an output terminal of the transistor T4, an output terminal of the transistor T5, an output terminal of the transistor T6, an output terminal of the transistor T7, an output terminal of the transistor T8, and an output terminal of the transistor T9 are all sources. A control terminal of the transistor T1, a control terminal of the transistor T2, a control terminal of the transistor T3, a control terminal of the transistor T4, a control terminal of the transistor T5, a control terminal of the transistor T6, a control terminal of the transistor T7, a control terminal of the transistor T8, or a control terminal of the transistor T9 are all gates.
In this embodiment, as a Transistor which can be used in the present application, a Thin Film Transistor (TFT) is used, a MOS Transistor (i.e., a metal-oxide-semiconductor field effect Transistor (MOSFET) is used), a junction field effect Transistor, or the like. Preferably, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, and the transistor T9 are all thin film transistors. The thin film transistor is used as a switch to drive the liquid crystal pixel point, and the characteristics of high speed, high brightness and high contrast can be achieved.
In this embodiment, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, the capacitor C1, and the capacitor C2 are all disposed on a display panel. The Display panel is an LCD Display panel, the LCD is short for Liquid Crystal Display, and Chinese is a Liquid Crystal Display. The LCD display panel has advantages of small size, low power consumption, and high brightness.
Or in some embodiments, the GIP circuit may be disposed on an OLED display panel, where the OLED is an Organic Light-Emitting Diode, and the chinese language is an Organic electroluminescent display or an Organic Light-Emitting semiconductor. The OLED display panel has the characteristics of lightness, thinness, high brightness, low power consumption, quick response, high definition, good flexibility, high luminous efficiency and the like, and can meet the new requirements of consumers on display technology.
It should be noted that vg (n) represents the voltage on gate line g (n). There are a plurality of GIP circuits in the display panel, each GIP circuit is connected to one sub-pixel through a gate line g (n) to realize driving to the sub-pixel, and each GIP circuit is connected to a driving ic through a gate line g (n +4) and a gate line g (n-4) so that the driving ic drives the sub-pixel through the GIP circuit. The plurality of sub-pixels are arranged on the display panel in an array mode, and one side of each sub-pixel is provided with a GIP circuit.
Referring to fig. 1 and fig. 2, the present embodiment further provides a gate circuit driving method for improving display quality, which is applied to the gate circuit for improving display quality according to any one of the above embodiments, and the method includes the following steps: at stage t1, the voltage signal FW is written with high potential, the voltage signal VGL is written with low potential, the gate signal Vg (n-4) is written with high potential, and the clock signal CKn is written with low potential; at stage t2, the voltage signal FW is written with high potential, the voltage signal VGL is written with low potential, the gate signal vg (n) is written with high potential, and the clock signal CKn is written with high potential; at a stage t3, the voltage signal FW is written at a high potential, the voltage signal VGL is written at a low potential, the gate signal Vg (n +4) is written at a high potential, and the clock signal CKn is written at a low potential.
The voltage signal FW is a high dc voltage and may be set to a value of 15V, 14V, 13V, or the like, and specifically, the potential value of the voltage signal FW is set to H here based on the actual circuit requirement. The voltage signal VGL is a dc low voltage, and can be set to a value of-10V, -9V, -8V, etc., specifically based on the requirement of the actual circuit, where the potential value of the voltage signal VGL is set to L.
At the stage T1, the gate signal Vg (n-4) is at a high level, and at this time, the transistor T1, the transistor T2, the transistor T3 and the transistor T4 are turned on, and the Q node and the Q' node are charged to a high level (the high level has a value H, H >0), respectively. The potential of the Q node rises and the transistor T3 and the transistor T4 turn on. Since the transistor T4 is turned on, the clock signal CKn is at a low potential at this time, referring to the waveform of the gate signal vg (n) in fig. 2, the voltage at the node of the gate signal vg (n) is at a low potential (the value of the low potential is L, and L <0), so that the value of the voltage at the node Qb is the same as the value of the voltage signal VGL. At this time, the transistor T5 and the transistor T8 are turned off, the gate signal Vg (n +4) is at a low voltage, and the transistor T7 and the transistor T9 are turned off.
At stage t2, when CKn corresponding to gate signal vg (n) changes from low to high, refer to the waveform of gate signal vg (n) in fig. 2. When the gate signal Vg (n-4) is at a low potential, the transistor T1 is turned off, the Q node is in a floating state, and the potential of the gate signal Vg (n) node changes from a low potential (the low potential is L) to a high potential (the high potential is H). Due to the coupling effect of the capacitor C1, the potential value of the Q node changes from H to 2H, and at this time, the transistor T4 is stable, and the clock signal CKn can better transfer the output waveform to the gate signal vg (n).
During the generation of the whole Vg (n) waveform, when the Q node is in a high state, the Q' node is always in a high state, the Qb node and the gate signal Vg (n +4) are always in a low state, and the gate-source voltage Vgs of the transistor T5 and the transistor T7 is a negative value. For example, the voltage signal FW is set to 15V, the voltage signal VGL may be set to-10V, and the gate-source voltages Vgs of the transistor T5 and the transistor T7 are-10V-15V-25V. The TFT leakage in this range for Vgs is extremely small according to the Ids-Vgs curve of the transistor, so the transistors T5 and T7 of the present application can appear to be leakage free. Since no leakage occurs to the transistor T5 and the transistor T7, the potential of the Q node becomes stable, and the state of the transistor T4 is also stable. The output waveform transmitted by CKn to the gate lines g (n) is not distorted, and the output waveform is not distorted, so that the transistors at the display area of the display panel can be controlled to be turned on or turned off.
At the time t3, the clock signal CKn is low, and the voltage level at the node Q decreases from 2H to H due to the coupling effect of the capacitor C1. When the gate signal Vg (n +4) changes from L to H, the transistor T7 and the transistor T9 turn on, the values of the corresponding Q node and Q' node are pulled to L, the transistor T3 turns off, and therefore the low level value of the Qb node is L, and the transistor T5 and the transistor T8 turn off.
It should be noted that two of the t1 phase, t2 phase and t3 phase may be continuous or discontinuous. For example, in FIG. 2, there are intervals between the t1 phase, the t2 phase and the t3 phase.
It should be noted that, although the above embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, the changes and modifications of the embodiments described herein, or the equivalent structure or equivalent process changes made by the contents of the specification and the drawings of the present invention, directly or indirectly apply the above technical solutions to other related technical fields, all included in the scope of the present invention.
Claims (5)
1. A gate circuit for improving display quality comprises a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a capacitor C1 and a capacitor C2;
the control end of the transistor T1 is connected with a gate signal Vg (n-4), the input end of the transistor T1 is connected with a voltage signal FW, the output end of the transistor T1 is respectively connected with the control end of the transistor T3, the control end of the transistor T4 and the input end of the transistor T7, and a first node is arranged on a line connecting the output end of the transistor T1 and the control end of the transistor T4;
the control terminal of the transistor T2 is connected to the first node, the input terminal of the transistor T2 is connected to the voltage signal FW, and the output terminal of the transistor T2 is connected to the input terminal of the transistor T8;
the input end of the transistor T3 is connected with the first plate of the capacitor C2, the second plate of the capacitor C2 is connected with the clock signal CKn, and the output end of the transistor T3 is connected with the voltage signal VGL;
the input end of the transistor T4 is connected with the clock signal CKn, and the output end of the transistor T4 is respectively connected with the gate signal Vg (n) and the input end of the transistor T6;
the first plate of the capacitor C1 is connected with the control end of the transistor T4, and the second plate of the capacitor C1 is connected with the output end of the transistor T4;
a second node is arranged on a line connecting the input end of the transistor T3 and the first plate of the capacitor C2, the control end of the transistor T5 is connected with the second node, the input end of the transistor T5 is connected with the first node, and the output end of the transistor T5 is connected with the input end of the transistor T8;
the control end of the transistor T6 is connected with the second node, and the output end of the transistor T6 is connected with a voltage signal VGL;
the control end of the transistor T7 is connected with a gate signal Vg (n +4), the input end of the transistor T7 is connected with a line connecting the first node and the control end of the transistor T4, the output end of the transistor T7 is connected with the input end of the transistor T9, and the output end of the transistor T2 is also connected with a line connecting the output end of the transistor T7 and the input end of the transistor T9;
the control end of the transistor T8 is connected with the second node, and the output end of the transistor T8 is connected with a voltage signal VGL;
the control end of the transistor T9 is connected to the gate signal Vg (n +4), and the output end of the transistor T9 is connected to the voltage signal VGL.
2. The gate circuit of claim 1, wherein the input terminal of the transistor T1, the input terminal of the transistor T2, the input terminal of the transistor T3, the input terminal of the transistor T4, the input terminal of the transistor T5, the input terminal of the transistor T6, the input terminal of the transistor T7, the input terminal of the transistor T8 and the input terminal of the transistor T9 are all drains.
3. The gate circuit of claim 1, wherein the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, and the transistor T9 are all thin film transistors.
4. The gate circuit according to claim 1, wherein the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, the capacitor C1, and the capacitor C2 are disposed on a display panel.
5. The gate circuit of claim 4, wherein the display panel is an LCD display panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023004023.XU CN214012479U (en) | 2020-12-14 | 2020-12-14 | Gate circuit for improving display quality |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202023004023.XU CN214012479U (en) | 2020-12-14 | 2020-12-14 | Gate circuit for improving display quality |
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| CN214012479U true CN214012479U (en) | 2021-08-20 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112530348A (en) * | 2020-12-14 | 2021-03-19 | 福建华佳彩有限公司 | Grid circuit for improving display quality and driving method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112530348A (en) * | 2020-12-14 | 2021-03-19 | 福建华佳彩有限公司 | Grid circuit for improving display quality and driving method |
| CN112530348B (en) * | 2020-12-14 | 2024-01-16 | 福建华佳彩有限公司 | Gate circuit for improving display quality and driving method |
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