TW201532014A - Shift control cell - Google Patents
Shift control cell Download PDFInfo
- Publication number
- TW201532014A TW201532014A TW103104075A TW103104075A TW201532014A TW 201532014 A TW201532014 A TW 201532014A TW 103104075 A TW103104075 A TW 103104075A TW 103104075 A TW103104075 A TW 103104075A TW 201532014 A TW201532014 A TW 201532014A
- Authority
- TW
- Taiwan
- Prior art keywords
- transistor
- coupled
- control unit
- type mos
- clock signal
- Prior art date
Links
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Shift Register Type Memory (AREA)
- Electroluminescent Light Sources (AREA)
- Led Devices (AREA)
Abstract
Description
本發明提供一種位移控制單元，尤指一種用於有機發光二極體(Organic Light Emitting Diode，OLED)顯示裝置中之可調整發光脈波寬度的位移控制單元。 The present invention provides a displacement control unit, and more particularly to a displacement control unit for adjusting an illumination pulse width in an Organic Light Emitting Diode (OLED) display device.
有機發光二極體顯示裝置(Organic Light Emitting Diode，OLED)擁有高亮度、反應速度快、輕薄短小、廣色域、高對比、視野範圍廣、不需要液晶顯示裝置之背光源以及低耗電量等優點，逐漸成為新一代可攜式資訊產品及筆記型電腦普遍使用之顯示裝置，然而，其需要設計適當的閘級驅動電路以保證其穩定工作與顯示品質。 Organic Light Emitting Diode (OLED) has high brightness, fast response, light and short, wide color gamut, high contrast, wide field of view, no need for backlight of liquid crystal display device, and low power consumption. Such advantages have gradually become the display device commonly used in the new generation of portable information products and notebook computers. However, it is necessary to design an appropriate gate drive circuit to ensure stable operation and display quality.
一般來說，有機發光二極體顯示裝置中之閘級驅動電路會產生複數個發光脈波訊號及複數個掃描訊號來控制複數個OLED像素的灰階表現及發光時間，而閘級驅動電路係以複數級的移位暫存器做為重要的核心電路，每一級的移位暫存器包含位移控制單元，位移控制單元包含複數個薄膜電晶體(Thin Film Transistor，TFT)開關以及複數個電容。而移位暫存器也是除了畫面像素電路之外，在面板內部最重要且最多的數位電路。因此，移位暫存器在電路架構設計上，除了基本功能要能夠正常工作外，其內部的位移控制單元也必需考量功率消耗，製成容忍度及佈局面積等相關問題。 Generally, the gate driving circuit in the organic light emitting diode display device generates a plurality of light emitting pulse signals and a plurality of scanning signals to control the gray scale performance and the light emitting time of the plurality of OLED pixels, and the gate driving circuit is The multi-level shift register is regarded as an important core circuit. Each stage of the shift register includes a displacement control unit. The displacement control unit includes a plurality of Thin Film Transistor (TFT) switches and a plurality of capacitors. . The shift register is also the most important and most digital circuit inside the panel except the picture pixel circuit. Therefore, in the circuit architecture design, in addition to the basic functions to be able to work normally, the internal displacement control unit must also consider the power consumption, and make related problems such as tolerance and layout area.
然而，習知的位移控制單元由於電晶體特性，常常在高低電位之間存在漏電路徑而導致閘級驅動電路輸出之發光脈波訊號及掃描訊號失真而影響顯示器影像品質。另外，由於位移控制單元電路所需之TFT開關甚多， 當移位暫存器之級數很大時會花費大量的佈局面積及功率消耗，此外，利用位移控制單元實現之閘級驅動電路只能接受最多兩個系統時脈寬度之脈波訊號之輸出及輸入，如此將造成每一個OLED像素發光時間被限制為最多兩個時脈，因此當OLED顯示裝置在特殊應用上欲延長其發光時間時，位移控制單元電路將無法有彈性的被應用在閘級驅動電路中。 However, the conventional displacement control unit often has a leakage path between high and low potentials due to the characteristics of the transistor, which causes the illumination pulse signal and the scanning signal distortion outputted by the gate drive circuit to affect the image quality of the display. In addition, since the displacement control unit circuit requires a large number of TFT switches, When the number of stages of the shift register is large, a large amount of layout area and power consumption are required. In addition, the gate drive circuit realized by the displacement control unit can only accept pulse signals of up to two system clock widths. Output and input, this will cause each OLED pixel illumination time to be limited to at most two clocks, so when the OLED display device wants to extend its illumination time in special applications, the displacement control unit circuit will not be elastically applied in In the gate drive circuit.
本發明提供一種位移控制單元，包含第一電晶體，包含第一端用以接收輸入脈波訊號，控制端用以接收第一時脈訊號，及第二端；第二電晶體，包含第一端用以接收第二時脈訊號，控制端，及第二端；第一電容，包含第一端耦接於該第二電晶體之第二端，及第二端耦接於該第一電晶體之第二端；第三電晶體，包含第一端用以接收第一直流偏壓，控制端耦接於該第一電晶體之第二端，及第二端；第二電容，包含第一端用以接收該第一時脈訊號，及第二端耦接於該第三電晶體之第二端；第四電晶體，包含第一端用以接收第二直流偏壓，控制端耦接於該第一電晶體之第二端，及第二端耦接於該第二電晶體之控制端，用以輸出一發光脈波訊號；及第五電晶體，包含第一端耦接於該第四電晶體之第二端；一控制端耦接於該第三電晶體之第二端，及一第二端用以接收該第一直流偏壓。 The present invention provides a displacement control unit comprising a first transistor, comprising a first end for receiving an input pulse signal, a control end for receiving a first clock signal, and a second end; the second transistor comprising the first The second terminal is configured to receive the second clock signal, the control end, and the second end; the first capacitor includes a first end coupled to the second end of the second transistor, and the second end is coupled to the first end a second end of the crystal; the third transistor includes a first end for receiving the first DC bias, the control end is coupled to the second end of the first transistor, and the second end; the second capacitor includes The first end is configured to receive the first clock signal, and the second end is coupled to the second end of the third transistor; the fourth transistor includes a first end for receiving the second DC bias, and the control end The second end is coupled to the second end of the first transistor, and the second end is coupled to the control end of the second transistor for outputting a light pulse signal; and the fifth transistor includes a first end coupled The second end of the fourth transistor; a control end coupled to the second end of the third transistor, and a second end Receiving the first DC bias.
本發明另提供一種位移控制單元，包含第一電晶體，包含第一端用以接收輸入脈波訊號，控制端用以接收第一時脈訊號，及第二端；第二電晶體，包含第一端用以接收第二時脈訊號，控制端，及第二端；第一電容，包含第一端耦接於該第二電晶體之第二端，及第二端耦接於該第一電晶體之第二端；第二電容，包含第一端用以接收該第一時脈訊號，及第二端；第三電晶體，包含第一端耦接於該第二電容之第二端，控制端耦接於該第一電晶體之第二端，及第二端用以接收第二直流偏壓；第四電晶體，包含第一端用以接收第一直流偏壓，控制端耦接於該第一電晶體之第二端，及第二端耦接 於該第二電晶體之控制端，用以輸出發光脈波訊號；及第五電晶體，包含第一端耦接於該第四電晶體之第二端，控制端耦接於該第三電晶體之第一端，及第二端用以接收該第二直流偏壓。 The invention further provides a displacement control unit, comprising a first transistor, comprising a first end for receiving an input pulse signal, a control end for receiving a first clock signal, and a second end; the second transistor comprising One end is configured to receive the second clock signal, the control end, and the second end; the first capacitor includes a first end coupled to the second end of the second transistor, and the second end coupled to the first end a second end of the second transistor; the second end of the second capacitor; the first end is configured to receive the first clock signal, and the second end; the third transistor includes a first end coupled to the second end of the second capacitor The control end is coupled to the second end of the first transistor, and the second end is configured to receive the second DC bias voltage; the fourth transistor includes a first end for receiving the first DC bias voltage, and the control end The second end of the first transistor is coupled to the second end The second transistor is configured to be coupled to the second end of the fourth transistor, and the control end is coupled to the third The first end of the crystal, and the second end are configured to receive the second DC bias.
N1‧‧‧第一N型金氧半電晶體 N1‧‧‧First N-type gold oxide semi-transistor
N2‧‧‧第二N型金氧半電晶體 N2‧‧‧Second N-type gold oxide semi-transistor
N3‧‧‧第三N型金氧半電晶體 N3‧‧‧ Third N-type gold oxide semi-transistor
N4‧‧‧第四N型金氧半電晶體 N4‧‧‧4th N-type gold oxide semi-transistor
N5‧‧‧第五N型金氧半電晶體 N5‧‧‧ fifth N-type gold oxide semi-transistor
P1‧‧‧第一P型金氧半電晶體 P1‧‧‧First P-type oxy-halide transistor
P2‧‧‧第二P型金氧半電晶體 P2‧‧‧Second P-type oxy-oxygen semiconductor
P3‧‧‧第三P型金氧半電晶體 P3‧‧‧ Third P-type gold oxide semi-transistor
P4‧‧‧第四P型金氧半電晶體 P4‧‧‧Four P-type gold oxide semi-transistor
P5‧‧‧第五P型金氧半電晶體 P5‧‧‧ Fifth P-type MOS semi-transistor
C1‧‧‧第一電容 C1‧‧‧first capacitor
C2‧‧‧第二電容 C2‧‧‧second capacitor
IN‧‧‧輸入脈波訊號 IN‧‧‧ input pulse signal
EM‧‧‧發光脈波訊號 EM‧‧‧Glowing pulse signal
CK‧‧‧第一時脈訊號 CK‧‧‧ first clock signal
XCK‧‧‧第二時脈訊號 XCK‧‧‧ second clock signal
VGH‧‧‧第一直流偏壓 V GH ‧‧‧first DC bias
VGL‧‧‧第二直流偏壓 V GL ‧‧‧second DC bias
t0至t10‧‧‧時間 t 0 to t 10 ‧‧‧ time
第1圖係為本發明第一實施例之位移控制單元之電路示意圖。 Fig. 1 is a circuit diagram showing a displacement control unit of a first embodiment of the present invention.
第2圖係第1圖位移控制單元之輸入脈波訊號、第一時脈訊號、第二時脈訊號及發光脈波訊號在十個時脈區間內之波形圖。 Figure 2 is a waveform diagram of the input pulse wave signal, the first clock signal, the second clock signal, and the illumination pulse signal in the displacement control unit of the first figure in ten clock intervals.
第3圖係為本發明第二實施例之位移控制單元之電路示意圖。 Figure 3 is a circuit diagram of a displacement control unit of a second embodiment of the present invention.
為讓本發明更顯而易懂，下文依本發明之位移控制單元電路，特舉實施例配合所附圖式作詳細說明，但所提供之實施例並非用以限制本發明所涵蓋的範圍。 In order to make the invention more apparent, the following is a detailed description of the displacement control unit circuit according to the present invention, and the embodiments are not intended to limit the scope of the present invention.
請參考第1圖，第1圖係為本發明第一實施例之位移控制單元100之電路示意圖。如第1圖所示，位移控制單元100包含第一P型金氧半電晶體P1、第二P型金氧半電晶體P2、第三P型金氧半電晶體P3、第四P型金氧半電晶體P4及第五P型金氧半電晶體P5、第一電容C1及第二電容C2。每一P型金氧半電晶體P1、P2、P3、P4、P5包含第一端、控制端以及第二端。每一電容C1、C2包含第一端以及第二端。位移控制單元100之第一P型金氧半電晶體P1之第一端用來接收輸入脈波訊號IN，第一P型金氧半電晶體P1之控制端和第二電容C2之第一端用來接收第一時脈訊號CK，第二P型金氧半電晶體P2之第一端用來接收第二時脈訊號XCK，第三P型金氧半電晶體P3之第二端和第五P型金氧半電晶體P5之第二端耦接於第一直流偏壓VGH，第四P型金氧半電晶體P4之第一端耦接於第二直流偏壓VGL，而第四P型金氧半電晶體P4之第二端會傳送發光脈波訊號EM至第二P型金氧半 電晶體P2之控制端以控制第二P型金氧半電晶體P2的開關，且第四P型金氧半電晶體P4之第二端另耦接於發光二極體。在位移控制單元100中，第一直流偏壓VGH相對於第二直流偏壓VGL為高電位且第一時脈訊號CK和第二時脈訊號XCK可為反向，當第一時脈訊號CK為高電位時，由於第一直流偏壓VGH亦為高電位，無論第三P型金氧半電晶體P3是否開啟，第五P型金氧半電晶體P5之控制端電位必為高電位而將第五P型金氧半電晶體P5關閉；當第一時脈訊號CK為低電位且輸入脈波訊號IN為高電位時，第一P型金氧半電晶體P1為開啟，故高電位之輸入脈波訊號IN經由第一P型金氧半電晶體P1流向第四P型金氧半電晶體P4之控制端而將第四P型金氧半電晶體P4關閉；當第一時脈訊號CK為低電位且輸入脈波訊號IN為低電位時，第一P型金氧半電晶體P1為開啟，且第三P型金氧半電晶體P3之控制端電位等同於低電位之輸入脈波訊號IN而將第三P型金氧半電晶體P3開啟，此時高電位之第一直流偏壓VGH將經由第三P型金氧半電晶體P3流向第五P型金氧半電晶體P5之控制端而將第五P型金氧半電晶體P5關閉。由上述可知，位移控制單元100內之第四P型金氧半電晶體P4及第五P型金氧半電晶體P5在任何情況下均不會同時開啟，也就是說由第一直流偏壓VGH到第二直流偏壓VGL的漏電路徑在任何時間內是不存在的。 Please refer to FIG. 1. FIG. 1 is a circuit diagram of the displacement control unit 100 according to the first embodiment of the present invention. As shown in FIG. 1, the displacement control unit 100 includes a first P-type MOS transistor P1, a second P-type MOS transistor P2, a third P-type MOS transistor P3, and a fourth P-type gold. The oxygen semiconductor transistor P4 and the fifth P-type gold oxide semiconductor transistor P5, the first capacitor C1 and the second capacitor C2. Each of the P-type MOS transistors P1, P2, P3, P4, P5 includes a first end, a control end, and a second end. Each capacitor C1, C2 includes a first end and a second end. The first end of the first P-type MOS transistor P1 of the displacement control unit 100 is configured to receive the input pulse signal IN, the control end of the first P-type MOS transistor P1 and the first end of the second capacitor C2 For receiving the first clock signal CK, the first end of the second P-type MOS transistor P2 is for receiving the second clock signal XCK, and the second end of the third P-type MOS transistor P3 is The second end of the fifth P-type MOS transistor P5 is coupled to the first DC bias voltage V GH , and the first end of the fourth P-type MOS transistor B4 is coupled to the second DC bias voltage V GL . The second end of the fourth P-type MOS transistor P4 transmits the illuminating pulse signal EM to the control terminal of the second P-type MOS transistor P2 to control the switch of the second P-type MOS transistor P2. The second end of the fourth P-type MOS transistor P4 is coupled to the LED. In the displacement control unit 100, the first DC bias voltage V GH is high with respect to the second DC bias voltage V GL and the first clock signal CK and the second clock signal XCK may be reversed, when the first time When the pulse signal CK is at a high potential, since the first DC bias voltage V GH is also at a high potential, regardless of whether the third P-type MOS transistor P3 is turned on, the control terminal potential of the fifth P-type MOS transistor 5 The fifth P-type MOS transistor P5 must be turned off; when the first clock signal CK is low and the input pulse signal IN is high, the first P-type MOS transistor P1 is Turning on, the high-potential input pulse signal IN flows to the control terminal of the fourth P-type MOS transistor P4 via the first P-type MOS transistor P1 to turn off the fourth P-type MOS transistor P4; When the first clock signal CK is low and the input pulse signal IN is low, the first P-type MOS transistor P1 is turned on, and the control terminal potential of the third P-type MOS transistor P3 is equal. iN of the input pulse signal and the low potential of the third P-type metal-oxide-semiconductor transistor P3 is turned on, while the first DC bias of the high potential V GH via the third P-type Oxide-semiconductor transistor P3 flows fifth P-type metal-oxide-semiconductor electrical control terminal P5 of the crystal and the fifth P-type metal-oxide-semiconductor transistor P5 is turned off. It can be seen from the above that the fourth P-type MOS transistor P4 and the fifth P-type MOS transistor P5 in the displacement control unit 100 are not simultaneously turned on in any case, that is, by the first DC bias. The leakage path from V GH to the second DC bias voltage V GL does not exist at any time.
第2圖為位移控制單元100之輸入脈波訊號IN、第一時脈訊號CK、第二時脈訊號XCK及發光脈波訊號EM在連續十個時脈區間內之波形圖。在此考慮輸入脈波訊號IN為六個時脈寬度且輸入脈波訊號IN在第三個時脈區間到第八個時脈區間為高電位，其餘時脈區間為低電位。以下將分別針對十個時脈區間詳細描述位移控制單元100的電路驅動狀態。 FIG. 2 is a waveform diagram of the input pulse signal IN, the first clock signal CK, the second clock signal XCK, and the illumination pulse signal EM of the displacement control unit 100 in ten consecutive clock intervals. Here, the input pulse signal IN is considered to be six clock widths and the input pulse signal IN is at a high potential in the third clock interval to the eighth clock interval, and the remaining clock intervals are low. The circuit driving state of the displacement control unit 100 will be described in detail below for ten clock intervals, respectively.
當位移控制單元100運作於第一時脈區間(t0至t1的區間)時，輸入脈波訊號IN為低電位、發光脈波訊號EM之初始值為低電位、第一時脈訊號CK為高電位及第二時脈訊號XCK為低電位，因此在位移控制單元100中之第二P型金氧半電晶體P2、第三P型金氧半電晶體P3及第四P型金氧半電 晶體P4為開啟且第一P型金氧半電晶體P1及第五P型金氧半電晶體P5為關閉，因此第二直流偏壓VGL經由開啟的第四P型金氧半電晶體P4輸出成為低電位之發光脈波訊號EM。 When the displacement control unit 100 operates in the first clock interval (the interval between t 0 and t 1 ), the input pulse signal IN is low, the initial value of the illumination pulse signal EM is low, and the first clock signal CK The high potential and the second clock signal XCK are low, so the second P-type MOS transistor P2, the third P-type MOS transistor P3, and the fourth P-type gold oxide in the displacement control unit 100 The semi-transistor P4 is turned on and the first P-type MOS transistor P1 and the fifth P-type MOS transistor P5 are turned off, so the second DC bias voltage V GL is turned on via the fourth P-type MOS The crystal P4 outputs a low-emission luminous pulse signal EM.
當位移控制單元100運作於第二時脈區間(t1至t2的區間)時，輸入脈波訊號IN為低電位、第一時脈訊號CK為低電位及第二時脈訊號XCK為高電位，因此在位移控制單元100中之第一P型金氧半電晶體P1、第二P型金氧半電晶體P2、第三P型金氧半電晶體P3及第四P型金氧半電晶體P4為開啟且第五P型金氧半電晶體P5為關閉，因此第二直流偏壓VGL經由開啟的第四P型金氧半電晶體P4輸出成為一低電位之發光脈波訊號EM。 When the displacement control unit 100 operates in the second clock interval (the interval between t 1 and t 2 ), the input pulse signal IN is low, the first clock signal CK is low, and the second clock signal XCK is high. The potential, therefore, the first P-type MOS transistor P1, the second P-type MOS transistor P2, the third P-type MOS transistor P3, and the fourth P-type MOS half in the displacement control unit 100 The transistor P4 is turned on and the fifth P-type MOS transistor P5 is turned off, so the second DC bias voltage V GL is outputted as a low-potential light-emitting pulse signal via the turned-on fourth P-type MOS transistor P4. EM.
當位移控制單元100運作於第三時脈區間(t2至t3的區間)時，輸入脈波訊號IN為高電位、第一時脈訊號CK為高電位及第二時脈訊號XCK為低電位，因此在位移控制單元100中之第二P型金氧半電晶體P2、第三P型金氧半電晶體P3及第四P型金氧半電晶體P4為開啟且第一P型金氧半電晶體P1及第五P型金氧半電晶體P5為關閉，因此第二直流偏壓VGL經由開啟的第四P型金氧半電晶體P4輸出成為一低電位之發光脈波訊號EM。 When the displacement control unit 100 operates in the third clock interval (the interval between t 2 and t 3 ), the input pulse signal IN is high, the first clock signal CK is high, and the second clock signal XCK is low. The potential, therefore, the second P-type MOS transistor P2, the third P-type MOS transistor P3, and the fourth P-type MOS transistor P4 in the displacement control unit 100 are turned on and the first P-type gold The oxygen half transistor P1 and the fifth P type gold oxide half transistor P5 are turned off, so the second DC bias voltage V GL is outputted as a low potential light pulse wave signal via the turned-on fourth P-type metal oxide semiconductor transistor P4. EM.
當位移控制單元100運作於第四時脈區間(t3至t4的區間)時，輸入 脈波訊號IN為高電位、第一時脈訊號CK為低電位及第二時脈訊號XCK為高電位，因此在位移控制單元100中之第一P型金氧半電晶體P1及第五P型金氧半電晶體P5為開啟且第二P型金氧半電晶體P2、第三P型金氧半電晶體P3及第四P型金氧半電晶體P4為關閉，因此第一直流偏壓VGH經由開啟的第五P型金氧半電晶體P5輸出成為一高電位之發光脈波訊號EM。 When the displacement control unit 100 operates in the fourth clock interval (interval of t 3 to t 4 ), the input pulse signal IN is at a high potential, the first clock signal CK is at a low potential, and the second clock signal XCK is at a high level. The potential, therefore, the first P-type MOS transistor P1 and the fifth P-type MOS transistor P5 in the displacement control unit 100 are on and the second P-type MOS transistor P2, the third P-type gold The oxygen semiconductor transistor P3 and the fourth P-type gold oxide semiconductor transistor P4 are turned off, so that the first DC bias voltage V GH is output as a high-potential light-emitting pulse wave via the turned-on fifth P-type metal oxide semiconductor transistor P5. Signal EM.
當位移控制單元100運作於第五時脈區間(t4至t5的區間)時，輸入脈波訊號IN為高電位、第一時脈訊號CK為高電位及第二時脈訊號XCK為低電位，因此所有P型金氧半電晶體P1、P2、P3、P4及P5均為關閉狀態。然而因第四P型金氧半電晶體P4之第二端電位耦接於像素端之電晶體，故其輸出之發光脈波訊號EM藉由像素端之內部電容即維持在第四時脈區間之高 電位。 When the displacement control unit 100 operates in the fifth clock interval (interval of t 4 to t 5 ), the input pulse signal IN is high, the first clock signal CK is high, and the second clock signal XCK is low. The potential is therefore all P-type MOS transistors P1, P2, P3, P4 and P5 are off. However, since the second terminal of the fourth P-type MOS transistor P4 is coupled to the transistor at the pixel end, the output illuminating pulse signal EM is maintained in the fourth clock interval by the internal capacitance of the pixel terminal. High potential.
當位移控制單元100運作於第六時脈區間(t5至t6的區間)時，輸入脈波訊號IN為高電位、第一時脈訊號CK為低電位及第二時脈訊號XCK為高電位，因此在位移控制單元100中之第一P型金氧半電晶體P1及第五P型金氧半電晶體P5為開啟且第二P型金氧半電晶體P2、第三P型金氧半電晶體P3及第四P型金氧半電晶體P4為關閉，因此該第一直流偏壓VGH經由開啟的第五P型金氧半電晶體P5輸出成為一高電位之發光脈波訊號EM。 When the displacement control unit 100 operates in the sixth clock interval (the interval between t 5 and t 6 ), the input pulse signal IN is high, the first clock signal CK is low, and the second clock signal XCK is high. The potential, therefore, the first P-type MOS transistor P1 and the fifth P-type MOS transistor P5 in the displacement control unit 100 are on and the second P-type MOS transistor P2, the third P-type gold The oxygen half transistor P3 and the fourth P type gold oxide half transistor P4 are turned off, so the first DC bias voltage V GH is outputted as a high potential luminescence via the turned-on fifth P-type MOS transistor P5. Wave signal EM.
當位移控制單元100運作於第七時脈區間(t6至t7的區間)時，輸入脈波訊號IN為高電位、第一時脈訊號CK為高電位及第二時脈訊號XCK為低電位，因此所有P型金氧半電晶體P1、P2、P3、P4及P5均為關閉狀態。然而因第四P型金氧半電晶體P4之第二端電位耦接於像素端之電晶體，故發光脈波訊號EM藉由像素端之內部電容即維持在第六時脈區間之高電位。 When the displacement control unit 100 operates in the seventh clock interval (the interval between t 6 and t 7 ), the input pulse signal IN is high, the first clock signal CK is high, and the second clock signal XCK is low. The potential is therefore all P-type MOS transistors P1, P2, P3, P4 and P5 are off. However, since the second terminal of the fourth P-type MOS transistor P4 is coupled to the transistor at the pixel end, the illuminating pulse signal EM maintains the high potential of the sixth clock interval by the internal capacitance of the pixel terminal. .
當位移控制單元100運作於第八時脈區間(t7至t8的區間)時，輸入脈波訊號IN為高電位、第一時脈訊號CK為低電位及第二時脈訊號XCK為高電位，因此在位移控制單元100中之第一P型金氧半電晶體P1及第五P型金氧半電晶體P5為開啟且第二P型金氧半電晶體P2、第三P型金氧半電晶體P3及第四P型金氧半電晶體P4為關閉，因此該第一直流偏壓VGH經由開啟的第五P型金氧半電晶體P5輸出成為一高電位之發光脈波訊號EM。 When the displacement control unit 100 operates in the eighth clock interval (the interval from t 7 to t 8 ), the input pulse signal IN is at a high potential, the first clock signal CK is at a low potential, and the second clock signal XCK is at a high level. The potential, therefore, the first P-type MOS transistor P1 and the fifth P-type MOS transistor P5 in the displacement control unit 100 are on and the second P-type MOS transistor P2, the third P-type gold The oxygen half transistor P3 and the fourth P type gold oxide half transistor P4 are turned off, so the first DC bias voltage V GH is outputted as a high potential luminescence via the turned-on fifth P-type MOS transistor P5. Wave signal EM.
當位移控制單元100運作於第九時脈區間(t8至t9的區間)時，輸入脈波訊號IN為低電位、第一時脈訊號CK為高電位及第二時脈訊號XCK為低電位，因此所有P型金氧半電晶體P1、P2、P3、P4及P5均為關閉狀態。然而因第四P型金氧半電晶體P4之第二端電位耦接於像素端之電晶體，故發光脈波訊號EM藉由像素端之內部電容即維持在第八時脈區間之高電位。 When the displacement control unit 100 operates in the ninth clock interval (the interval from t 8 to t 9 ), the input pulse signal IN is low, the first clock signal CK is high, and the second clock signal XCK is low. The potential is therefore all P-type MOS transistors P1, P2, P3, P4 and P5 are off. However, since the second terminal of the fourth P-type MOS transistor P4 is coupled to the transistor at the pixel end, the illuminating pulse signal EM is maintained at the high potential of the eighth clock interval by the internal capacitance of the pixel terminal. .
當位移控制單元100運作於第十時脈區間(t9至t10的區間)時，輸入脈波訊號IN為低電位、第一時脈訊號CK為低電位及第二時脈訊號XCK為高電位，因此在位移控制單元100中之第一P型金氧半電晶體P1、第二P 型金氧半電晶體P2、第三P型金氧半電晶體P3及第四P型金氧半電晶體P4為開啟且第五P型金氧半電晶體P5為關閉，因此第二直流偏壓VGL經由開啟的第四P型金氧半電晶體P4輸出成為一低電位之發光脈波訊號EM。 When the displacement operation of the control unit 100 in the tenth clock interval (interval t 9 to t 10), the input pulse signal IN is low level, the first clock signal CK is low level and the second clock signal XCK is high The potential, therefore, the first P-type MOS transistor P1, the second P-type MOS transistor P2, the third P-type MOS transistor P3, and the fourth P-type MOS half in the displacement control unit 100 The transistor P4 is turned on and the fifth P-type MOS transistor P5 is turned off, so the second DC bias voltage V GL is outputted as a low-potential light-emitting pulse signal via the turned-on fourth P-type MOS transistor P4. EM.
由第2圖知，對應於六個時脈寬度之輸入脈波訊號IN，發光脈波訊號EM亦為六個時脈寬度且發光脈波訊號EM在第四個時脈區間到第九個時脈區間為高電位，其餘時脈區間為低電位。 According to the second figure, the input pulse signal IN corresponding to the six clock widths, the illumination pulse signal EM is also six clock widths, and the illumination pulse signal EM is in the fourth clock interval to the ninth. The clock interval is high, and the rest of the clock interval is low.
請參考第3圖，第3圖係為本發明第二實施例之位移控制單元200之電路示意圖。如第3圖所示，位移控制單元200包含第一N型金氧半電晶體N1、第二N型金氧半電晶體N2、第三N型金氧半電晶體N3、第四N型金氧半電晶體N4及第五N型金氧半電晶體N5、第一電容C1及第二電容C2。每一N型金氧半電晶體N1、N2、N3、N4、N5包含第一端、控制端以及第二端。每一電容C1、C2包含第一端以及第二端。位移控制單元200之第一N型金氧半電晶體N1之第一端用來接收輸入脈波訊號IN，且第一N型金氧半電晶體N1之控制端及第二電容C2之第一端用來接收第一時脈訊號CK，第二N型金氧半電晶體N2之第一端用來接收第二時脈訊號XCK。第四N型金氧半電晶體N4之第一端耦接於第一直流偏壓VGH且第五N型金氧半電晶體N5之第二端及第三N型金氧半電晶體N3之第二端耦接於第二直流偏壓VGL。第四N型金氧半電晶體N4之第二端耦接於第二N型金氧半電晶體N2之控制端及發光二極體並傳送發光脈波訊號EM至第二N型金氧半電晶體N2之控制端及發光二極體。在位移控制單元200中，第一直流偏壓VGH相對於第二直流偏壓VGL為高電位且第一時脈訊號CK和第二時脈訊號XCK可為反向，當第一時脈訊號CK為低電位時，由於第二直流偏壓VGL亦為低電位，無論第三N型金氧半電晶體N3是否開啟，第五N型金氧半電晶體N5之控制端電位必為低電位而將第五N型金氧半電晶體N5關閉；當第一時脈訊號CK為高電位且輸入脈波訊號IN為低電位時，第一N型金氧半電晶體N1為開啟，因此第四N型金氧半電晶體N4之控制端電位等同於低電位之脈波輸 入訊號IN而將第四N型金氧半電晶體N4關閉；當第一時脈訊號CK為高電位且輸入脈波訊號IN為高電位時，第一N型金氧半電晶體N1為開啟，因此第三N型金氧半電晶體N3之控制端為高電位而將第三N型金氧半電晶體N3開啟，因此第五N型金氧半電晶體N5之控制端電位等同於第二直流偏壓VGL之低電位而將第五N型金氧半電晶體N5開關關閉。由上述可知，位移控制單元200內之第四N型金氧半電晶體N4及第五N型金氧半電晶體N5開關在任何情況下均不會同時開啟，也就是說由第一直流偏壓VGH到第二直流偏壓VGL的漏電路徑在任何時間內是不存在的。 Please refer to FIG. 3, which is a circuit diagram of the displacement control unit 200 according to the second embodiment of the present invention. As shown in FIG. 3, the displacement control unit 200 includes a first N-type MOS transistor N1, a second N-type MOS transistor N2, a third N-type MOS transistor N3, and a fourth N-type gold. The oxygen semiconductor transistor N4 and the fifth N-type gold oxide semiconductor transistor N5, the first capacitor C1 and the second capacitor C2. Each of the N-type oxynitrides N1, N2, N3, N4, N5 includes a first end, a control end, and a second end. Each capacitor C1, C2 includes a first end and a second end. The first end of the first N-type MOS transistor N1 of the displacement control unit 200 is configured to receive the input pulse signal IN, and the first end of the first N-type MOS transistor N1 and the second capacitor C2 The terminal is configured to receive the first clock signal CK, and the first end of the second N-type MOS transistor N2 is configured to receive the second clock signal XCK. The first end of the fourth N-type MOS transistor N4 is coupled to the first DC bias voltage V GH and the second end of the fifth N-type MOS transistor N5 and the third N-type MOS transistor The second end of the N3 is coupled to the second DC bias voltage V GL . The second end of the fourth N-type MOS transistor N4 is coupled to the control terminal of the second N-type MOS transistor N2 and the LED and transmits the illuminating pulse signal EM to the second N-type oxy-half The control terminal of the transistor N2 and the light emitting diode. In the displacement control unit 200, the first DC bias voltage V GH is high with respect to the second DC bias voltage V GL and the first clock signal CK and the second clock signal XCK may be reversed, when the first time When the pulse signal CK is at a low potential, since the second DC bias voltage V GL is also low, regardless of whether the third N-type MOS transistor N3 is turned on, the control terminal potential of the fifth N-type MOS transistor N5 is necessary. The fifth N-type MOS transistor N5 is turned off for a low potential; when the first clock signal CK is at a high potential and the input pulse signal IN is at a low potential, the first N-type MOS transistor N1 is turned on. Therefore, the control terminal of the fourth N-type MOS transistor N4 is equivalent to the low-frequency pulse input signal IN to turn off the fourth N-type MOS transistor N4; when the first clock signal CK is high When the input pulse signal IN is at a high potential, the first N-type MOS transistor N1 is turned on, so the control terminal of the third N-type MOS transistor N3 is at a high potential and the third N-type MOS is half. The transistor N3 is turned on, so the control terminal potential of the fifth N-type MOS transistor N5 is equal to the low potential of the second DC bias voltage V GL and the fifth N-type gold is The oxygen half transistor N5 switch is turned off. It can be seen from the above that the fourth N-type MOS transistor N4 and the fifth N-type MOS transistor N5 switch in the displacement control unit 200 are not simultaneously turned on under any circumstances, that is, by the first DC. The leakage path of the bias voltage V GH to the second DC bias voltage V GL does not exist at any time.
綜上所述，本發明之位移控制單元只需要五P型金氧半電晶體或五N型金氧半電晶體以及二電容即可實現，在電路驅動時可接受超過兩個時脈寬度之脈波輸入訊號而產生對應寬度之發光脈波訊號，此外，在任何時脈區間由第一直流偏壓VGH至第二直流偏壓VGL之漏電路徑皆不存在。因此，本發明之位移控制單元除了能更有彈性地應用於不同發光時間的OLED像素之外，其驅動電路應用於OLED顯示系統也因為有較小的佈局面積以及不會漏電而產生壓降的特性，進而能提供較小的功率消耗和較高顯示品質。 In summary, the displacement control unit of the present invention only needs five P-type MOS transistors or five N-type MOS transistors and two capacitors, and can accept more than two clock widths when the circuit is driven. The pulse wave input signal generates a corresponding pulsed pulse wave signal, and in addition, the leakage path from the first DC bias voltage V GH to the second DC bias voltage V GL does not exist in any clock interval. Therefore, the displacement control unit of the present invention can be applied to an OLED display system in addition to being more flexible in application to OLED pixels of different illumination times, and also has a voltage drop due to a small layout area and no leakage. Features, which in turn provide less power consumption and higher display quality.
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
P1‧‧‧第一P型金氧半電晶體 P1‧‧‧First P-type oxy-halide transistor
P2‧‧‧第二P型金氧半電晶體 P2‧‧‧Second P-type oxy-oxygen semiconductor
P3‧‧‧第三P型金氧半電晶體 P3‧‧‧ Third P-type gold oxide semi-transistor
P4‧‧‧第四P型金氧半電晶體 P4‧‧‧Four P-type gold oxide semi-transistor
P5‧‧‧第五P型金氧半電晶體 P5‧‧‧ Fifth P-type MOS semi-transistor
C1‧‧‧第一電容 C1‧‧‧first capacitor
C2‧‧‧第二電容 C2‧‧‧second capacitor
IN‧‧‧輸入脈波訊號 IN‧‧‧ input pulse signal
EM‧‧‧發光脈波訊號 EM‧‧‧Glowing pulse signal
CK‧‧‧第一時脈訊號 CK‧‧‧ first clock signal
XCK‧‧‧第二時脈訊號 XCK‧‧‧ second clock signal
VGH‧‧‧第一直流偏壓 V GH ‧‧‧first DC bias
VGL‧‧‧第二直流偏壓 V GL ‧‧‧second DC bias
Claims (10)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103104075A TWI520117B (en) | 2014-02-07 | 2014-02-07 | Shift control cell |
| CN201410117601.0A CN104134423B (en) | 2014-02-07 | 2014-03-27 | Displacement control unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103104075A TWI520117B (en) | 2014-02-07 | 2014-02-07 | Shift control cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201532014A true TW201532014A (en) | 2015-08-16 |
| TWI520117B TWI520117B (en) | 2016-02-01 |
Family
ID=51807075
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW103104075A TWI520117B (en) | 2014-02-07 | 2014-02-07 | Shift control cell |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN104134423B (en) |
| TW (1) | TWI520117B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104376814B (en) * | 2014-11-25 | 2017-12-26 | 上海天马微电子有限公司 | A kind of drive circuit and driving method, display panel, display device |
| CN105096808B (en) * | 2015-09-18 | 2018-02-16 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
| KR20180062282A (en) * | 2016-11-30 | 2018-06-08 | 엘지디스플레이 주식회사 | Emission driver for display device and disaplay device applying thereof |
| CN113785350B (en) * | 2020-04-10 | 2023-06-16 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
| CN112838109A (en) * | 2020-08-28 | 2021-05-25 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100762690B1 (en) * | 2005-11-07 | 2007-10-01 | 삼성에스디아이 주식회사 | scan driving circuit and Organic Light Emitting Display Using the same |
| KR100776511B1 (en) * | 2006-04-18 | 2007-11-16 | 삼성에스디아이 주식회사 | Scan driving circuit and organic light emitting display using the same |
| TWI341507B (en) * | 2006-12-29 | 2011-05-01 | Chimei Innolux Corp | Shift register and liquid crystal display device |
| TWI480882B (en) * | 2012-09-04 | 2015-04-11 | Au Optronics Corp | Shift register and driving method thereof |
-
2014
- 2014-02-07 TW TW103104075A patent/TWI520117B/en active
- 2014-03-27 CN CN201410117601.0A patent/CN104134423B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN104134423A (en) | 2014-11-05 |
| TWI520117B (en) | 2016-02-01 |
| CN104134423B (en) | 2016-06-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI534781B (en) | Scan drive circuit and organic light shower display | |
| TWI459352B (en) | Displays | |
| US9262966B2 (en) | Pixel circuit, display panel and display apparatus | |
| WO2016026218A1 (en) | Pixel circuit, organic electroluminescent display panel and display apparatus | |
| WO2016074359A1 (en) | Pixel circuit, organic electroluminescence display panel, and display device and driving method therefor | |
| TWI596592B (en) | Compensation pixel circuit | |
| CN107818759B (en) | Pixel driving circuit, pixel driving method, array substrate and display device | |
| US10311783B2 (en) | Pixel circuit, method for driving the same, display panel and display device | |
| WO2018171137A1 (en) | Goa unit and driving method thereof, goa circuit, and display device | |
| US9972245B2 (en) | Pixel circuit, driving method for the pixel circuit, display panel, and display device | |
| US9437142B2 (en) | Pixel circuit and display apparatus | |
| US20170243535A1 (en) | Oled inverting circuit and display panel | |
| WO2015196730A1 (en) | Pixel circuit, driving method therefor and display device | |
| TWI520117B (en) | Shift control cell | |
| WO2016187991A1 (en) | Pixel circuit, drive method, organic electroluminescence display panel and display apparatus | |
| US9406259B2 (en) | Pixel circuits, organic electroluminescent display panels and display devices | |
| WO2015192528A1 (en) | Pixel circuit and display device | |
| TWI685831B (en) | Pixel circuit and driving method thereof | |
| TWI714317B (en) | Pixel circuit and display device having the same | |
| WO2016004693A1 (en) | Pixel circuit, driving method therefor, and display device | |
| WO2016004713A1 (en) | Pixel circuit and display device | |
| CN106782271B (en) | Pixel circuit, display panel and display device | |
| TWI699577B (en) | Pixel structure | |
| TWI694431B (en) | Pixel circuit and display device | |
| TWI780635B (en) | Display pannel and pixel circuit |