TWI685831B - Pixel circuit and driving method thereof - Google Patents

Abstract

A pixel circuit includes a first transistor, a second transistor, a third transistor and a driving transistor. A second terminal of the first transistor, a first terminal of the second transistor and a first terminal of the third transistor is coupled to a first node. A second terminal of the third transistor is coupled to a second node. The driving transistor is coupled to the second node and an emitting element. A first terminal of the first transistor receives a system high voltage. A second terminal of the second transistor receives a system low voltage. The first transistor and the third transistor are configured to conduct selectively according to a control signal. A control terminal of the second transistor is configured to receive a data signal. The driving transistor is configured to output a driving current to the emitting element according to the voltage level of the second node.

Description

Pixel circuit and its driving method

This disclosure relates to a pixel circuit, and particularly to a pixel circuit with a compensation function.

With the increasing demand for digital display devices, Indium Gallium Zinc Oxide (IGZO) is widely used in Active Matrix Liquid Crystal Displays (AMLCD) and Active Organic Light Emitting Diode display devices (Active Matrix Organic Light Emitting Display (AMOLED), etc.

In order to maintain a uniform brightness of the self-luminous display, the driving current in the pixels must be kept constant. However, in the IGZO process, the variation of the threshold voltage (Vth) of the driving transistor will cause the brightness of different pixels to change.

An aspect of this disclosure relates to a pixel circuit. The pixel circuit includes a first transistor, a second transistor, a third transistor, and a driving transistor. The first terminal of the first transistor receives the high voltage of the system. The second of the first transistor The terminal is coupled to the first node. The first transistor is used to selectively conduct according to the control signal. The first end of the second transistor is coupled to the first node. The second terminal of the second transistor receives the low voltage of the system. The control terminal of the second transistor is used to receive the data signal. The first end of the third transistor is coupled to the first node. The second terminal of the third transistor is coupled to the second node. The third transistor is used to selectively conduct according to the control signal. The driving transistor is coupled to the second node and the light emitting element. The driving transistor is used to output a driving current to the light emitting element according to the voltage level of the node.

One aspect of the present disclosure relates to another pixel circuit including a first transistor, a second transistor, a third transistor, and a driving transistor. The first terminal of the first transistor receives the high voltage of the system. The second terminal of the first transistor is coupled to the first node. The first transistor is used to selectively conduct according to the first control signal. The first end of the second transistor is coupled to the first node. The second terminal of the second transistor receives the low voltage of the system. The control terminal of the second transistor is used to receive the data signal. The first end of the third transistor is coupled to the first node. The second terminal of the third transistor is coupled to the second node. The third transistor is used to selectively conduct according to the second control signal. The driving transistor is coupled to the second node and the light emitting element. The driving transistor is used to output a driving current to the light emitting element according to the voltage level of the node.

An aspect of the present disclosure relates to a pixel circuit driving method, including: the first transistor and the second transistor are turned on according to the control signal and the data signal to provide a voltage level; and the third transistor is controlled according to the control signal Turn on to output the voltage level; the drive transistor outputs the drive current to the light-emitting element according to the voltage level; and the light-emitting element emits light according to the drive current.

100, 300 ‧‧‧ pixel circuit

T1, T2, T3, Td ‧‧‧ transistor

C1‧‧‧Capacitance

LED‧‧‧Lighting element

N1, N2‧‧‧ Node

S1, S2‧‧‧Control signal

Data‧‧‧Data signal

Id‧‧‧Drive current

OVDD‧‧‧System high voltage

OVSS‧‧‧System low voltage

Vs1, Vs2‧‧‧Enable voltage level

Vgl1, Vgh2, Vdl‧‧‧Enable voltage level

Vdata‧‧‧Data voltage level

During T1, T2, Tf‧‧‧

500‧‧‧ pixel circuit driving method

S520, S540, S560, S580‧‧‧Operation

FIG. 1 is a schematic diagram of a pixel circuit according to some embodiments of the present disclosure.

FIG. 2 is a signal timing diagram of a pixel circuit according to some embodiments of the present disclosure.

FIG. 3 is a schematic diagram of another pixel circuit according to other embodiments of the present disclosure.

FIG. 4 is a signal timing diagram of another pixel circuit according to other embodiments of the present disclosure.

FIG. 5 is a flowchart illustrating a pixel circuit driving method according to some embodiments of the present disclosure.

The following is a detailed description of the embodiments in conjunction with the drawings, but the specific embodiments described are only used to explain the case, not to limit the case, and the description of the structural operation is not used to limit the order of execution, any component The recombined structure and the resulting devices with equal effects are all covered by the disclosure.

Terms used throughout the specification and the scope of patent application, unless otherwise specified, usually have the ordinary meaning that each term is used in this field, in the content disclosed herein, and in special content. The terms "first", "second", "third", etc. used in this article do not specifically refer to order or order, nor are they intended to limit this disclosure. They are merely used to distinguish the same technology The term describes the element or operation only.

Please refer to Figure 1. FIG. 1 is a schematic diagram of a pixel circuit 100 according to some embodiments of the present disclosure. In some embodiments, the pixel circuit 100 may be used for an active liquid crystal display (Active Matrix Liquid Crystal Displays, AMLCD), an active organic light emitting diode display (Active Matrix Organic Light Emitting Display, AMOLED), an active micro light emitting diode Body display (Active Matrix Micro Light Emitting Display, AMOLED, AMμLED) and so on. The display device may include a plurality of pixel circuits 100 as shown in FIG. 1 to form a complete display screen.

As shown in FIG. 1, in some embodiments, the pixel circuit 100 includes a transistor T1, a transistor T2, a transistor T3, a driving transistor Td, a capacitor C1, and a light emitting element LED. In this embodiment, as shown in FIG. 1, the transistors T1, T2, T3 and the driving transistor Td are all N-type thin film transistors. Among them, the size W/L ratio of the transistor T1 and the transistor T2 is 1:4, W is the transistor gate width, and L is the transistor gate length. In some embodiments, the light emitting element LED may be a light emitting diode.

Structurally, the first end of the transistor T1 is coupled to the system high voltage OVDD. The control terminal of the transistor T1 is coupled to the scan line. The second end of the transistor T1 is coupled to the node N1. The first end of the transistor T2 is coupled to the node N1. The control terminal of the transistor T2 is coupled to the data line. The second terminal of the transistor T2 is coupled to the system low voltage OVSS. The first end of the transistor T3 is coupled to the node N1. The control terminal of the transistor T3 is coupled to the scan line. The second end of the transistor T3 is coupled to the node N2.

The first end of the driving transistor Td is coupled to the system high voltage OVDD. The control terminal of the driving transistor Td is coupled to the node N2. Drive transistor Td The second terminal is coupled to the system low voltage OVSS. The first end of the capacitor C1 is coupled to the node N2. The second end of the capacitor C1 is coupled to the second end of the driving transistor Td. The light emitting element LED is coupled between the first end of the driving transistor Td and the system high voltage OVDD. In some other embodiments, the light emitting element LED may be coupled between the driving transistor Td and the system low voltage OVSS.

In operation, the transistor T1 is used to selectively conduct according to the control signal S1 transmitted from the scan line. The transistor T2 is used to selectively conduct according to the data signal Data transmitted from the data line. In other words, the transistor T1 and the transistor T2 are used for conducting according to the control signal S1 and the data signal Data to provide a voltage level to the node N1.

The transistor T3 is used to selectively conduct according to the control signal S1 transmitted from the scan line to receive the voltage level of the node N1 and output it to the node N2. The driving transistor Td is used to selectively turn on according to the voltage level of the node N2 to output the driving current Id to the light emitting element LED. The light emitting element LED emits light according to the driving current Id.

For the convenience of description, the specific operations of each element in the pixel circuit 100 will be described with the drawings in the following paragraphs. Please refer to Figure 1 and Figure 2 together. FIG. 2 is a signal timing diagram of a pixel circuit 100 according to some embodiments of the present disclosure. As shown in Fig. 2, the period Tf is the time of one frame. The period Tf includes a first period T1 and a second period T2.

In some embodiments, the first period T1 corresponds to the writing and compensation phase of the pixel circuit 100. During the first period T1, the control signal S1 is the enable voltage level Vs1. As shown in Figure 2, the control signal S1 is at a high voltage level. In the first period T1, the data signal Data is the data voltage level Vdata. For example In other words, the first period T1 may be 2 microseconds.

The second period T2 corresponds to the light-emitting stage of the pixel circuit 100. During the second period T2, the control signal S1 is the disabled voltage level Vgl1. As shown in Figure 2, the control signal S1 is at a low voltage level. In the second period T2, the data signal Data is the disabled voltage level Vdl. As shown in Figure 2, the data signal Data can be at a low voltage level. In some embodiments, the disabled voltage levels Vgl1 and Vdl of the control signal S1 and the data signal Data may be the same or different voltage levels. In some other embodiments, during the second period T2, the data signal Data may be a floating voltage level.

Specifically, in the first period T1, the control signal S1 at the enable voltage level Vs1 turns on the transistor T1. The data signal Data at the data voltage level Vdata turns on the transistor T2. Since the currents of the transistor T1 and the transistor T2 are equal, as shown in the following formula (1): 4k(Vdata-Vth2) ² = k(Vs1-Vn1-Vth1) ² (1)

Among them, Vth1 is the critical voltage of transistor T1. Vth2 is the critical voltage of transistor T2. Vn1 is the voltage level provided to node N1.

Therefore, according to equation (1), the voltage level provided by transistor T1 and transistor T2 to node N1 is as shown in equation (2): Vn1=Vs1-2Vdata+2Vth2-Vth1 (2)

In addition, during the first period T1, the control signal S1 at the enable voltage level Vs1 also turns on the transistor T3 to provide the voltage level of the node N1 to the node N2. Specifically, the voltage level of the node N2 is as shown in equation (3).

Vn2=Vn1=Vs1-2Vdata+2Vth2-Vth1 (3)

Among them, Vn2 is the voltage level provided to the node N2.

In this way, according to equation (3) and because the distance between the transistors T1, T2, T3 and the driving transistor Td is close, the critical voltages of the transistors T1, T2, T3 and the driving transistor Td are approximately equal. Therefore, in the second period T2, the drive transistor Td outputs the drive current Id according to equation (4).

Id=k(Vgs-Vthd) ² =k(Vs1-2Vdata+2Vth2-Vth1-Vthd) ² =k(Vs1-2Vdata) ² (4)

Among them, Vgs is the voltage difference between the gate and source terminals of the driving transistor Td. Vthd is the critical voltage for driving transistor Td. Since the distances between the transistors T1, T2, T3 and the driving transistor Td are close, the critical voltage Vth1 of the transistor T1, the critical voltage Vth2 of the transistor T2, and the critical voltage Vthd of the driving transistor Td are approximately equal. Therefore, 2Vth2-Vth1-Vthd can be cancelled to zero. In other words, the influence of the driving current Id due to the variation of the threshold voltage Vthd of the driving transistor Td may be eliminated.

In addition, during the second period T2, the control signal S1 at the disabled voltage level Vgl1 turns off the transistors T1 and T3. The data signal Data at the disabled voltage level Vdl causes the transistor T2 to be turned off. In some other embodiments, the data signal Data at the floating voltage level makes the transistor T2 not necessarily on or off.

Please refer to Figure 3. FIG. 3 is a schematic diagram of another pixel circuit 300 according to other embodiments of the present disclosure. In the embodiment shown in FIG. 3, components similar to those in the embodiment of FIG. 1 are denoted by the same component symbols, and their operations have been described in the previous paragraphs, and will not be repeated here. Compared with the embodiment shown in FIG. 1, as shown in FIG. 3, the transistor T3 in the pixel circuit 300 is used To receive the control signal S2. Among them, the transistors T1 and T2 and the driving transistor Td are N-type thin film transistors, and the transistor T3 is a P-type thin film transistor.

For ease of description, the specific operations of each element in the pixel circuit 300 will be described with the drawings in the following paragraphs. Please refer to Figure 3 and Figure 4 together. FIG. 4 is a signal timing diagram of a pixel circuit 300 according to some embodiments of the present disclosure. In the embodiment shown in FIG. 4, elements similar to those in the embodiment of FIG. 2 are denoted by the same element symbols, and their operations have been described in the previous paragraphs, and will not be repeated here. Compared with the embodiment shown in FIG. 2, the control signal S2 is shown in FIG. 4.

In some embodiments, during the first period T1, the control signals S1 and S2 are the enable voltage levels Vs1 and Vs2, respectively. As shown in Fig. 4, the control signal S1 is at a high voltage level, and the control signal S2 is at a low voltage level. During the second period T2, the control signals S1 and S2 are the disabled voltage levels Vgl1 and Vgh2, respectively. As shown in Fig. 4, the control signal S1 is at a low voltage level, and the control signal S2 is at a high voltage level.

In some embodiments, the enable voltage level Vs1 and the disable voltage level Vgh2 may be the same voltage level. The disabled voltage level Vgl1 and the enabled voltage level Vs2 may be the same voltage level. In other words, the control signals S1 and S2 can be mutually opposite signals.

Please refer to Figure 5. FIG. 5 is a flowchart illustrating a pixel circuit driving method 500 according to some embodiments of the present disclosure. As shown in FIG. 5, the pixel circuit driving method 500 includes operations S520, S540, S560, and S580.

First, in operation S520, the transistor T1 and the transistor T2 are turned on according to the control signal S1 and the data signal Data to provide a voltage level. Specifically, in the first period T1, the transistor T1 is turned on according to the control signal S1, and the transistor T2 is turned on according to the data signal Data. The voltage level is provided to the node N1 according to the current flowing through the transistor T1 and the transistor T2 together. At this time, the voltage level of the node N1 is as shown in the above formula (2).

Next, in operation S540, the transistor T3 is turned on according to the control signal S1 or S2 to output the voltage level. Specifically, in the first period T1, the N-type thin film transistor T3 is turned on according to the control signal S1 to output the voltage level of the node N1 to the node N2. Alternatively, the P-type thin film transistor T3 is turned on according to the control signal S2 to output the voltage level of the node N1 to the node N2. At this time, the voltage level of the node N2 is as shown in the above formula (3).

Next, in operation S560, the driving current Td is output to the light emitting element LED by the driving transistor Td according to the voltage level. Specifically, in the second period T2, the driving transistor Td outputs the driving current Id to the light emitting element LED according to the voltage level shown in equation (3). The drive current Id is shown in equation (4).

Next, in operation S580, the light emitting element LED emits light according to the drive current Id.

Although the disclosed method is shown and described herein as a series of steps or events, it should be understood that the order of the steps or events shown should not be interpreted as limiting. For example, some steps may occur in a different order and/or simultaneously with other steps or events other than those shown and/or described herein. In addition, not all of the steps shown here are necessary to implement one or more aspects or embodiments described herein. In addition, one or more steps herein may also be performed in one or more separate steps and/or stages.

In summary, in this case, through the application of the above embodiments, the size ratio of the transistors T1 and T2 and the design of the data signal Data are used to compensate, so that when the display panel displays, the current size of the drive current Id will not be affected The driving transistor Td is influenced by the element characteristics (such as different threshold voltages), and can provide a relatively stable driving current Id. In addition, by simultaneously completing data writing and transistor threshold voltage compensation in one stage, the time from the compensation threshold voltage to the light emitting element LED emitting light can be significantly shortened, and the compensation effect is good. Furthermore, in some embodiments of this case, only one scan line control signal S1 is needed, so the complexity of the control circuit can be reduced, and thus the cost of the display system can be reduced. The pixel circuits 100 and 300 in this case are of 4T1C architecture, which can reduce the area of the transistor array compared to pixel circuits of 4T2C or higher.

Although this disclosure has been disclosed as above by way of implementation, it is not intended to limit this disclosure. Those with ordinary knowledge in the technical field can make various changes and modifications within the spirit and scope of this disclosure, so this The scope of protection of the disclosure shall be deemed as defined by the scope of the attached patent application.

100‧‧‧Pixel circuit

T1, T2, T3, Td ‧‧‧ transistor

C1‧‧‧Capacitance

LED‧‧‧Lighting element

N1, N2‧‧‧ Node

S1‧‧‧Control signal

Data‧‧‧Data signal

Id‧‧‧Drive current

OVDD‧‧‧System high voltage

OVSS‧‧‧System low voltage

Claims (10)

A pixel circuit includes: a first transistor, a first terminal of the first transistor receives a system high voltage, a second terminal of the first transistor is coupled to a first node, the first circuit The crystal is used to selectively conduct according to a control signal; a second transistor, a first end of the second transistor is coupled to the first node, and a second end of the second transistor receives a system low voltage , A control terminal of the second transistor is used to receive a data signal; a third transistor, a first end of the third transistor is coupled to the first node, and a second end of the third transistor Coupled to a second node, the third transistor is used to selectively conduct according to the control signal; and a driving transistor, the driving transistor is coupled to the second node and a light emitting element, the driving transistor is used to According to the voltage level of the second node, a driving current is output to the light-emitting device. The pixel circuit according to claim 1, further comprising: a capacitor, a first terminal of the capacitor is coupled to the second node, and a second terminal of the capacitor is coupled to the second terminal of the driving transistor. The pixel circuit as described in claim 1, wherein in a first period, the first transistor and the third transistor are used to conduct according to the control signal, and the second transistor is used to receive the data signal, in During a second period, the first transistor is used to turn off according to the control signal, and the light emitting element is used to emit light according to the driving current. The pixel circuit as claimed in claim 1, wherein a size ratio of the first transistor and the second transistor is one to four. The pixel circuit according to claim 4, wherein the first transistor, the second transistor, the third transistor, and the driving transistor are N-type thin film transistors. A pixel circuit includes: a first transistor, a first terminal of the first transistor receives a system high voltage, a second terminal of the first transistor is coupled to a first node, the first circuit The crystal is used to selectively conduct according to a first control signal; a second transistor, a first end of the second transistor is coupled to the first node, and a second end of the second transistor receives a system At a low voltage, a control terminal of the second transistor is used to receive a data signal; a third transistor, a first terminal of the third transistor is coupled to the first node, and a second terminal of the third transistor The terminal is coupled to a second node, the third transistor is used to selectively conduct according to a second control signal; and a driving transistor, the driving transistor is coupled to the second node and a light emitting element, the driving circuit The crystal is used to output a driving current to the light emitting device according to the voltage level of the node. A pixel circuit driving method includes: a first transistor and a second transistor according to a control signal and A data signal is turned on and provides a voltage level according to the current flowing through the first transistor and the second transistor together, wherein a second end of the first transistor is connected to a first terminal of the second transistor One end; a third transistor is turned on according to the control signal to output the voltage level; a driving transistor outputs a driving current to a light emitting element according to the voltage level; and a light emitting element performs according to the driving current Glow. The driving method of the pixel circuit according to claim 7, further comprising: during a first period, the first transistor and the second transistor are respectively turned on according to the control signal and the data signal to provide the voltage level , And the third transistor is turned on according to the control signal to output the voltage level; and in a second period, the first transistor and the third transistor are turned off according to the control signal, and the driving circuit The crystal outputs the driving current to the light emitting element according to the voltage level, and the light emitting element emits light according to the driving current. The pixel circuit driving method according to claim 7, wherein a size ratio of the first transistor and the second transistor is one to four. The pixel circuit driving method according to claim 7, wherein the first transistor, the second transistor, the third transistor and the driving transistor The body is an N-type thin film transistor.

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