TWI699742B - Pixel circuit - Google Patents

Pixel circuit Download PDF

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TWI699742B
TWI699742B TW108100427A TW108100427A TWI699742B TW I699742 B TWI699742 B TW I699742B TW 108100427 A TW108100427 A TW 108100427A TW 108100427 A TW108100427 A TW 108100427A TW I699742 B TWI699742 B TW I699742B
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driving transistor
terminal
pixel circuit
compensation
compensation capacitor
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TW108100427A
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Chinese (zh)
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TW202001840A (en
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林志隆
曾金賢
賴柏成
林祐陞
鄭貿薰
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友達光電股份有限公司
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Priority to CN201910380336.8A priority Critical patent/CN110070825B/en
Priority to US16/436,126 priority patent/US10916169B2/en
Publication of TW202001840A publication Critical patent/TW202001840A/en
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Publication of TWI699742B publication Critical patent/TWI699742B/en
Priority to US16/952,199 priority patent/US11495155B2/en

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Abstract

A pixel circuit includes a light emitting element, a first driver transistor, a second driver transistor, and a first compensation capacitor. A first terminal of the first driving transistor is configured to receive a power signal, and a second terminal of the first driving transistor is electrically coupled to the light emitting element. A first terminal of the second driving transistor receives the power signal, and a control terminal of the second driving transistor is electrically coupled to the light emitting element. The first compensation capacitance is electrically coupled to a control terminal of the first driving transistor and the second terminal of the second driving transistor, respectively.

Description

畫素電路 Pixel circuit

本揭示內容關於一種畫素電路，特別是一種可補償驅動電晶體的臨界電壓變異的畫素電路。 The present disclosure relates to a pixel circuit, particularly a pixel circuit that can compensate for the variation of the threshold voltage of the driving transistor.

低溫多晶矽薄膜電晶體(low temperature poly-silicon thin-film transistor)具有高載子遷移率與尺寸小的特點，適合應用於高解析度、窄邊框以及低耗電的顯示面板。目前業界廣泛使用準分子雷射退火(excimer laser annealing)技術來形成低溫多晶矽薄膜電晶體的多晶矽薄膜。然而，由於準分子雷射每一發的掃描功率並不穩定，不同區域的多晶矽薄膜會具有晶粒尺寸與數量的差異。因此，於顯示面板的不同區域中，低溫多晶矽薄膜電晶體的特性便會不同。例如，不同區域的低溫多晶矽薄膜電晶體會有著不同的臨界電壓(threshold voltage)。 Low temperature poly-silicon thin-film transistors have the characteristics of high carrier mobility and small size, and are suitable for high-resolution, narrow-frame and low-power display panels. Excimer laser annealing (excimer laser annealing) technology is widely used in the industry to form low-temperature polysilicon thin-film transistors. However, since the scanning power of each excimer laser is not stable, the polysilicon film in different regions will have differences in the size and number of crystal grains. Therefore, in different areas of the display panel, the characteristics of the low-temperature polysilicon thin film transistors will be different. For example, low-temperature polysilicon thin-film transistors in different regions have different threshold voltages.

目前業界廣泛使用畫素內補償之技術方案，以克服上述臨界電壓變異的問題。然而，具有畫素內補償功能之畫素電路具有複雜之電路結構，使得相關之顯示面板的開口率低下。 At present, the industry widely uses the technical solution of pixel compensation to overcome the above-mentioned problem of threshold voltage variation. However, the pixel circuit with the function of pixel compensation has a complicated circuit structure, so that the aperture ratio of the related display panel is low.

本揭示內容之一態樣為一種畫素電路，包含發光元件、第一驅動電晶體、第二驅動店經及第一補償電容。第一驅動電晶體具有第一端、第二端與控制端。第一驅動電晶體該第一端用以接收電源訊號，第一驅動電晶體的第二端電性連接至發光元件。第二驅動電晶體具有第一端、第二端與控制端。第二驅動電晶體的第一端用以接收電源訊號，第二驅動電晶體的控制端電性連接至發光元件。第一補償電容分別電性連接於第一驅動電晶體的控制端與第二驅動電晶體之第二端之間。 One aspect of the present disclosure is a pixel circuit including a light-emitting element, a first driving transistor, a second driving circuit, and a first compensation capacitor. The first driving transistor has a first end, a second end and a control end. The first end of the first driving transistor is used for receiving a power signal, and the second end of the first driving transistor is electrically connected to the light-emitting element. The second driving transistor has a first end, a second end and a control end. The first terminal of the second driving transistor is used for receiving a power signal, and the control terminal of the second driving transistor is electrically connected to the light emitting element. The first compensation capacitor is electrically connected between the control terminal of the first driving transistor and the second terminal of the second driving transistor.

本揭示內容之另一態樣為一種畫素電路，包含發光元件、第一驅動電晶體、第二驅動店經及第一補償電容。第一驅動電晶體具有第一端、第二端與控制端。第一驅動電晶體的第二端電性連接至發光元件。第二驅動電晶體具有第一端、第二端與控制端。第二驅動電晶體的控制端電性連接至發光元件。第一補償電容分別電性連接於第一驅動電晶體的控制端與第二驅動電晶體的第二端之間，且第一補償電容及第二驅動電晶體之間為補償節點。其中，於資料寫入階段中，第一驅動電晶體的控制端用以接收資料訊號；於補償階段中，補償節點之電壓實質上為兩倍的第二驅動電晶體的控制端的電壓。 Another aspect of the present disclosure is a pixel circuit including a light-emitting element, a first driving transistor, a second driving circuit, and a first compensation capacitor. The first driving transistor has a first end, a second end and a control end. The second end of the first driving transistor is electrically connected to the light emitting element. The second driving transistor has a first end, a second end and a control end. The control terminal of the second driving transistor is electrically connected to the light-emitting element. The first compensation capacitor is electrically connected between the control terminal of the first driving transistor and the second terminal of the second driving transistor, and the compensation node is between the first compensation capacitor and the second driving transistor. In the data writing stage, the control terminal of the first driving transistor is used to receive the data signal; in the compensation stage, the voltage of the compensation node is substantially twice the voltage of the control terminal of the second driving transistor.

本揭示內容利用相互匹配的第一驅動電晶 體及第二驅動電晶體，偵測臨界電壓值的變異，據此，將能精簡畫素電路的電路架構，使其可透過單一條訊號線，控制畫素電路進行補償。 The present disclosure uses matched first driving transistors and second driving transistors to detect the variation of the threshold voltage value. According to this, the circuit structure of the pixel circuit can be simplified so that it can be controlled by a single signal line The pixel circuit compensates.

100‧‧‧畫素電路 100‧‧‧Pixel circuit

110‧‧‧發光二極體 110‧‧‧Light Emitting Diode

T1‧‧‧第一驅動電晶體 T1‧‧‧First driving transistor

T2‧‧‧第二驅動電晶體 T2‧‧‧Second driving transistor

T3‧‧‧電晶體開關 T3‧‧‧Transistor Switch

C1‧‧‧第一補償電容 C1‧‧‧First compensation capacitor

C2‧‧‧第二補償電容 C2‧‧‧Second compensation capacitor

A‧‧‧第一節點 A‧‧‧First node

B‧‧‧第二節點 B‧‧‧Second node

C‧‧‧補償節點 C‧‧‧Compensation node

Vdd‧‧‧電源訊號 Vdd‧‧‧Power signal

Vss‧‧‧參考電壓源 Vss‧‧‧Reference voltage source

Vdata‧‧‧資料訊號 Vdata‧‧‧Data signal

P1‧‧‧重置階段 P1‧‧‧Reset phase

P2‧‧‧資料寫入階段 P2‧‧‧Data writing stage

P3‧‧‧補償階段 P3‧‧‧Compensation phase

P4‧‧‧發光階段 P4‧‧‧Lighting stage

Ir‧‧‧重置電流 Ir‧‧‧reset current

I1‧‧‧第一電流 I1‧‧‧First current

I2‧‧‧第二電流 I2‧‧‧Second current

I3‧‧‧第三電流 I3‧‧‧Third current

I4‧‧‧第四電流 I4‧‧‧Fourth current

I5‧‧‧第五電流 I5‧‧‧Fifth current

I6‧‧‧第六電流 I6‧‧‧Sixth current

Vh‧‧‧高準位電壓 Vh‧‧‧High level voltage

V1‧‧‧低準位電壓 V1‧‧‧Low level voltage

S1、S1[n]、S1[n-1]‧‧‧閘極訊號 S1, S1[n], S1[n-1]‧‧‧Gate signal

Vin‧‧‧輸入訊號 Vin‧‧‧Input signal

第1圖為根據本揭示內容之部分實施例所繪示的畫素電路的示意圖。 FIG. 1 is a schematic diagram of a pixel circuit according to some embodiments of the present disclosure.

第2圖為根據本揭示內容之部分實施例所繪示的畫素電路的運作時序圖。 FIG. 2 is a timing diagram of the operation of the pixel circuit according to some embodiments of the present disclosure.

第3A~3D圖為本揭示內容之部分實施例中，畫素電路於不同運作時序中的示意圖。 Figures 3A to 3D are schematic diagrams of pixel circuits in different operation timings in some embodiments of the disclosure.

以下將以圖式揭露本案之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本案。也就是說，在本揭示內容部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。 Hereinafter, multiple implementation modes of this case will be disclosed in schematic form. For the sake of clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the case. In other words, in some implementations of the present disclosure, these practical details are unnecessary. In addition, in order to simplify the drawings, some conventionally used structures and elements are shown in the drawings in a simple and schematic manner.

於本文中，當一元件被稱為「連接」或「耦接」時，可指「電性連接」或「電性耦接」。「連接」或「耦接」亦可用以表示二或多個元件間相互搭配 操作或互動。此外，雖然本文中使用「第一」、「第二」、...等用語描述不同元件，該用語僅是用以區別以相同技術用語描述的元件或操作。除非上下文清楚指明，否則該用語並非特別指稱或暗示次序或順位，亦非用以限定本發明。 In this text, when a component is referred to as “connected” or “coupled”, it can be referred to as “electrically connected” or “electrically coupled”. "Connected" or "coupled" can also be used to mean that two or more components cooperate or interact with each other. In addition, although terms such as "first", "second", ... are used herein to describe different elements, the terms are only used to distinguish elements or operations described in the same technical terms. Unless the context clearly indicates, the terms do not specifically refer to or imply order or sequence, nor are they used to limit the present invention.

請參閱第1圖所示，為根據本揭示內容之部分實施例所繪示的畫素電路100的示意圖。畫素電路100包含發光元件110、第一驅動電晶體T1、第二驅動電晶體T2及第一補償電容C1。在部分實施例中，發光元件110為至少一個發光二極體，例如：有機發光二極體(Organic Light-Emitting Diode)。於本實施例中，第一驅動電晶體T1具有第一端、第二端與控制端，其中，第一驅動電晶體T1的第一端用以接收電源訊號Vdd，第一驅動電晶體T1的第二端則電性連接至該發光元件110。具體而言，發光元件110具有正極端及負極端，而第一驅動電晶體T1之第二端電性連接於發光元件110的正極端。 Please refer to FIG. 1, which is a schematic diagram of a pixel circuit 100 drawn according to some embodiments of the present disclosure. The pixel circuit 100 includes a light-emitting element 110, a first driving transistor T1, a second driving transistor T2, and a first compensation capacitor C1. In some embodiments, the light-emitting element 110 is at least one light-emitting diode, such as an organic light-emitting diode (Organic Light-Emitting Diode). In this embodiment, the first driving transistor T1 has a first terminal, a second terminal and a control terminal. The first terminal of the first driving transistor T1 is used to receive the power signal Vdd, and the first driving transistor T1 The second end is electrically connected to the light-emitting element 110. Specifically, the light-emitting element 110 has a positive terminal and a negative terminal, and the second terminal of the first driving transistor T1 is electrically connected to the positive terminal of the light-emitting element 110.

於本實施例中，第二驅動電晶體T2具有第一端、第二端與控制端。第二驅動電晶體T2的第一端同樣用以接收電源訊號Vdd，而第二驅動電晶體T2的控制端電性連接至發光元件110的正極端。第一補償電容C1則分別電性連接於第一驅動電晶體T1的控制端與第二驅動電晶體T2的第二端。在部分實施例中，第二驅動電晶體T2的第二端透過補償節點C而電 性連接至第一補償電容C1，且第一驅動電晶體T1及第二驅動電晶體T2之臨界電壓值Vth相互匹配。 In this embodiment, the second driving transistor T2 has a first terminal, a second terminal and a control terminal. The first terminal of the second driving transistor T2 is also used to receive the power signal Vdd, and the control terminal of the second driving transistor T2 is electrically connected to the positive terminal of the light emitting element 110. The first compensation capacitor C1 is electrically connected to the control terminal of the first driving transistor T1 and the second terminal of the second driving transistor T2, respectively. In some embodiments, the second terminal of the second driving transistor T2 is electrically connected to the first compensation capacitor C1 through the compensation node C, and the threshold voltage value Vth of the first driving transistor T1 and the second driving transistor T2 Match each other.

據此，由於整個畫素電路100可透過單一條訊號線進行控制(即，控制第一驅動電晶體T1的控制端的電壓)，故能有效精簡電路架構。相較於一般的畫素電路，因為需要控制至少一個額外的電晶體開關，來補償驅動電晶體之臨界電壓的變異，因此電路會較為複雜，且亦需要多條控制訊號線。本揭示內容之畫素電路透過第一驅動電晶體T1及第二驅動電晶體T2彼此間的匹配關係來實現補償，因此，不需要使用額外的一條訊號控制線去控制第二驅動電晶體T2。 Accordingly, since the entire pixel circuit 100 can be controlled through a single signal line (ie, control the voltage of the control terminal of the first driving transistor T1), the circuit structure can be effectively simplified. Compared with the general pixel circuit, because at least one additional transistor switch needs to be controlled to compensate for the variation of the threshold voltage of the driving transistor, the circuit is more complicated and multiple control signal lines are required. The pixel circuit of the present disclosure realizes compensation through the matching relationship between the first driving transistor T1 and the second driving transistor T2. Therefore, there is no need to use an additional signal control line to control the second driving transistor T2.

在部分實施例中，在畫素電路100處於資料寫入階段時，第一驅動電晶體T1的控制端用以接收資料訊號，使得畫素電路100處於補償階段時，補償節點C之電壓實質上為兩倍的第二驅動電晶體T2的控制端的電壓，以補償電晶體之臨界電壓Vth變異造成的影響，使發光元件110產生預期之光亮。 In some embodiments, when the pixel circuit 100 is in the data writing stage, the control terminal of the first driving transistor T1 is used to receive the data signal, so that when the pixel circuit 100 is in the compensation stage, the voltage of the compensation node C is substantially The voltage at the control terminal of the second driving transistor T2 is doubled to compensate for the influence of the variation of the threshold voltage Vth of the transistor, so that the light-emitting element 110 generates the expected light.

在部分實施例中，畫素電路100更包含第二補償電容C2。第二補償電容C2具有第一端與第二端，且第二補償電容C2的第一端電性連接至參考電壓源Vss。第二補償電容C2的第二端電性連接至第一驅動電晶體T1之控制端。在本實施例中，第一補償電容C1及第二補償電容C2可組成電容耦合電路，第一補償電容C1及第二補償電容C2之間具有第一節點A。在 部分實施例中，第一節點A對應於第一驅動電晶體T1的控制端，以在第一節點A接收輸入訊號Vin(如：用於控制發光元件110之亮度的資料訊號)、且輸入訊號Vin產生電壓變化時，電容耦合電路透過第一補償電容C1及第二補償電容C2間的電容耦合效應，改變第一驅動電晶體T1的閘極電壓值。 In some embodiments, the pixel circuit 100 further includes a second compensation capacitor C2. The second compensation capacitor C2 has a first terminal and a second terminal, and the first terminal of the second compensation capacitor C2 is electrically connected to the reference voltage source Vss. The second terminal of the second compensation capacitor C2 is electrically connected to the control terminal of the first driving transistor T1. In this embodiment, the first compensation capacitor C1 and the second compensation capacitor C2 can form a capacitive coupling circuit, and there is a first node A between the first compensation capacitor C1 and the second compensation capacitor C2. In some embodiments, the first node A corresponds to the control terminal of the first driving transistor T1 to receive the input signal Vin (such as a data signal for controlling the brightness of the light-emitting element 110) at the first node A, and input When the signal Vin generates a voltage change, the capacitive coupling circuit changes the gate voltage value of the first driving transistor T1 through the capacitive coupling effect between the first compensation capacitor C1 and the second compensation capacitor C2.

在部分實施例中，第一驅動電晶體T1與第二驅動電晶體T2之臨界電壓值具有第一匹配關係。第一補償電容C1及第二補償電容C2之電容值具有第二匹配關係，且第一匹配關係與第二匹配關係相同。舉例而言，第一驅動電晶體T1與第二驅動電晶體T2之臨界電壓值為1：1，第一補償電容C1及第二補償電容C2之電容值亦為1：1。或者，第一驅動電晶體T1及第二驅動電晶體T2之臨界電壓值為2：1，第一補償電容C1及第二補償電容C2之電容值為2：1。具體而言，第一驅動電晶體T1之臨界電壓值與第二驅動電晶體T2之臨界電壓值的比值關係實質相等於第一補償電容C1與第二補償電容C2的比值關係。據此，當畫素電路100處於補償階段時，補償節點C之電壓實質上為兩倍的第二驅動電晶體T2的控制端的電壓。在本實施例中，第一驅動電晶體T1與第二驅動電晶體T2具有相同之臨界電壓值，第一補償電容C1及第二補償電容C2具有相同之電容值。 In some embodiments, the threshold voltage values of the first driving transistor T1 and the second driving transistor T2 have a first matching relationship. The capacitance values of the first compensation capacitor C1 and the second compensation capacitor C2 have a second matching relationship, and the first matching relationship is the same as the second matching relationship. For example, the threshold voltage value of the first driving transistor T1 and the second driving transistor T2 is 1:1, and the capacitance value of the first compensation capacitor C1 and the second compensation capacitor C2 is also 1:1. Alternatively, the threshold voltage value of the first driving transistor T1 and the second driving transistor T2 is 2:1, and the capacitance value of the first compensation capacitor C1 and the second compensation capacitor C2 is 2:1. Specifically, the ratio of the threshold voltage value of the first driving transistor T1 to the threshold voltage value of the second driving transistor T2 is substantially equal to the ratio of the first compensation capacitor C1 to the second compensation capacitor C2. Accordingly, when the pixel circuit 100 is in the compensation phase, the voltage of the compensation node C is substantially twice the voltage of the control terminal of the second driving transistor T2. In this embodiment, the first driving transistor T1 and the second driving transistor T2 have the same threshold voltage value, and the first compensation capacitor C1 and the second compensation capacitor C2 have the same capacitance value.

在其他部分實施例中，畫素電路100更包 含電晶體開關T3。電晶體開關T3具有第一端、第二端與控制端。電晶體開關T3的第一端用以接收輸入訊號Vin，在資料寫入階段中，輸入訊號Vin為資料訊號。另外，電晶體開關T3的第二端電性連接至第一驅動電晶體T1之控制端。電晶體開關T3的控制端用以接收閘極訊號S1，以透過閘極訊號S1，決定電晶體開關T3之啟閉。 In some other embodiments, the pixel circuit 100 further includes a transistor switch T3. The transistor switch T3 has a first terminal, a second terminal and a control terminal. The first end of the transistor switch T3 is used to receive the input signal Vin. In the data writing stage, the input signal Vin is a data signal. In addition, the second terminal of the transistor switch T3 is electrically connected to the control terminal of the first driving transistor T1. The control terminal of the transistor switch T3 is used for receiving the gate signal S1, and determines the opening and closing of the transistor switch T3 through the gate signal S1.

為清楚說明畫素電路100的運作方式，在此以第3A~3D圖為例，分別說明畫素電路100的操作時序。請參閱第2及3A~3D圖，其中第2圖係根據本揭示內容之部分實施例繪製之運作時序圖。如第2圖所示，畫素電路100的工作週期包括重置階段P1、資料寫入階段P2、補償階段P3及發光階段P4。在部分實施例中，重置階段P1、資料寫入階段P2、補償階段P3與發光階段P4為依照時間順序排列的時序。在本實施例中，畫素電路100應用於顯示裝置。顯示裝置之處理器會依序驅動每一排的畫素電路100。因此，第2圖中之S1[n]代表用於控制第3A~3D圖中繪示之畫素電路100的閘極訊號、S1[n-1]則代表用於驅動與該畫素電路100相鄰之另一排之畫素電路的閘極訊號。 In order to clearly illustrate the operation mode of the pixel circuit 100, the operation timings of the pixel circuit 100 are respectively described by taking FIGS. 3A to 3D as examples. Please refer to Figures 2 and 3A to 3D. Figure 2 is an operation timing diagram drawn according to some embodiments of the present disclosure. As shown in FIG. 2, the working cycle of the pixel circuit 100 includes a reset phase P1, a data writing phase P2, a compensation phase P3, and a light-emitting phase P4. In some embodiments, the reset phase P1, the data writing phase P2, the compensation phase P3, and the light-emitting phase P4 are arranged in a time sequence. In this embodiment, the pixel circuit 100 is applied to a display device. The processor of the display device sequentially drives the pixel circuits 100 of each row. Therefore, S1[n] in Figure 2 represents the gate signal used to control the pixel circuit 100 shown in Figures 3A to 3D, and S1[n-1] represents the gate signal used to drive and the pixel circuit 100 The gate signal of the pixel circuit in the other adjacent row.

請參閱第2及3A圖所示，在重置階段P1中，閘極訊號S1為致能訊號，以導通電晶體開關T3，並流經第二電流I2。由於電晶體開關T3導通，故第一驅動電晶體T1的控制端能透過電晶體開關T3，接收顯 示裝置傳來之輸入訊號Vin，使第一驅動電晶體T1導通，並使第一驅動電晶體T1的控制端被充電至輸入訊號Vin具有的參考電位。 Please refer to Figures 2 and 3A. In the reset phase P1, the gate signal S1 is an enabling signal to turn on the transistor switch T3 and flow the second current I2. Since the transistor switch T3 is turned on, the control terminal of the first drive transistor T1 can receive the input signal Vin from the display device through the transistor switch T3, so that the first drive transistor T1 is turned on and the first drive transistor is turned on The control terminal of T1 is charged to the reference potential of the input signal Vin.

舉例而言，在本實施例中，第一驅動電晶體T1、第二驅動電晶體T2及電晶體開關T3皆為P型TFT(薄膜電晶體)。對於P型TFT而言，禁能準位為高電位、致能準位為低電位。反之，當第一驅動電晶體T1、第二驅動電晶體T2及電晶體開關T3為N型TFT時，禁能準位為低電位、致能準位為高電位。在部分實施例中，輸入訊號Vin之參考電位為低電位，對於第一驅動電晶體T1而言為致能準位，因此，當閘極訊號S1為低電位，用以導通電晶體開關T3後，輸入訊號Vin會將第一節點A控制於低電位，以導通第一驅動電晶體T1。 For example, in this embodiment, the first driving transistor T1, the second driving transistor T2, and the transistor switch T3 are all P-type TFTs (thin film transistors). For P-type TFTs, the disable level is a high potential and the enable level is a low potential. Conversely, when the first driving transistor T1, the second driving transistor T2, and the transistor switch T3 are N-type TFTs, the disable level is a low potential and the enable level is a high potential. In some embodiments, the reference potential of the input signal Vin is a low potential, which is the enable level for the first driving transistor T1. Therefore, when the gate signal S1 is at a low potential, it is used to turn on the transistor switch T3. , The input signal Vin will control the first node A to a low potential to turn on the first driving transistor T1.

此外，在重置階段P1中，電源訊號Vdd為低準位電壓V1，使得第一驅動電晶體T1的第一端接收低電位訊號。由於在重置階段P1中，畫素電路100中的第二節點B(即，發光元件110之正極端)仍維持在前一個工作週期中讓發光元件100發光的電壓值(即，發光階段P4，在本實施例中為高電壓準位)。因此，在重置階段P1的初期，第一驅動電晶體T1之第一端為低電位、第二端為高電位，以使得第一驅動電晶體T1反向導通，使第二節點B開始放電。此時，重置電流Ir自該發光元件110流經第一驅動電晶體T1進 行放電，以進行重置。 In addition, in the reset phase P1, the power signal Vdd is the low-level voltage V1, so that the first terminal of the first driving transistor T1 receives the low-level signal. In the reset phase P1, the second node B in the pixel circuit 100 (that is, the positive terminal of the light-emitting element 110) still maintains the voltage value at which the light-emitting element 100 emits light in the previous working cycle (that is, the light-emitting phase P4). , In this embodiment, the high voltage level). Therefore, at the beginning of the reset phase P1, the first terminal of the first driving transistor T1 is at a low potential and the second terminal is at a high potential, so that the first driving transistor T1 is reversely conducted and the second node B starts to discharge . At this time, the reset current Ir flows from the light-emitting element 110 through the first driving transistor T1 to discharge to perform resetting.

承上，第二節點B的電壓會被放電至與第一節點A的電壓相差一個臨界電壓。在部分實施例中，第一節點A為趨近於零之低電位，故，第二節點B的電壓值即為第一驅動電晶體T1的臨界電壓值Vth，使得第二驅動電晶體T2亦導通，產生第一電流I1。在第二驅動電晶體T2導通的情況下，補償節點C之電壓會被放電至對應於第一驅動電晶體T1之臨界電壓值Vth與第二驅動電晶體T2之臨界電壓值Vth之和。在本實施例中，由於第一驅動電晶體T1之臨界電壓值Vth與第二驅動電晶體T2之臨界電壓值Vth相同，故補償節點C之電壓將為兩倍的Vth。當補償節點C放電到預定值後，第二驅動電晶體T2會變成關斷。 In conclusion, the voltage of the second node B will be discharged to a threshold voltage different from the voltage of the first node A. In some embodiments, the first node A has a low potential approaching zero, so the voltage value of the second node B is the threshold voltage value Vth of the first driving transistor T1, so that the second driving transistor T2 is also Turn on to generate a first current I1. When the second driving transistor T2 is turned on, the voltage of the compensation node C will be discharged to the sum of the threshold voltage value Vth of the first driving transistor T1 and the threshold voltage value Vth of the second driving transistor T2. In this embodiment, since the threshold voltage Vth of the first driving transistor T1 is the same as the threshold voltage Vth of the second driving transistor T2, the voltage of the compensation node C will be twice Vth. When the compensation node C is discharged to a predetermined value, the second driving transistor T2 will turn off.

請再參閱第2及3B圖所示，在資料寫入階段P2中，輸入訊號Vin為高電位之資料訊號Vdata，閘極訊號S1為致能訊號，因此，電晶體開關T3導通，使其第一端接收資料訊號Vdata，且第三電流I3通過電晶體開關T3。此時，由於資料訊號Vdata對於第一驅動電晶體T1為禁能訊號，故第一驅動電晶體T1關斷。在本實施例中，由於重置階段P1時第一節點A的電壓為趨近於零之低電位，因此，當畫素電路100在資料寫入階段P2中接收資料訊號Vdata時，第一節點A的電壓值上升幅度即為資料訊號Vdata之大小。透過第一補償電容C1及第二補償電容C2間的電容耦合效 應，補償節點C之電壓值也將產生相應的變化，即「2Vth+Vdata」，以導通該第二驅動電晶體T2。 Please refer to Figures 2 and 3B again. In the data writing phase P2, the input signal Vin is the high-potential data signal Vdata, and the gate signal S1 is the enable signal. Therefore, the transistor switch T3 is turned on to make the first One end receives the data signal Vdata, and the third current I3 passes through the transistor switch T3. At this time, since the data signal Vdata is a disable signal for the first driving transistor T1, the first driving transistor T1 is turned off. In this embodiment, since the voltage of the first node A is close to zero during the reset phase P1, when the pixel circuit 100 receives the data signal Vdata in the data writing phase P2, the first node The increase in voltage value of A is the magnitude of the data signal Vdata. Through the capacitive coupling effect between the first compensation capacitor C1 and the second compensation capacitor C2, the voltage value of the compensation node C will also change accordingly, namely "2Vth+Vdata" to turn on the second driving transistor T2.

請參閱第2及3C圖，一旦第二驅動電晶體T2導通並產生第四電流I4，補償節點C將透過第二驅動電晶體T2放電，使畫素電路進入補償階段P3。在補償階段P3中，閘極訊號S1為禁能訊號，以關斷電晶體開關T3。第一驅動電晶體T1及第二驅動電晶體T2皆為導通之狀態。此時，由於畫素電路100停止接收資料訊號Vdata，因此，第一節點A的電壓值將成為可變動的狀態。補償節點C的電壓值會透過第二驅動電晶體T2進行放電，使得第一驅動電晶體T1的控制端(即，第一節點A)的電壓值相應於補償節點C之電壓變化而下降。 Please refer to FIGS. 2 and 3C. Once the second driving transistor T2 is turned on and a fourth current I4 is generated, the compensation node C will discharge through the second driving transistor T2, so that the pixel circuit enters the compensation phase P3. In the compensation phase P3, the gate signal S1 is a disable signal to turn off the transistor switch T3. The first driving transistor T1 and the second driving transistor T2 are both in a conducting state. At this time, since the pixel circuit 100 stops receiving the data signal Vdata, the voltage value of the first node A will become a variable state. The voltage value of the compensation node C is discharged through the second driving transistor T2, so that the voltage value of the control terminal of the first driving transistor T1 (ie, the first node A) decreases corresponding to the voltage change of the compensation node C.

在部分實施例中，由於第一驅動電晶體T1的臨界電壓值Vth與第二驅動電晶體T2的臨界電壓值Vth相匹配，因此，補償節點C會放電至電壓等於兩倍的臨界電壓值Vth為止，且此時補償節點C的電壓實質上為第二驅動電晶體T2之控制端的電壓的兩倍。亦即，補償節點C將由「2Vth+Vdata」下降至「2Vth」，電壓的變化幅度為「Vdata」。透過第一補償電容C1及第二補償電容C2間的電容耦合效應，第一節點A的電壓值亦將產生相應變化。由於在本實施例中，第一補償電容C1及第二補償電容C2的電容值相同，因此，根據分壓定律，第一節點A的電壓值變化應為「Vdata」 的一半，即第一節點A的電壓會變成0.5Vdata。 In some embodiments, since the threshold voltage value Vth of the first driving transistor T1 matches the threshold voltage value Vth of the second driving transistor T2, the compensation node C is discharged to a voltage equal to twice the threshold voltage value Vth So far, and at this time, the voltage of the compensation node C is substantially twice the voltage of the control terminal of the second driving transistor T2. That is, the compensation node C will drop from "2Vth+Vdata" to "2Vth", and the voltage variation range is "Vdata". Through the capacitive coupling effect between the first compensation capacitor C1 and the second compensation capacitor C2, the voltage value of the first node A will also change accordingly. Since in this embodiment, the capacitance values of the first compensation capacitor C1 and the second compensation capacitor C2 are the same, according to the law of voltage division, the voltage value of the first node A should change to half of "Vdata", that is, the first node The voltage of A will become 0.5Vdata.

在發光階段P4中，第一驅動電晶體T1及該第二驅動電晶體T2皆導通，以分別流經第五電流I5及第六電流I6。閘極訊號S1則維持禁能訊號，使電晶體開關T3關斷，使得第一驅動電晶體T1的控制端的電壓值相應於補償節點C之電壓變化而上升。在部分實施例中，電源訊號Vdd會被提升成高準位電壓Vh，以改變第二節點B之電壓值，確保第二驅動電晶體T2亦被導通。補償節點C能透過第二驅動電晶體T2，被電源訊號Vdd充電至高準位電壓Vh。亦即，補償節點C之電壓將從2Vth上升成Vh，電壓變化幅度為「Vh-2Vth」，如前所述，此時第一節點A的電壓將為補償節點C之電壓變化幅度的一半，因此第一節點A的電壓會變成「0.5Vdata+0.5Vh-Vth」。 In the light-emitting phase P4, the first driving transistor T1 and the second driving transistor T2 are both turned on to flow through the fifth current I5 and the sixth current I6, respectively. The gate signal S1 maintains the disable signal to turn off the transistor switch T3, so that the voltage value of the control terminal of the first driving transistor T1 rises corresponding to the voltage change of the compensation node C. In some embodiments, the power signal Vdd is raised to a high-level voltage Vh to change the voltage value of the second node B to ensure that the second driving transistor T2 is also turned on. The compensation node C can be charged to the high level voltage Vh by the power signal Vdd through the second driving transistor T2. That is, the voltage of the compensation node C will rise from 2Vth to Vh, and the voltage change range will be "Vh-2Vth". As mentioned above, the voltage of the first node A will be half of the voltage change range of the compensation node C. Therefore, the voltage of the first node A becomes "0.5Vdata+0.5Vh-Vth".

根據電晶體的電流公式「I=K×(Vsg-Vth)2」，其中，K代表第一驅動電晶體T1的載子遷移率(carrier mobility)、閘極氧化層的單位電容大小以及閘極寬長比三者的乘積。Vsg為第一驅動電晶體T1之第二端(源極)及控制端之間的電壓差。Vth則為第一驅動電晶體T1的臨界電壓值。由於在第一驅動電晶體T1導通時，其第一端及第二端可視為短路，因此，第一驅動電晶體T1之第二端(源極)可視為高準位電壓Vh。前述公式能被整理為「I=K×(Vdd-(0.5Vdata+0.5Vh-Vth)-Vth)2」。由於電流I與臨界電壓 值Vth無關，因此能確保發光二極體110的發光強度不會因為臨界電壓值Vt的變異而受到影響。 According to the current formula of the transistor "I=K×(Vsg-Vth) 2 ", K represents the carrier mobility of the first driving transistor T1, the unit capacitance of the gate oxide layer and the gate The product of the three aspect ratios. Vsg is the voltage difference between the second terminal (source) and the control terminal of the first driving transistor T1. Vth is the threshold voltage value of the first driving transistor T1. When the first driving transistor T1 is turned on, the first terminal and the second terminal of the first driving transistor T1 can be regarded as a short circuit. Therefore, the second terminal (source) of the first driving transistor T1 can be regarded as the high-level voltage Vh. The aforementioned formula can be sorted into "I=K×(Vdd-(0.5Vdata+0.5Vh-Vth)-Vth) 2 ". Since the current I has nothing to do with the threshold voltage value Vth, it can be ensured that the luminous intensity of the light emitting diode 110 will not be affected by the variation of the threshold voltage value Vt.

請參閱第2圖所示之運作時序圖，在本實施例中，顯示裝置中的所有畫素電路100在同一時間進入重置階段P1，接著，在資料寫入階段P2中，不同排的畫素電路100會依序接收資料訊號Vdata。在所有畫素電路100皆完成資料寫入階段P2後，再於同一時間進入補償階段P3。在部分實施例中，在補償階段P3後還有一個緩衝階段P31。透過緩衝階段P31，顯示裝置能確保所有的畫素電路100都完成補償後，再統一進入發光階段P4，使每個畫素電路都能產生預期之理想光亮。緩衝階段P31之時間長短係根據第一驅動電晶體T1及第二驅動電晶體T2的特性。在其他部分實施例中，亦可在補償階段P3後直接進入發光階段P4。 Please refer to the operation timing diagram shown in Figure 2. In this embodiment, all the pixel circuits 100 in the display device enter the reset phase P1 at the same time. Then, in the data writing phase P2, different rows of pictures The pixel circuit 100 sequentially receives the data signal Vdata. After all the pixel circuits 100 complete the data writing phase P2, they enter the compensation phase P3 at the same time. In some embodiments, there is a buffer phase P31 after the compensation phase P3. Through the buffer stage P31, the display device can ensure that all the pixel circuits 100 are compensated, and then enter the light-emitting stage P4 uniformly, so that each pixel circuit can generate the desired ideal light. The duration of the buffer phase P31 is based on the characteristics of the first driving transistor T1 and the second driving transistor T2. In some other embodiments, it is also possible to enter the light-emitting phase P4 directly after the compensation phase P3.

如前所述，在畫素電路100的工作週期中，可透過控制輸入訊號Vin的輸入與否(如：改變閘極訊號S1)，使畫素電路100進入不同操作時序。畫素電路100具有3T2C的精簡架構(即，包含三個電晶體及兩個電容)，能減少電路成本，且使其更易於控制。此外，當畫素電路未處於發光階段P4時，電源訊號Vdd皆被控制於低準位電壓V1，能避免顯示裝置出現閃爍的異常現象。 As mentioned above, during the working cycle of the pixel circuit 100, the pixel circuit 100 can enter different operation timings by controlling whether the input signal Vin is input or not (eg, changing the gate signal S1). The pixel circuit 100 has a 3T2C streamlined architecture (that is, includes three transistors and two capacitors), which can reduce the circuit cost and make it easier to control. In addition, when the pixel circuit is not in the light-emitting phase P4, the power signal Vdd is controlled to the low level voltage V1, which can avoid the abnormal phenomenon of flicker in the display device.

雖然本揭示內容已以實施方式揭露如上，然其並非用以限定本發明內容，任何熟習此技藝者，在 不脫離本發明內容之精神和範圍內，當可作各種更動與潤飾，因此本發明內容之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the content of the present invention. Anyone who is familiar with the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection of the content shall be subject to the scope of the attached patent application.

100‧‧‧畫素電路 100‧‧‧Pixel circuit

110‧‧‧發光二極體 110‧‧‧Light Emitting Diode

T1‧‧‧第一驅動電晶體 T1‧‧‧First driving transistor

T2‧‧‧第二驅動電晶體 T2‧‧‧Second driving transistor

T3‧‧‧電晶體開關 T3‧‧‧Transistor Switch

C1‧‧‧第一補償電容 C1‧‧‧First compensation capacitor

C2‧‧‧第二補償電容 C2‧‧‧Second compensation capacitor

A‧‧‧第一節點 A‧‧‧First node

B‧‧‧第二節點 B‧‧‧Second node

C‧‧‧補償節點 C‧‧‧Compensation node

Vdd‧‧‧電源訊號 Vdd‧‧‧Power signal

Vss‧‧‧參考電壓源 Vss‧‧‧Reference voltage source

S1‧‧‧閘極訊號 S1‧‧‧Gate signal

Vin‧‧‧輸入訊號 Vin‧‧‧Input signal

Claims (15)

一種畫素電路，包含：一發光元件；一第一驅動電晶體，具有一第一端、一第二端與一控制端，其中該第一驅動電晶體的該第一端用以接收一電源訊號，該第一驅動電晶體的該第二端電性連接至該發光元件；一第二驅動電晶體，具有一第一端、一第二端與一控制端，其中該第二驅動電晶體的該第一端用以接收該電源訊號，該第二驅動電晶體的該控制端電性連接至該發光元件；以及一第一補償電容，分別電性連接於該第一驅動電晶體的該控制端與該第二驅動電晶體之該第二端之間。 A pixel circuit comprising: a light-emitting element; a first driving transistor having a first end, a second end and a control end, wherein the first end of the first driving transistor is used for receiving a power source Signal, the second terminal of the first driving transistor is electrically connected to the light-emitting element; a second driving transistor has a first terminal, a second terminal and a control terminal, wherein the second driving transistor The first terminal is used to receive the power signal, the control terminal of the second driving transistor is electrically connected to the light-emitting element; and a first compensation capacitor is electrically connected to the first driving transistor. Between the control terminal and the second terminal of the second driving transistor. 如請求項1所述之畫素電路，其中該第二驅動電晶體的該第二端透過一補償節點，電性連接至該第一補償電容，且該第一驅動電晶體及該第二驅動電晶體之臨界電壓值相互匹配。 The pixel circuit according to claim 1, wherein the second end of the second driving transistor is electrically connected to the first compensation capacitor through a compensation node, and the first driving transistor and the second driving transistor The threshold voltage values of the transistors match each other. 如請求項2所述之畫素電路，更包含：一第二補償電容，具有一第一端與一第二端，且該第二補償電容的該第一端電性連接至一參考電壓源，該第二補償電容的該第二端電性連接至該第一驅動電晶體之該控制端。 The pixel circuit according to claim 2, further comprising: a second compensation capacitor having a first terminal and a second terminal, and the first terminal of the second compensation capacitor is electrically connected to a reference voltage source The second end of the second compensation capacitor is electrically connected to the control end of the first driving transistor. 如請求項3所述之畫素電路，其中，該第一驅動電晶體該第二驅動電晶體之臨界電壓值具有一第一匹配關係，該第一補償電容及該第二補償電容之電容值具有一第二匹配關係，且該第一匹配關係與該第二匹配關係相同。 The pixel circuit according to claim 3, wherein the threshold voltage values of the first driving transistor and the second driving transistor have a first matching relationship, and the capacitance values of the first compensation capacitor and the second compensation capacitor There is a second matching relationship, and the first matching relationship is the same as the second matching relationship. 如請求項4所述之畫素電路，其中，該第一驅動電晶體與該第二驅動電晶體具有相同之臨界電壓值，該第一補償電容及該第二補償電容具有相同之電容值。 The pixel circuit according to claim 4, wherein the first driving transistor and the second driving transistor have the same threshold voltage value, and the first compensation capacitor and the second compensation capacitor have the same capacitance value. 如請求項1所述之畫素電路，更包含：一電晶體開關，具有一第一端、一第二端與一控制端，該電晶體開關的該第一端用以接收一資料訊號，該電晶體開關的該第二端電性連接至該第一驅動電晶體之該控制端，該電晶體開關的該控制端用以接收一閘極訊號。 The pixel circuit according to claim 1, further comprising: a transistor switch having a first terminal, a second terminal and a control terminal, the first terminal of the transistor switch is used for receiving a data signal, The second terminal of the transistor switch is electrically connected to the control terminal of the first driving transistor, and the control terminal of the transistor switch is used for receiving a gate signal. 一種畫素電路，包含：一發光元件；一第一驅動電晶體，具有一第一端、一第二端與一控制端，其中該第一驅動電晶體的該第二端電性連接至該發光元件； 一第二驅動電晶體，具有一第一端、一第二端與一控制端，其中該第二驅動電晶體的該控制端電性連接至該發光元件；以及一第一補償電容，分別電性連接於該第一驅動電晶體的該控制端與該第二驅動電晶體的該第二端之間，且該第一補償電容及該第二驅動電晶體之間為一補償節點；其中，於一資料寫入階段中，該第一驅動電晶體的該控制端用以接收一資料訊號；其中，於一補償階段中，該補償節點之電壓實質上為兩倍的該第二驅動電晶體的控制端的電壓。 A pixel circuit comprising: a light-emitting element; a first driving transistor having a first end, a second end and a control end, wherein the second end of the first driving transistor is electrically connected to the Light-emitting element A second driving transistor has a first terminal, a second terminal and a control terminal, wherein the control terminal of the second driving transistor is electrically connected to the light-emitting element; and a first compensation capacitor, respectively Is electrically connected between the control terminal of the first driving transistor and the second terminal of the second driving transistor, and between the first compensation capacitor and the second driving transistor is a compensation node; wherein, In a data writing phase, the control terminal of the first driving transistor is used to receive a data signal; wherein, in a compensation phase, the voltage of the compensation node is substantially twice that of the second driving transistor The voltage of the control terminal. 如請求項7所述之畫素電路，其中，於一重置階段中，該第一驅動電晶體導通，且該第一驅動電晶體的該第一端用以接收一低電位訊號，且該第二驅動電晶體亦導通。 The pixel circuit according to claim 7, wherein, in a reset phase, the first driving transistor is turned on, and the first end of the first driving transistor is used to receive a low-level signal, and the The second driving transistor is also turned on. 如請求項8所述之畫素電路，其中，於該重置階段中，該補償節點之電壓係放電至對應於該第一驅動電晶體之臨界電壓值與該第二驅動電晶體之臨界電壓值之和。 The pixel circuit according to claim 8, wherein, in the reset phase, the voltage of the compensation node is discharged to correspond to the threshold voltage value of the first driving transistor and the threshold voltage of the second driving transistor The sum of values. 如請求項7所述之畫素電路，更包含：一第二補償電容，分別電性連接於該第一驅動電晶 體的該控制端及一參考電壓源；其中，於該資料寫入階段中，該第一驅動電晶體關斷，且該第一補償電容及該第二補償電容透過電容耦合效應改變該補償節點之電壓值，以導通該第二驅動電晶體。 The pixel circuit according to claim 7, further comprising: a second compensation capacitor electrically connected to the first driving transistor The control terminal of the body and a reference voltage source; wherein, in the data writing stage, the first driving transistor is turned off, and the first compensation capacitor and the second compensation capacitor change the compensation node through capacitive coupling effect To turn on the second driving transistor. 如請求項10所述之畫素電路，其中，在該補償階段中，該第一驅動電晶體及該第二驅動電晶體皆導通，且該第一補償電容及一第二補償電容透過電容耦合效應，使得該第一驅動電晶體的該控制端的電壓值相應於該補償節點之電壓變化而下降。 The pixel circuit according to claim 10, wherein, in the compensation phase, the first driving transistor and the second driving transistor are both turned on, and the first compensation capacitor and the second compensation capacitor are capacitively coupled The effect causes the voltage value of the control terminal of the first driving transistor to drop corresponding to the voltage change of the compensation node. 如請求項7所述之畫素電路，更包含：一電晶體開關，具有一第一端、一第二端及一控制端，其中，於該資料寫入階段中，該電晶體開關的該第一端用以接收該資料訊號；該電晶體開關的該第二端電性連接於該第一驅動電晶體的該控制端。 The pixel circuit according to claim 7, further comprising: a transistor switch having a first terminal, a second terminal and a control terminal, wherein, in the data writing stage, the transistor switch The first terminal is used for receiving the data signal; the second terminal of the transistor switch is electrically connected to the control terminal of the first driving transistor. 如請求項12所述之畫素電路，其中，於一重置階段中，該電晶體開關導通。 The pixel circuit according to claim 12, wherein, in a reset phase, the transistor switch is turned on. 如請求項12所述之畫素電路，其中，於一發光階段中，該第一驅動電晶體及該第二驅動電晶體皆導通，該電晶體開關關斷。 The pixel circuit according to claim 12, wherein, in a light-emitting phase, the first driving transistor and the second driving transistor are both turned on, and the transistor switch is turned off. 如請求項14所述之畫素電路，其中，該重置階段、該資料寫入階段、該補償階段與該發光階段為依序排列的時序。 The pixel circuit according to claim 14, wherein the reset phase, the data writing phase, the compensation phase and the light-emitting phase are arranged in sequence.
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