TW202001864A - Gate driving apparatus - Google Patents

Abstract

A gate driving apparatus includes a plurality of shift register circuits. In the shift register circuit, an output stage circuit receives the control signal and provides a gate low or high voltage in accordance with the control signal to charge the output to generate a gate drive signal. In a compensation circuit, a transistor receives the latter gate drive signal and the control signal. A first voltage regulator according to a mode selection signal to provide the low or high gate voltage to adjust the control signal. A second voltage regulator according to a switching signal and a reverse clock signal to provide a pre-drive signal or a start pulse signal to adjust the control signal. A third voltage regulator according to the mode selection signal and the control signal to provide the low or a high gate voltage to adjust the control signal. A fourth voltage regulator adjusts the control signal according to the reverse clock signal.

Description

Gate drive

The invention relates to a gate driving device, and in particular to a gate driving device of a display device.

In recent years, many products have integrated the gate driver circuit (Gate driver) in the display driver circuit on the glass, which is the gate-driver-on-array (GOA) circuit. The gate drive circuit on the array has many advantages. It can reduce the width of the frame of the display panel to achieve the effect of a narrow frame, thereby effectively reducing the design area of the internal circuit of the display.

In the display device, since the display screen presented by the display panel is easily affected by the turn-on voltage of the driving transistor in the pixel circuit, the quality of the display screen is reduced. Therefore, the gate driving circuit needs to make the pixel switches of the same column be turned on or off at the same time in the compensation stage to perform compensation operation on the driving transistor. Next, the gate drive circuit needs to turn on the pixel switches row by row during the data writing stage to write the drawing voltage (or pixel data) to the corresponding pixel circuit.

In other words, how to effectively generate a consistent gate drive signal when the gate drive device is operating in the compensation stage, and to sequentially generate the gate drive signals during the data writing stage to improve gate drive The performance of the device will be an important issue for those skilled in the art.

The invention provides a gate drive device, which can enable each gate drive signal at the same time in the compensation phase, and enable each gate drive signal in sequence during the write phase, thereby enhancing the gate drive device efficacy.

The gate driving device of the present invention includes a plurality of shift temporary storage circuits. A plurality of shift register circuits are coupled in series with each other to generate a plurality of gate drive signals, wherein the shift register circuit of the Nth stage includes an output stage circuit, a compensation circuit, and first to fourth voltage regulators. The output stage circuit has a first control terminal and a second control terminal to receive the first control signal and the second control signal, respectively, according to the first control signal and the second control signal to provide the gate low voltage or the gate high voltage to the output terminal Charge to generate the Nth gate drive signal. The compensation circuit is coupled to the first control terminal, wherein the compensation circuit includes a capacitor and a first transistor. The capacitor is coupled between the first control terminal and the first node. The first terminal of the first transistor receives the latter-stage gate driving signal, the second terminal of the first transistor is coupled to the first node, and the control terminal of the first transistor receives the first control signal. The first voltage regulator is coupled to the first control terminal, and provides a gate low voltage or a gate high voltage according to the first mode selection signal and the second mode selection signal to adjust the first control signal. The second voltage regulator is coupled to the first control terminal, and provides a previous-stage gate driving signal or a starting pulse signal according to the switching signal and the reverse clock signal to adjust the first control signal. The third voltage regulator is coupled between the first control terminal and the second control terminal, and provides the gate low voltage or the gate high voltage according to the second mode selection signal and the first control signal to adjust the second control signal. The fourth voltage regulator is coupled to the second control terminal and adjusts the second control signal according to the reverse clock signal.

Based on the above, the shift temporary storage circuit of the gate drive device of the present invention can synchronize the output of the N-th gate drive signal generated by the output stage circuit and the subsequent-stage gate drive signal during the compensation stage. In the writing stage, the N-th gate driving signal and the subsequent-stage gate driving signal generated by the output stage circuit are output in order, thereby improving the performance of the gate driving device.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

The term "coupling (or connection)" used in the entire specification of this case (including the scope of patent application) may refer to any direct or indirect connection means. For example, if it is described that the first device is coupled (or connected) to the second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be connected to another device or a certain device. Connection means indirectly connected to the second device. In addition, wherever possible, elements/components/steps using the same reference numbers in the drawings and embodiments represent the same or similar parts. Elements/components/steps that use the same reference numbers or use the same terminology in different embodiments may refer to related descriptions with each other.

FIG. 1 is a circuit diagram of an Nth-stage shift register circuit according to an embodiment of the invention. The gate driving device of the embodiment of the present invention includes a plurality of shift register circuits, and these shift register circuits are coupled in series with each other to generate a plurality of gate drive signals, respectively. Wherein, the shift register circuit 100 of FIG. 1 represents the shift register circuit of the Nth stage of the gate driving device, and the aforementioned N is a positive integer.

Referring to FIG. 1, in this embodiment, the shift register circuit 100 includes an output stage circuit 110, a compensation circuit 120, and voltage regulators 130-160. The output stage circuit 110 includes transistors M1-M2. The first terminal of the transistor M1 receives the gate low voltage VGL, the second terminal of the transistor M1 is coupled to the output terminal OUT, and the control terminal of the transistor M1 receives the control signal CS1. The first terminal of the transistor M2 is coupled to the output terminal OUT, the second terminal of the transistor M2 receives the gate high voltage VGH, and the control terminal of the transistor M2 receives the control signal CS2.

Specifically, the output stage circuit 110 of this embodiment can receive the control signal CS1 and the control signal CS2 through the control terminal CT1 and the control terminal CT2, respectively. In addition, the output stage circuit 110 can charge the output voltage OUT by the gate low voltage VGL or the gate high voltage VGH according to the control signal CS1 and the control signal CS2, thereby causing the output stage circuit 110 to generate the Nth gate drive signal G [N] The pixel circuit to the back end.

Next, the compensation circuit 120 is coupled to the control terminal CT1. The compensation circuit 120 includes a capacitor C1 and a transistor M3. The capacitor C1 is coupled between the control terminal CT1 and the node P1. Moreover, the first end of the transistor M3 receives the subsequent gate drive signal G[N+1], the second end of the transistor M3 is coupled to the node P1, and the control end of the transistor M3 receives the control signal CS1.

On the other hand, the voltage regulator 130 is coupled to the control terminal CT1. The voltage regulator 130 includes transistors M4-M6. The first terminal of the transistor M4 receives the gate low voltage VGL, the second terminal of the transistor M4 is coupled to the control terminal CT1, and the control terminal of the transistor M4 receives the mode selection signal SS1. The first terminal of the transistor M5 receives the gate high voltage VGH, and the control terminal of the transistor M5 receives the mode selection signal SS2. The first terminal of the transistor M6 is coupled to the second terminal of the transistor M5, the second terminal of the transistor M6 is coupled to the control terminal CT1, and the control terminal of the transistor M6 receives the mode selection signal SS2. Specifically, the voltage regulator 130 of this embodiment may determine to provide the gate low voltage VGL or the gate high voltage VGH to the control terminal CT1 according to the states of the mode selection signal SS1 and the mode selection signal SS2, so that the voltage regulator 130 can adjust the control signal CS1 through the gate low voltage VGL or the gate high voltage VGH.

Next, the voltage regulator 140 is coupled to the control terminal CT1. The voltage regulator 140 includes transistors M7-M8. Among them, the first end of the transistor M7 receives the previous-stage gate drive signal G[N-1] or the start pulse signal ST, and the control end of the transistor M7 receives the reverse clock signal XCLK. The first terminal of the transistor M8 is coupled to the second terminal of the transistor M7, the second terminal of the transistor M8 is coupled to the control terminal CT1, and the control terminal of the transistor M8 receives the switching signal CHA. Specifically, the voltage regulator 140 of this embodiment may determine to provide the previous-stage gate driving signal G[N-1] or the start pulse signal ST to the control terminal according to the switching signal CHA and the reverse clock signal XCLK CT1, so that the voltage regulator 140 can adjust the control signal CS1 through the previous-stage gate driving signal G[N-1] or the start pulse signal ST.

In particular, in this embodiment, when the shift register circuit 100 operates in the compensation stage, the voltage regulator 140 can turn off the transistor M8 according to the switching signal CHA with a high voltage level. In this way, during the compensation stage, the output state of the gate drive signal G[N] output by the output stage circuit 110 can be unaffected by the output state of the previous-stage gate drive signal G[N-1].

On the other hand, the voltage regulator 150 is coupled between the control terminal CT1 and the control terminal CT2. The voltage regulator 150 includes transistors M9-M12. The first terminal of the transistor M9 receives the gate low voltage VGL, the second terminal of the transistor M9 is coupled to the control terminal CT2, and the control terminal of the transistor M9 receives the mode selection signal SS2. The first terminal of the transistor M10 is coupled to the control terminal CT2, the second terminal of the transistor M10 receives the gate high voltage VGH, and the control terminal of the transistor M10 receives the control signal CS1. The first terminal of the transistor M11 is coupled to the control terminal CT1, and the control terminal of the transistor M11 is coupled to the control terminal CT2. The first terminal of the transistor M12 is coupled to the second terminal of the transistor M11, the second terminal of the transistor M12 receives the gate high voltage VGH, and the control terminal of the transistor M12 is coupled to the control terminal CT2. Specifically, the voltage regulator 150 of this embodiment may determine to provide the gate low voltage VGL or the gate high voltage VGH to the control terminal CT2 according to the mode selection signal SS2 and the control signal CS1, so that the voltage regulator 150 can pass through The gate low voltage VGL or the gate high voltage VGH adjusts the control signal CS2.

Next, the voltage regulator 160 is coupled to the control terminal CT2. The voltage regulator 160 includes transistors M13-M14. Wherein, the first end of the transistor M13 and the control end jointly receive the reverse clock signal XCLK. The first terminal of the transistor M14 is coupled to the second terminal of the transistor M13, the second terminal of the transistor M14 is coupled to the control terminal CT2, and the control terminal of the transistor M14 receives the reverse clock signal XCLK. Specifically, the voltage regulator 160 of this embodiment may adjust the control signal CS2 according to the reverse clock signal XCLK. It is worth mentioning that the transistors M13-M14 of this embodiment can form a diode according to the connection mode of the diode configuration (Diode Connection). Wherein, the cathode of the diode (that is, the first end of the transistor M13) receives the reverse clock signal XCLK, and the anode of the diode (that is, the second end of the transistor M14) is coupled to the control端CT2. Incidentally, the transistors M1 to M14 of this embodiment are P-type transistors as an example, but the embodiments of the present invention are not limited thereto.

FIG. 2 is a waveform diagram of the shift register circuit of the Nth stage according to an embodiment of the invention. Referring to FIG. 2, in this embodiment, one pixel period TFR of the shift register circuit 100 can be divided into a compensation stage TC, a writing stage TR, and a voltage holding stage TVH, and a compensation stage TC, a writing stage TR and TVH does not overlap each other in the voltage holding phase. Wherein, the writing phase TR is enabled after the compensation phase TC, and the voltage holding phase TVH is enabled after the writing phase TR.

FIG. 3 is a circuit schematic diagram of the first sub-stage of the Nth-stage shift register circuit in the compensation stage according to an embodiment of the invention. Please refer to FIG. 2 and FIG. 3 at the same time. Specifically, when the shift register circuit 100 operates in the first sub-stage TC_1 of the compensation stage TC, a clock generator (not shown) externally connected to the shift register circuit 100 The clock signal CLK with a high voltage level and the reverse clock signal XCLK with a low voltage level can be provided to the shift register circuit 100. In addition, the shift register circuit 100 can set the mode selection signal SS1 to a low voltage level state, and set the mode selection signal SS2 to a high voltage level state.

In detail, the voltage regulator 130 can transmit the gate low voltage VGL to the control terminal CT1 according to the mode selection signal SS1, so as to lower the voltage level of the control signal CS1. Moreover, the voltage regulator 120 can be turned on according to the control signal CS1 being pulled down. At the same time, the shift register circuit 100 can set the switching signal CHA to a high voltage level state, so that the transistor M8 can be turned off. In this case, the voltage regulator 140 cannot transmit the previous-stage gate driving signal G[N-1] or the start pulse signal ST to the control terminal CT1. In this way, this embodiment can effectively isolate the influence between the previous-stage gate drive signal G[N-1] or the start pulse signal ST and the control signal CS1.

On the other hand, in the first sub-stage TC_1, the voltage regulator 160 may be turned on according to the reverse clock signal XCLK, and charge the control signal CS2. Then, the voltage regulator 150 can transmit the gate high voltage VGH to the control terminal CT2 according to the pulled-down control signal CS1, and then pull the control signal CS2 to the voltage level of the gate high voltage VGH.

In other words, in this embodiment, when the shift register circuit 100 operates in the first sub-stage TC_1, the output stage circuit 110 can provide the gate low voltage VGL to the output terminal OUT according to the pulled-down control signal CS1 The charging action enables the output stage circuit 110 to generate the N-th gate drive signal G[N] with the voltage level of the gate low voltage VGL through the output terminal OUT.

FIG. 4 is a circuit schematic diagram of the second sub-stage of the N-stage shift register circuit in the compensation stage according to an embodiment of the invention. Please refer to FIGS. 2 and 4 at the same time. Specifically, when the shift register circuit 100 operates in the second sub-stage TC_2, the shift register circuit 100 can set both the mode selection signal SS1 and the mode selection signal SS2 to be high voltage Level status. In addition, an external clock generator (not shown) can provide the clock signal CLK and the reverse clock signal XCLK that periodically change state to the shift register circuit 100.

In detail, the voltage regulator 130 can be disconnected according to the mode selection signal SS1 and the mode selection signal SS2, and the voltage regulator 140 can be continuously disconnected according to the switching signal CHA. Then, the compensation circuit 120 can be turned on according to the control signal CS1 being pulled down. It is worth mentioning that, since the later-stage gate drive signal G[N+1] operates at the voltage level of the lower gate voltage VGL, the voltage value at the node P1 can be based on the later-stage gate drive signal G[N+1] is simultaneously pulled down to the voltage level of the gate low voltage VGL. In this way, the compensation circuit 120 can use the coupling effect of the capacitor C1 to adjust the voltage level of the control signal CS1 to the sum of the voltage value of the gate low voltage VGL and a voltage value V1. It should be noted that the voltage value V1 can be expressed as a voltage difference between the on-voltage |VTH4| of the transistor M4 and an offset value ΔV after the coupling effect. That is, the voltage level of the control signal CS1 at this time is VGL+V1=VGL+|VTH4|-△V.

On the other hand, the voltage regulator 160 is periodically turned off according to the reverse clock signal XCLK. Moreover, the voltage regulator 150 can provide the gate high voltage VGH to the control terminal CT2 according to the pulled-down control signal CS1, so that the voltage level of the control signal CS2 can be maintained at the voltage value of the gate high voltage VGH.

In other words, in the present embodiment, when the shift register circuit 100 operates in the second sub-stage TC_2, the output stage circuit 110 can provide the gate low voltage VGL to the output terminal OUT according to the pulled-down control signal CS1 The charging action enables the output stage circuit 110 to generate the N-th gate drive signal G[N] with the voltage level of the gate low voltage VGL through the output terminal OUT.

FIG. 5 is a circuit schematic diagram of the third sub-stage of the shift register circuit of the Nth stage in the compensation stage according to an embodiment of the invention. Please refer to FIGS. 2 and 5 at the same time. Specifically, when the shift register circuit 100 operates in the third sub-stage TC_3 of the compensation stage TC, the shift register circuit 100 can set the mode selection signal SS1 to maintain the high voltage Level state, and set the mode selection signal SS2 to a low voltage level state. In addition, an external clock generator (not shown) can provide a clock signal CLK with a high voltage level and a reverse clock signal XCLK with a low voltage level.

In detail, the voltage regulator 130 can provide the gate high voltage VGH to the control terminal CT1 according to the mode selection signal SS2, so that the voltage level of the control signal CS1 can be pulled up to the voltage value of the gate high voltage VGH. At the same time, the voltage regulator 120 can be turned off according to the pulled-up control signal CS1. In addition, the voltage regulator 140 is continuously turned off according to the switching signal CHA.

On the other hand, the voltage regulator 160 can be turned on according to the reverse clock signal XCLK to charge the control signal CS2. Then, the voltage regulator 150 can provide the gate low voltage VGL to the control terminal CT2 according to the mode selection signal SS2, so that the voltage level of the control signal CS2 is adjusted to the voltage value of the gate low voltage VGL and a voltage value V2 sum. It should be noted that the voltage value V2 can be expressed as the on-voltage |VTH9| of the transistor M9. That is, the voltage level of the control signal CS2 at this time is VGL+ V2=VGL+|VTH9|.

In other words, in the present embodiment, when the shift register circuit 100 operates in the third sub-stage TC_3, the output stage circuit 110 can provide the gate high voltage VGH to the output terminal OUT according to the pulled-down control signal CS2 The charging operation enables the output stage circuit 110 to generate the N-th gate drive signal G[N] having the voltage level of the gate high voltage VGH through the output terminal OUT.

According to the above descriptions of FIGS. 3 to 5, it is clear that during the compensation stage TC, the shift register circuit 100 can open the front gate by setting the switching signal CHA to a high voltage level state. The driving signal G[N-1] is transmitted to the path of the control terminal CT1, so that the gate driving signal G[N] generated by the output stage circuit 110 will not be affected by the previous stage gate driving signal G[N-1] As a result, the gate drive signal G[N] can be output in synchronization with the subsequent gate drive signal G[N+1], thereby improving the performance of the display gate drive device.

FIG. 6 is a circuit schematic diagram of the first sub-stage of the shift register circuit of the Nth stage in the writing stage according to an embodiment of the invention. Please refer to FIGS. 2 and 6 at the same time. Specifically, when the shift register circuit 100 operates in the first sub-stage TR_1 of the writing stage TR, the shift register circuit 100 can set the mode selection signal SS1 and the mode selection signal SS2 is in a high voltage level state. An external clock generator (not shown) can provide a clock signal CLK with a high voltage level and a reverse clock signal XCLK with a low voltage level to the shift register circuit 100.

In detail, the voltage regulator 130 can be turned off according to the mode selection signal SS1 and the mode selection signal SS2. Moreover, the voltage regulator 120 can be turned on according to the control signal CS1 being pulled down. Different from the compensation stage TC, in the writing stage TR, the shift register circuit 100 can set the switching signal CHA to a low voltage level state, so that the voltage regulator 140 can respond to the switching signal CHA and the reverse clock signal XCLK is turned on.

In this case, the voltage regulator 140 can transmit the previous-stage gate drive signal G[N-1] or the start pulse signal ST to the control terminal CT1, so that the voltage level of the control signal CS1 can be pulled down to the gate The sum of the voltage value of the very low voltage VGL and a voltage value V3. It should be noted that the voltage value V3 can be expressed as the on-voltage |VTH7| of the transistor M7. That is, the voltage level of the control signal CS1 at this time is VGL+V3=VGL+|VTH7|.

On the other hand, in the first sub-stage TR_1, the voltage regulator 160 can be continuously turned on according to the pulled-down reverse clock signal XCLK, and continuously charge the control signal CS2. Then, the voltage regulator 150 can transmit the gate high voltage VGH to the control terminal CT2 according to the pulled-down control signal CS1, so that the voltage level of the control signal CS2 can be pulled up to the voltage value of the gate high voltage VGH.

In other words, in the present embodiment, when the shift register circuit 100 operates in the first sub-stage TR_1, the output stage circuit 110 can generate the N-th gate driving signal G[N] according to the pulled-down control signal CS1. Here, the voltage level of the N-th gate drive signal G[N] at this time is the sum of the voltage value of the gate low voltage VGL and a voltage value V4. It should be noted that the voltage value V4 can be expressed as the on-voltage |VTH7| of the transistor M7 and the on-voltage |VTH1| of the transistor M1. That is, the voltage level of the gate drive signal G[N] at this time is VGL+V4=VGL+|VTH7|+|VTH1|.

7 is a circuit schematic diagram of the second sub-stage of the N-stage shift register circuit in the writing stage according to an embodiment of the invention. Please refer to FIGS. 2 and 7 at the same time. Specifically, when the shift register circuit 100 operates in the second sub-stage TR_2 of the writing stage TR, the shift register circuit 100 can set the mode selection signal SS1 and the mode selection signal SS2 continues to maintain a high voltage level. An external clock generator (not shown) can provide a clock signal CLK with a low voltage level and a reverse clock signal XCLK with a high voltage level to the shift register circuit 100.

In detail, the voltage regulator 130 can be continuously disconnected according to the mode selection signal SS1 and the mode selection signal SS2, and the voltage regulator 120 can be disconnected again according to the inverted clock signal XCLK being pulled high. Then, the compensation circuit 120 can be turned on according to the control signal CS1 being pulled down. At the same time, since the later-stage gate drive signal G[N+1] is pulled down to the voltage level VA, the voltage value on the node P1 can be based on the later-stage gate drive signal G[N+1]. It is pulled down to the voltage level VA simultaneously. In this way, the compensation circuit 120 can further adjust the voltage level of the control signal CS1 to the sum of the voltage value of the gate low voltage VGL and a voltage value V5 through the coupling effect of the capacitor C1. It should be noted that the voltage value V5 can be expressed as a voltage difference between the on-voltage |VTH7| of the transistor M7 and an offset value ΔV after the coupling effect. That is, the voltage level of the control signal CS1 at this time is VGL+V5=VGL+|VTH7|-△V.

On the other hand, the voltage regulator 160 can be turned off again according to the pulled up reverse clock signal XCLK. Then, the voltage regulator 150 can provide the gate high voltage VGH to the control terminal CT2 according to the pulled-down control signal CS1 to maintain the voltage level of the control signal CS2 at the gate high voltage VGH.

In other words, in the present embodiment, when the shift register circuit 100 operates in the second sub-stage TR_2, the output stage circuit 110 can provide the gate low voltage VGL to the output terminal OUT according to the pulled-down control signal CS1 The charging action enables the output stage circuit 110 to generate the N-th gate drive signal G[N] with the voltage level of the gate low voltage VGL through the output terminal OUT.

FIG. 8 is a circuit schematic diagram of the Nth-stage shift register circuit in the voltage holding stage according to an embodiment of the invention. Please refer to FIG. 2 and FIG. 8 at the same time. Specifically, when the shift register circuit 100 operates in the voltage holding stage TVH, the shift register circuit 100 can set the mode selection signal SS1 and the mode selection signal SS2 to continue at the high voltage level. Bit state, and an external clock generator (not shown) can provide the clock signal CLK and the reverse clock signal XCLK that periodically change state to the shift register circuit 100.

In detail, the voltage regulator 130 can remain off according to the mode selection signal SS1 and the mode selection signal SS2. At the same time, the voltage regulator 140 can be periodically turned on according to the reverse clock signal XCLK, and the voltage regulator 140 can periodically charge the control signal CS1 to pull the control signal CS1 high. Then, the voltage regulator 120 can be turned off again according to the pulled-up control signal CS1.

On the other hand, the voltage regulator 160 can be turned on periodically according to the reverse clock signal XCLK, and the voltage regulator 160 can periodically charge the control signal CS2 to lower the voltage level of the control signal CS2 .

In other words, in the present embodiment, when the shift register circuit 100 operates in the voltage holding stage TVH, the output stage circuit 110 can provide the gate low voltage VGH according to the pulled-down control signal CS2 to charge the output terminal OUT The operation causes the output stage circuit 110 to generate the N-th gate drive signal G[N] having the voltage level of the gate high voltage VGH through the output terminal OUT.

It should be noted that the above-mentioned high voltage level may be the voltage value of the gate high voltage VGH, and the low voltage level may be the voltage value of the gate low voltage VGL.

According to the above descriptions of FIGS. 6 to 8, it can be clearly understood that during the writing stage TR, the shift register circuit 100 can make the control signal CS1 be pulled down synchronously through the coupling effect of the capacitor C1, thereby enabling The gate driving signal G[N] and the subsequent-stage gate driving signal G[N+1] can be output in sequence, thereby improving the performance of the gate driving device.

In summary, the shift temporary storage circuit of the gate driving device of the present invention can synchronize the output of the Nth stage gate driving signal and the latter stage gate driving signal generated by the output stage circuit during the compensation stage. In the writing stage, the N-th gate driving signal and the subsequent-stage gate driving signal generated by the output stage circuit are output in order, thereby improving the performance of the gate driving device.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100‧‧‧ Shift temporary storage circuit 110‧‧‧ Output stage circuit 120‧‧‧ Compensation circuit 130～160‧‧‧Voltage regulator CT1～CT2‧Control terminal CS1～CS2‧‧‧‧Control signal CHA‧‧ ‧Switching signal C1‧‧‧Capacitance G[N-1]～G[N+1]‧‧‧Gate drive signal M1～M14‧‧‧Transistor OUT‧‧‧Output P1‧‧‧Node VGL‧‧ ‧Gate low voltage VGH‧‧‧Gate high voltage SS1～SS2 ‧‧‧ Mode selection signal ST‧‧‧Start pulse signal TFR‧‧‧Pixel period TC‧‧‧Compensation stage TR‧‧‧Write Stage TVH‧‧‧Voltage holding stage TC_1～TC_3, TR_1～TR_2‧‧‧Substage V1～V5‧‧‧Voltage value VA‧‧‧Voltage level XCLK‧‧‧Reverse clock signal

FIG. 1 is a circuit diagram of an Nth-stage shift register circuit according to an embodiment of the invention. FIG. 2 is a waveform diagram of the shift register circuit of the Nth stage according to an embodiment of the invention. FIG. 3 is a circuit schematic diagram of the first sub-stage of the Nth-stage shift register circuit in the compensation stage according to an embodiment of the invention. FIG. 4 is a circuit schematic diagram of the second sub-stage of the N-stage shift register circuit in the compensation stage according to an embodiment of the invention. FIG. 5 is a circuit schematic diagram of the third sub-stage of the shift register circuit of the Nth stage in the compensation stage according to an embodiment of the invention. FIG. 6 is a circuit schematic diagram of the first sub-stage of the shift register circuit of the Nth stage in the writing stage according to an embodiment of the invention. 7 is a circuit schematic diagram of the second sub-stage of the N-stage shift register circuit in the writing stage according to an embodiment of the invention. FIG. 8 is a circuit schematic diagram of the Nth-stage shift register circuit in the voltage holding stage according to an embodiment of the invention.

100‧‧‧shift temporary storage circuit

110‧‧‧ output stage circuit

120‧‧‧Compensation circuit

130~160‧‧‧Voltage regulator

CT1~CT2‧‧‧Control terminal

CS1~CS2‧‧‧Control signal

CHA‧‧‧switch signal

C1‧‧‧Capacitance

G[N-1]~G[N+1]‧‧‧Gate drive signal

M1~M14‧‧‧Transistor

OUT‧‧‧Output

P1‧‧‧ Node

VGL‧‧‧gate low voltage

VGH‧‧‧gate high voltage

SS1~SS2‧‧‧Mode selection signal

ST‧‧‧Start pulse signal

XCLK‧‧‧Reverse clock signal

Claims (17)

A gate drive device includes: a plurality of shift register circuits, which are coupled in series to each other, and generate a plurality of gate drive signals, wherein the shift register circuit of the Nth stage includes: a The output stage circuit has a first control terminal and a second control terminal to receive a first control signal and a second control signal respectively, and to provide a gate low voltage according to the first control signal and the second control signal Or a gate high voltage to an output terminal to generate an N-th gate drive signal; a compensation circuit coupled to the first control terminal, wherein the compensation circuit includes: a capacitor coupled to the first control Between a terminal and a first node; and a first transistor, the first terminal of which receives a subsequent gate drive signal, the second terminal of the first transistor is coupled to the first node, the first The control terminal of the crystal receives the first control signal; a first voltage regulator, coupled to the first control terminal, provides the gate low voltage or the second mode selection signal according to a first mode selection signal and a second mode selection signal The gate high voltage adjusts the first control signal; a second voltage regulator, coupled to the first control terminal, provides a previous-stage gate drive signal or together according to a switching signal and a reverse clock signal The first pulse signal to adjust the first control signal; a third voltage regulator, coupled between the first control terminal and the second control terminal, according to the second mode selection signal and the first control signal to Providing the gate low voltage or the gate high voltage to adjust the second control signal; and a fourth voltage regulator, coupled to the second control terminal, to adjust the second control according to the reverse clock signal signal. The gate drive device according to item 1 of the patent application scope, wherein in a compensation stage, the second voltage regulator is cut off according to the switching signal, and the first voltage regulator is based on the first mode selection signal The gate low voltage is provided to pull down the first control signal. The gate drive device as claimed in item 2 of the patent application, wherein in the compensation stage, the fourth transmission channel is turned on according to the reverse clock signal, and the third transmission channel is provided according to the first control signal The gate voltage is high to pull up the second control signal. The gate drive device as described in item 3 of the patent application range, wherein in the compensation stage, the output stage circuit provides the gate low voltage to the output terminal according to the first control signal. The gate drive device as described in item 2 of the patent application scope, wherein the first voltage regulator is turned off according to the first mode selection signal and the second mode selection signal in a first sub-stage of a writing stage On, the second voltage regulator is turned on according to the switching signal and the inverted clock signal pulled down to transmit the previous-stage gate drive signal or the starting pulse signal to pull down the first control signal. The gate drive device as described in item 5 of the patent application range, wherein in the first sub-stage of the writing stage, the fourth transmission channel is turned on according to the reverse clock signal, and the third transmission channel is based on The first control signal provides the gate high voltage to pull up the second control signal. The gate drive device as described in item 5 of the patent application scope, wherein in a second sub-stage of the writing stage, the second transmission channel is cut off according to the reverse clock signal being pulled up, the The first control signal is pulled down by an offset value according to the gate low voltage. The gate drive device as described in item 7 of the patent application range, wherein the output stage circuit provides the gate low voltage to the output terminal according to the first control signal. The gate drive device according to item 2 of the patent application scope, wherein in a voltage holding stage, the second voltage regulator is periodically turned on according to the reverse clock signal, and periodically responds to the first control signal During charging, the first voltage regulator remains cut off, the fourth voltage regulator is periodically turned on according to the reverse clock signal, and periodically charges the second control signal. The gate drive device as described in item 9 of the patent application range, wherein in the voltage holding stage, the output stage circuit provides the gate high voltage according to the second control signal. The gate drive device as described in item 1 of the patent application scope, wherein the output stage circuit includes: a second transistor whose first end receives the low voltage of the gate, and the second end of the second transistor is coupled To the output end, the control end of the second transistor receives the first control signal; and a third transistor, the first end of which is coupled to the output end, and the second end of the third transistor receives the gate Very high voltage, the control terminal of the third transistor receives the second control signal. The gate driving device as described in item 1 of the patent application range, wherein the first voltage regulator includes: a second transistor whose first terminal receives the low voltage of the gate and the second terminal of the second transistor Coupled to the first control terminal, the control terminal of the second transistor receives the first mode selection signal; and at least a third transistor, coupled between the first control terminal and the gate high voltage, The control terminal of the at least one third transistor receives the second mode selection signal. The gate drive device as described in item 1 of the patent application, wherein the second voltage regulator includes: a second transistor whose first end receives the previous-stage gate drive signal or the starting pulse signal, The control of the second transistor receives the reverse clock signal; and a third transistor, the first end of which is coupled to the second end of the second transistor, and the second end of the third transistor is coupled To the first control terminal, the control terminal of the third transistor receives the switching signal. The gate drive device as described in item 1 of the patent application scope, wherein the third voltage regulator includes: a second transistor whose first end receives the low voltage of the gate and the second end of the second transistor Coupled to the second control terminal, the control terminal of the second transistor receives the second mode selection signal; a third transistor, the first terminal of which is coupled to the second control terminal, the third transistor The second terminal receives the gate high voltage, the control terminal of the third transistor receives the first control signal; a fourth transistor, the first terminal of which is coupled to the first control terminal, the fourth transistor The control terminal is coupled to the second control terminal; and a fifth transistor, the first terminal of which is coupled to the second terminal of the fourth transistor, and the second terminal of the fifth transistor receives the gate high voltage The control terminal of the fifth transistor is coupled to the second control terminal. The gate drive device as described in item 1 of the patent application scope, wherein the fourth voltage regulator includes: a diode whose cathode receives the reverse clock signal and whose anode is coupled to the second control terminal. The gate drive device according to item 15 of the patent application scope, wherein the diode includes: a second transistor whose first terminal and control terminal receive the reverse clock signal; and a third transistor, The first terminal is coupled to the second terminal of the second transistor, the second terminal of the third transistor is coupled to the second control terminal, and the control terminal of the third transistor receives the reverse clock signal . The gate drive device as described in item 1 of the patent application scope, wherein the gate drive signals are simultaneously enabled during a compensation phase, and the gate drive signals are sequentially enabled during a write phase, In a voltage holding phase, the gate drive signals are kept at the disabled voltage value, wherein the compensation phase, the writing phase, and the voltage holding phase occur in sequence.

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