TWI607450B - Shift register and gate driving circuit using the same - Google Patents

Description

Shift register and gate drive circuit using same

The present invention relates to related art of displays, and more particularly to a shift register and a gate drive circuit using the above shift register.

The gate driving circuit used in the display is composed of a plurality of shift registers, each shift register is configured to output a gate signal, and a pulse is provided through the gate signal to turn on the corresponding column. The pixels are such that each pixel in the column of pixels can be written to the desired grayscale value.

However, in the conventional shift register circuit architecture, when the shift register shifts the pulse supplied from the high level to the low level, the falling time of the bit pulse is often too long. Causes the pixels to write incorrect grayscale values, which in turn affects display quality. This disadvantage is especially noticeable in high-resolution displays.

It is an object of the present invention to provide a shift register that can reduce the fall time of the pulses it provides.

Another object of the present invention is to provide a gate driving circuit using the above shift register.

The invention provides a shift register comprising an input signal selection circuit, an output circuit, a pull-down circuit and a voltage boost circuit. The input signal selection circuit is coupled to a node, a first signal source, a second signal source, a first input signal source, and a second input signal source. The output circuit is coupled to the node, the output of the shift register, and the first clock signal source. The pull-down circuit is coupled to the output terminal, the second clock signal source and the reference potential source. The voltage boosting circuit is coupled to the node, the output terminal, the first signal source, the second signal source, the third signal source, and the fourth signal source.

The invention further provides a gate driving circuit comprising a plurality of shift registers, each shift register further comprising an input signal selection circuit, an output circuit, a pull-down circuit and a voltage boost circuit. The input signal selection circuit is coupled to a node for determining whether to connect the node to the first input signal source according to the signal of the first signal source, and configured to determine whether to connect the node according to the signal of the second signal source To the second input signal source. The output circuit is coupled to the output end of the node and the shift register for determining whether to provide the signal of the first clock signal source to the output terminal according to the voltage of the node. The pull-down circuit is coupled to the output end for determining whether to connect the output end to the reference potential source according to the signal of the second clock signal source, wherein the signal of the second clock signal source and the signal of the first clock signal source The enabling times do not overlap each other. The voltage boosting circuit is coupled to the node and the output end, and is configured to determine whether to provide the first coupling voltage of the node according to the signal of the first signal source, the signal of the third signal source, and the voltage of the output terminal, and is configured to be based on the first signal The source signal, the signal of the third signal source, the signal of the fourth signal source, the signal of the second signal source and the voltage of the output terminal determine whether to provide the second coupling voltage of the node.

The shift register of the present invention prior to converting the pulse provided by the high level to the low level, since the node has been first used by the voltage boosting circuit (which can be regarded as the driving transistor in the shift register) The voltage of the same gate of the gate is raised to a higher level than that of the conventional shift register circuit structure, so that the output of the shift register can be discharged faster through the driving transistor. Shorten the fall time of the pulse provided by the shift register.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

For the sake of easy understanding of the reader, the gate driving circuit of the present invention will be described below. 1 is a circuit diagram of a shift register according to an embodiment of the present invention. As shown in FIG. 1, the gate drive circuit is composed of a plurality of shift registers, which are only shown in FIG. The n-3th shift register to the n+3 shift register, and only the complete coupling mode of the nth shift register is shown, and the rest of the shift register The complete coupling method can be analogized according to the following description, and will not be described here.

As shown in FIG. 1, the n-2th shift register, the nth shift register, and the n+2 shift register are all receiving clock signals CK1 and CK3, and the n-th The 3-level shift register, the n-1th shift register, the n+1th shift register, and the n+3 shift register are all receiving clock signals CK2 and CK4. That is to say, the odd-level shift registers are all receiving the clock signals CK1 and CK3, and the even-stage shift registers are receiving the clock signals CK2 and CK4; or, the odd-level shifts are temporarily stored. The receivers receive the clock signals CK2 and CK4, and the even-stage shift registers are the receive clock signals CK1 and CK3.

The n-3th shift register to the n+3 shift register are respectively used to output the gate signal G[n-3]~G[n+3]. In addition, each stage shift register also receives the gate signal output by the previous two-stage shift register and the gate signal output by the second stage shift register. Taking the nth stage shift register as an example, it also receives the gate signal G[n-2] outputted by the n-2th stage shift register, and the n-1th stage shift register. The output gate signal G[n-1], the gate signal G[n+1] outputted by the n+1th stage shift register, and the gate outputted by the n+2 stage shift register Signal G[n+2].

Next, the implementation of the shift register described above will be explained, and the n-th shift register will be exemplified. 2 is a circuit diagram of a shift register according to an embodiment of the present invention. As shown in FIG. 2, the shift register includes an input signal selection circuit 110, an output circuit 120, a pull-down circuit 130, and a voltage boost circuit. 140, the voltage stabilizing circuit 150 and the voltage stabilizing control circuit 160. The input signal selection circuit 110 is coupled to the node Q, the first signal source, the second signal source, the first input signal source, and the second input signal source. The input signal selection circuit 110 is configured to determine whether to connect the node Q to the first input signal source according to the signal of the first signal source, and to determine whether to connect the node Q to the second according to the signal of the second signal source. Enter the source of the signal. In this example, the first signal source is used to provide the gate signal G[n-2] outputted by the n-2th stage shift register, and the second signal source is used to provide the n+2 stage shift. The gate signal G[n+2] outputted by the memory, the first input signal source is used to provide a high level voltage U2D, for example, the power supply voltage VDD, and the second input signal source is used to provide The low level voltage D2U, for example, is the reference potential VSS.

The output circuit 120 is coupled to the node Q, the output terminal 170 of the shift register, and the first clock signal source. The output circuit 120 is configured to determine whether to provide the signal of the first clock signal source according to the voltage of the node Q. The above output terminal 170. In this example, the first clock signal source is used to provide the clock signal CK3. The pull-down circuit 130 is coupled to the output terminal 170, the second clock signal source and the reference potential source. The pull-down circuit 130 is configured to determine whether to connect the output terminal 170 to the reference potential source according to the signal of the second clock signal source. In this example, the second clock signal source is used to provide the clock signal CK1, and the reference potential source is used to provide the reference potential VSS. In addition, the pulse enable times of the clock signals CK1 and CK3 do not overlap each other.

The voltage boosting circuit 140 is coupled to the node Q, the output terminal 170, the first signal source, the second signal source, the third signal source, and the fourth signal source. The voltage boosting circuit 140 is configured to use the signal according to the first signal source. The signal of the third signal source and the voltage of the output terminal 170 determine whether to provide the first coupling voltage of the node Q, and are used according to the signal of the first signal source, the signal of the third signal source, the signal of the fourth signal source, and the second signal source. The signal and the voltage of the output terminal 170 determine whether to provide the second coupling voltage of the node Q. As described above, the first signal source is used to provide the gate signal G[n-2] outputted by the n-2th stage shift register, and the second signal source is used to provide the n+2th stage shift register. The gate signal G[n+2] is output. In addition, in this example, the third signal source is used to provide the gate signal G[n-1] outputted by the n-1th stage shift register, and the fourth signal source is used to provide the n+1th level. The gate signal G[n+1] output by the shift register.

The voltage stabilizing circuit 150 is coupled to the node Q, the output terminal 170, the voltage stabilizing control signal source and the reference potential source. The voltage stabilizing circuit 150 is configured to determine whether to connect the node Q and the output terminal 170 according to the signal of the voltage stabilization control signal source. Reference potential source. As before, the reference potential source is used to provide the reference potential VSS. In addition, in this example, the regulated control signal source is used to provide the regulated control signal P[n]. The voltage regulator control circuit 160 is coupled to the voltage regulator circuit 150, the first clock signal source and the node Q. The voltage regulator control circuit 160 is configured to provide voltage regulation according to the signal of the first clock signal source and the voltage of the node Q. Signal source. As described above, the first clock signal source is used to provide the clock signal CK3, and the voltage stabilization control signal source is used to provide the voltage stabilization control signal P[n].

Next, the implementation of the input signal selection circuit 110, the output circuit 120, the pull-down circuit 130, the voltage up circuit 140, the voltage stabilization circuit 150, and the voltage stabilization control circuit 160 will be further described. Please refer to FIG. The input signal selection circuit 110 includes transistors 111 and 112. The first end of the transistor 111 is coupled to the first input signal source to receive the high level voltage U2D provided by the first input signal source. The second end of the transistor 111 is coupled to the node Q to receive the signal Q[n] on the node Q. The control terminal of the transistor 111 is coupled to the first signal source to receive the gate signal G[n-2] provided by the first signal source. The first end of the transistor 112 is coupled to the second input signal source to receive the low level voltage D2U provided by the second input signal source. The second end of the transistor 112 is coupled to the node Q to receive the signal Q[n] on the node Q. The control end of the transistor 112 is coupled to the second signal source to receive the gate signal G[n+2] provided by the second signal source.

The output circuit 120 includes a transistor 121 (which serves as a driving transistor). The first end of the transistor 121 is coupled to the first clock signal source to receive the clock signal CK3 provided by the first clock signal source. The second end of the transistor 121 is coupled to the output terminal 170, and the control end of the transistor 121 is coupled to the node Q to receive the signal Q[n] on the node Q. The pull-down circuit 130 includes a transistor 131. The first end of the transistor 131 is coupled to the output terminal 170, and the second end of the transistor 131 is coupled to the reference potential source to receive the reference potential VSS provided by the reference potential source, and the control end of the transistor 131 is coupled to the second terminal. The pulse signal source receives the clock signal CK1 provided by the second clock signal source.

The voltage boost circuit 140 includes a capacitor 141, a capacitor 142, a transistor 143, and a transistor 144. The first end of the capacitor 141 is coupled to the node Q, the first end of the capacitor 142 is coupled to the second end of the capacitor 141, and the second end of the capacitor 142 is coupled to the output end 170. The first end of the transistor 143 is coupled to the third signal source to receive the gate signal G[n-1] provided by the third signal source. The second end of the transistor 143 is coupled to the second end of the capacitor 141, and the control end of the transistor 143 is coupled to the first signal source to receive the gate signal G[n-2] provided by the first signal source. The first end of the transistor 144 is coupled to the fourth signal source to receive the gate signal G[n+1] provided by the fourth signal source, and the second end of the transistor 144 is coupled to the second end of the capacitor 141. The control end of the transistor 144 is coupled to the second signal source to receive the gate signal G[n+2] provided by the second signal source.

The voltage stabilizing circuit 150 includes a transistor 151 and a transistor 152. The first end of the transistor 151 is coupled to the node Q to receive the signal Q[n] on the node Q. The second end of the transistor 151 is coupled to the reference potential source to receive the reference potential VSS provided by the reference potential source. The control terminal of the transistor 151 is coupled to the voltage stabilization control signal source to receive the voltage regulation control signal P[n] provided by the voltage stabilization control signal source. The first end of the transistor 152 is coupled to the output terminal 170, and the second end of the transistor 152 is coupled to the reference potential source to receive the reference potential VSS provided by the reference potential source, and the control terminal of the transistor 152 is coupled to the voltage regulator control. The signal source receives the voltage regulation control signal P[n] provided by the voltage stabilization control signal source. The voltage stabilizing control circuit 160 includes a capacitor 161 and a transistor 162. The first end of the capacitor 161 is coupled to the first clock signal source to receive the clock signal CK3 provided by the first clock signal source. The first end of the transistor 162 is coupled to the second end of the capacitor 161 and configured to provide the voltage control signal source described above. The second end of the transistor 162 is coupled to the reference potential source to receive the reference potential VSS provided by the reference potential source. The control terminal of the transistor 162 is coupled to the node Q to receive the signal Q[n] on the node Q.

FIG. 3 is a timing diagram of signals of a shift register according to an embodiment of the invention. In FIG. 3, the same reference numerals as those in FIGS. 1 and 2 are denoted as the same signals. Referring to FIG. 2 and FIG. 3 simultaneously, in the description of FIG. 2, the first signal source is used to provide the gate signal G[n-2] outputted by the n-2th stage shift register, and the second signal source The gate signal G[n+2] outputted by the n+2th stage shift register is provided, and the third signal source is used to provide the gate signal G outputted by the n-1th stage shift register. [n-1], the fourth signal source is used to provide the gate signal G[n+1] outputted by the n+1th stage shift register, and the gate signal G[n] shown in FIG. -2], G[n-1], G[n+1], and G[n+2] waveforms, which can be seen in the signals of the first signal source, the second signal source, the third signal source, and the fourth signal source. Each has a pulse, and the pulse enable time of the signal of the first signal source and the third signal source partially overlaps, and the pulse enable time of the signal of the second signal source and the fourth signal source partially overlaps, the first signal source The pulse enable time of the signal with the third signal source does not overlap with the pulse enable time of the signals of the second signal source and the fourth signal source.

Please refer to FIG. 2 and FIG. 3 at the same time. The operation of the shift register shown in FIG. 2 will be described in the following seven stages (stages 1 to 7) shown in FIG. 3, and the level of the high level voltage U2D and the pulse in each clock signal are assumed. The high level and the high level of the pulse in each gate signal are the level of the power supply voltage VDD, and the level of the low level voltage D2U, the low level of the pulse in each clock signal, and the position of each gate signal The low level of the pulse is the level of the reference potential VSS.

In phase 1, transistors 112, 144, 151, and 152 all assume a turned off state, while transistors 111, 121, 143, 162, and 131 all assume a turned on state. At this time, the voltage of the signal Q[n] is ,among them The threshold voltage of the transistor 111, and the voltages of the signal R[n] and the gate signal G[n] are both . In phase 2, transistors 111, 112, 144, 151, and 152 all assume a closed state, while transistors 121, 143, 162, and 131 all assume a conducting state. At this time, the voltage of the signal Q[n] is ,among them The first coupling voltage is supplied to the node Q for the voltage boosting circuit 140. The voltage of the signal R[n] is ,among them It is the threshold voltage of the transistor 143. As for the voltage of the gate signal G[n], . As can be seen from the above, before the pulse of the gate signal G[n] is generated, the voltage boosting circuit 140 has coupled the node Q to a higher potential, thereby increasing the conduction degree of the transistor 121, thereby shortening the gate signal G. The rising time of the pulse of [n].

In phase 3, transistors 111, 112, 143, 144, 151, 152, and 131 all assume a closed state, while transistors 162 and 121 both assume a conducting state. At this time, the voltage of the signal Q[n] is ,among them The second coupling voltage is supplied to the node Q for the voltage boosting circuit 140, and the voltage of the gate signal G[n] is . As can be seen from the above, before the pulse of the gate signal G[n] transitions from the high potential to the low potential, the voltage boost circuit 140 has coupled the node Q to a higher potential than that of the phase 2, thereby further increasing the power. The degree of conduction of the crystal 121 can further shorten the fall time of the pulse of the gate signal G[n].

In phase 4, transistors 111, 112, 143, 144, 151, 152, and 131 all assume a closed state, while transistors 121 and 162 both assume a conducting state. At this time, the voltage of the signal Q[n] is And the voltage of the gate signal G[n] is . In phase 5, transistors 111, 143, 121, 162, 151, and 152 all assume a closed state, while transistors 112, 144, and 131 all assume a conducting state. At this time, the voltages of the signal Q[n], the signal R[n] and the gate signal G[n] are both . In phase 6, since each transistor is in a closed state, the shift register has no action. In phase 7, transistors 111, 112, 143, 144, 121, 162, and 131 all assume a closed state, while transistors 151 and 152 both assume a conducting state. At this time, the voltages of the signal Q[n] and the gate signal G[n] are both .

In addition, as can be seen from the above teachings, both the voltage stabilizing circuit 150 and the voltage stabilizing control circuit 160 in the shift register shown in FIG. 2 can selectively determine whether to adopt according to actual circuit design requirements. In addition, although according to the description of the embodiment shown in FIG. 2 and FIG. 3, it can be known that the corresponding gate driving circuit sequentially supplies pulses from the gate signals G[n-2] to G[n+2]. Therefore, the gate driving circuit uses forward scanning to drive the gate lines in the display. However, this is not intended to limit the present invention. The gate driving circuit can also use reverse scanning. (which is opposite to the direction of the forward scan) to drive each gate line in the display, as long as the coupling relationship between the gate signal G[n-2] and G[n+2] shown in Figure 2 is reversed. And reverse-coupling can be done by swapping the coupling relationship between the gate signal G[n-1] and G[n+1].

In summary, the shift register of the present invention uses the voltage boost circuit to first view the node (which can be regarded as a shift register) before the pulse provided by the shift register is changed from the high level to the low level. The voltage of the same gate of the driving transistor is raised to a higher level than that of the conventional shift register circuit architecture, so that the output of the shift register can be driven faster. The crystal is discharged, thereby shortening the fall time of the pulse provided by the shift register.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any one skilled in the art can make some modifications and retouchings without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

110‧‧‧Input signal selection circuit

111, 112, 121, 131, 143, 144, 151, 152, 162‧‧‧ transistors

141, 142, 161‧‧ ‧ capacitor

120‧‧‧Output circuit

130‧‧‧ Pull-down circuit

140‧‧‧Voltage up circuit

150‧‧‧Variable circuit

160‧‧‧Regulator control circuit

170‧‧‧output

CK1, CK2, CK3, CK4‧‧‧ clock signal

D2U‧‧‧ low level voltage

G[n-3], G[n-2], G[n-1], G[n], G[n+1], G[n+2], G[n+3]‧‧‧ Extreme signal

P[n], Q[n], R[n]‧‧‧ signals

Q‧‧‧ node

U2D‧‧‧ high level voltage

VSS‧‧‧ reference potential

1 is a circuit block diagram of a gate driving circuit in accordance with an embodiment of the present invention; FIG. 2 is a circuit diagram of a shift register in accordance with an embodiment of the present invention; FIG. 3 is a shifting diagram in accordance with an embodiment of the present invention. The signal timing diagram of the register.

110‧‧‧Input signal selection circuit

111, 112, 121, 131, 143, 144, 151, 152, 162‧‧‧ transistors

141, 142, 161‧‧ ‧ capacitor

120‧‧‧Output circuit

130‧‧‧ Pull-down circuit

140‧‧‧Voltage up circuit

150‧‧‧Variable circuit

160‧‧‧Regulator control circuit

170‧‧‧output

CK1, CK3‧‧‧ clock signal

D2U‧‧‧ low level voltage

G[n-2], G[n-1], G[n], G[n+1], G[n+2]‧‧‧ gate signal

P[n], Q[n], R[n]‧‧‧ signals

Q‧‧‧ node

U2D‧‧‧ high level voltage

VSS‧‧‧ reference potential

Claims (18)

A shift register includes: an input signal selection circuit coupled to a node, a first signal source, a second signal source, a first input signal source and a second input signal source; and an output circuit And coupled to the node, one of the output of the shift register and a first clock signal source; a pull-down circuit coupled to the output terminal, a second clock signal source and a reference potential source; The voltage boosting circuit is coupled to the node, the output terminal, the first signal source, the second signal source, a third signal source, and a fourth signal source. The shift register according to claim 1, wherein the input signal selection circuit comprises: a first transistor having a first end, a second end and a first control end, the first The second end is coupled to the first input signal source, the second end is coupled to the node, and the first control end is coupled to the first signal source; and a second transistor has a third end and a fourth end And a second control end coupled to the second input signal source, the fourth end is coupled to the node, and the second control end is coupled to the second signal source. The shift register of claim 1, wherein the output circuit comprises: a transistor having a first end, a second end and a control end, the first end coupled to the first end The clock signal source, the second end is coupled to the output end, and the control end is coupled to the node. The shift register of claim 1, wherein the pull-down circuit comprises: a transistor having a first end, a second end and a control end, the first end coupled to the output end The second end is coupled to the reference potential source, and the control end is coupled to the second clock signal source. The shift register of claim 1, wherein the voltage boosting circuit comprises: a first capacitor having a first end and a second end, the first end coupled to the node; The second capacitor has a third end and a fourth end, the third end is coupled to the second end, and the fourth end is coupled to the output end; a first transistor has a fifth end, a first a sixth end and a first control end, the fifth end is coupled to the third signal source, the sixth end is coupled to the second end, and the first control end is coupled to the first signal source; and a second The transistor has a seventh end, an eighth end and a second control end, the seventh end is coupled to the fourth signal source, the eighth end is coupled to the second end, and the second control end is coupled The second signal source is connected. The shift register according to claim 1, further comprising: a voltage stabilizing circuit coupled to the node, the output end, a regulated control signal source and the reference potential source; and a voltage regulator The control circuit is coupled to the voltage stabilizing circuit, the first clock signal source, the node and the reference potential source, and is configured to provide the voltage control signal source. The shift register of claim 6, wherein the voltage stabilizing circuit comprises: a first transistor having a first end, a second end and a first control end, the first end The second end is coupled to the reference potential source, and the first control end is coupled to the regulated control signal source; and a second transistor has a third end, a fourth end, and a second end The second control end is coupled to the output end, the fourth end is coupled to the reference potential source, and the second control end is coupled to the voltage stabilization control signal source. The shift register of claim 6, wherein the voltage stabilizing control circuit comprises: a capacitor having a first end and a second end, wherein the first end is coupled to the first clock signal And a transistor having a third end, a fourth end, and a control end, the third end coupled to the second end, and configured to provide the voltage control signal source, the fourth end coupled to the Referring to the potential source, the control terminal is coupled to the node. The shift register according to claim 1, wherein the first signal source, the second signal source, the third signal source and the fourth signal source each have a pulse, and the signal The first signal source partially overlaps with the pulse enable time of the signal of the third signal source, and the second signal source partially overlaps with the pulse enable time of the signal of the fourth signal source, and the first signal source and the signal source The pulse enable time of the signal of the third signal source does not overlap with the pulse enable time of the signal of the second signal source and the fourth signal source. A gate driving circuit includes a plurality of shift registers, each shift register includes: an input signal selecting circuit coupled to a node for determining whether to use the signal according to a first signal source The node is coupled to a first input signal source, and configured to determine whether to connect the node to a second input signal source according to a signal of the second signal source; an output circuit coupled to the node and the shift temporary An output end of the register is configured to determine whether to provide a signal of a first clock signal source to the output end according to a voltage of the node; and a pull-down circuit coupled to the output end for using a second time The signal of the pulse signal source determines whether the output end is coupled to a reference potential source, wherein the pulse source enable time of the signal of the second clock signal source and the first clock signal source does not overlap with each other; and a voltage rise a circuit, coupled to the node and the output terminal, configured to determine whether to provide the first coupled power of the node according to the signal of the first signal source, the signal of the third signal source, and the voltage of the output terminal Pressing, and determining whether to provide the node according to the signal of the first signal source, the signal of the third signal source, the signal of a fourth signal source, the signal of the second signal source, and the voltage of the output terminal Coupling voltage. The gate drive circuit of claim 10, wherein the input signal selection circuit comprises: a first transistor having a first end, a second end and a first control end, the first end The first input signal source is coupled to the node, the second end is coupled to the first signal source, and the second transistor has a third end and a fourth end a second control end is coupled to the second input signal source, the fourth end is coupled to the node, and the second control end is coupled to the second signal source. The gate driving circuit of claim 10, wherein the output circuit comprises: a transistor having a first end, a second end and a control end, wherein the first end is coupled to the first end The signal source, the second end is coupled to the output end, and the control end is coupled to the node. The gate driving circuit of claim 10, wherein the pull-down circuit comprises: a transistor having a first end, a second end and a control end, wherein the first end is coupled to the output end, The second end is coupled to the reference potential source, and the control end is coupled to the second clock signal source. The gate drive circuit of claim 10, wherein the voltage boost circuit comprises: a first capacitor having a first end and a second end, the first end coupled to the node; a second capacitor having a third end and a fourth end, the third end is coupled to the second end, and the fourth end is coupled to the output end; a first transistor having a fifth end, a sixth end and a first control end, the fifth end is coupled to the third signal source, the sixth end is coupled to the second end, and the first control end is coupled to the first signal source; The second transistor has a seventh end, an eighth end and a second control end, the seventh end is coupled to the fourth signal source, the eighth end is coupled to the second end, and the second control The end is coupled to the second signal source. The gate driving circuit of claim 10, further comprising: a voltage stabilizing circuit coupled to the node and the output terminal for determining whether to use the node according to a signal of a voltage stabilized control signal source The output terminal is coupled to the reference potential source; and a voltage stabilizing control circuit coupled to the voltage stabilizing circuit for providing the voltage stabilization control according to the signal of the first clock signal source and a voltage of the node Signal source. The gate driving circuit of claim 15, wherein the voltage stabilizing circuit comprises: a first transistor having a first end, a second end and a first control end, the first end coupling Connected to the node, the second end is coupled to the reference potential source, and the first control end is coupled to the voltage stabilizing control signal source; and a second transistor has a third end, a fourth end, and a first The second terminal is coupled to the output terminal, the fourth terminal is coupled to the reference potential source, and the second control terminal is coupled to the voltage stabilization control signal source. The gate drive circuit of claim 15, wherein the voltage regulator control circuit comprises: a capacitor having a first end and a second end, the first end coupled to the first clock signal source ;as well as a transistor having a third end, a fourth end, and a control end, the third end being coupled to the second end, and configured to provide the regulated control signal source, the fourth end coupled to the reference potential source And the control end is coupled to the node. The gate driving circuit of claim 10, wherein the first signal source, the second signal source, the third signal source, and the fourth signal source each have a pulse, and the The signal source has a partial overlap with the pulse enable time of the signal of the third signal source, and the second signal source partially overlaps with the pulse enable time of the signal of the fourth signal source, the first signal source and the first signal source The pulse enable time of the signal of the third signal source does not overlap with the pulse enable time of the signal of the second signal source and the fourth signal source.