TWI670707B - Gate driving apparatus - Google Patents

Abstract

The gate driving device includes a plurality of shift register circuits. In the shift register circuit, the output stage circuit receives and charges the output terminal to generate a gate drive signal in response to the control signal to provide a gate low or high voltage. The compensation circuit includes first and second transistors and first and second capacitors. The first voltage regulator selects a signal according to the mode to provide a gate low or high voltage to adjust the control signal. The second voltage regulator adjusts the control signal according to the switching signal and the reverse clock signal to provide a front gate drive signal or a start pulse signal. The third voltage regulator selects a signal according to the mode and the control signal to provide a gate low or high voltage to adjust the control signal. The fourth voltage regulator adjusts the control signal according to the reverse clock signal.

Description

Gate drive

The present invention relates to a gate drive device, and more particularly to a gate drive device for a display device.

In recent years, there have been many products that integrate a gate driver circuit (Gate driver) in a display driver circuit into a glass, which is a Gate-Driver-on-Array (GOA) circuit. The gate driving circuit on the array has many advantages, which can reduce the width of the frame of the display panel to achieve the effect of the narrow frame, thereby effectively reducing the design area of the internal circuit of the display.

In the display device, since the display screen presented by the display panel is easily affected by the on-voltage of the driving transistor in the pixel circuit, the quality of the display screen is degraded. Therefore, the gate driving circuit needs to make the same column of pixel switches be turned on or off at the same time in the compensation phase to compensate the driving transistor. Then, the gate driving circuit needs to turn on the pixel switch column by column in the data writing phase to write the drawing voltage (or pixel data) into the corresponding pixel circuit.

In other words, how to generate a consistent gate drive signal effectively when the gate driving device operates in the compensation phase, and in the data writing phase, the gate drive signal can be sequentially generated to improve the gate drive. The performance of the device will be an important issue for those skilled in the art.

The invention provides a gate driving device, which can enable each gate driving signal to be simultaneously enabled in the compensation phase, and enable each gate driving signal to be sequentially activated during the writing phase, thereby improving the gate driving device. efficacy.

The gate driving device of the present invention has a plurality of shift register circuits. The plurality of shift register circuits are coupled to each other in series to generate a plurality of gate drive signals, wherein the shift stage circuit of the Nth stage comprises an output stage circuit, a compensation circuit, and first to fourth voltage regulators. The output stage circuit has a first control end and a second control end to respectively receive the first control signal and the second control signal, according to the first control signal and the second control signal to provide a gate low voltage or a gate high voltage pair output Charging to generate the Nth gate drive signal. The compensation circuit is coupled between the first control terminal and the output stage circuit, wherein the compensation circuit includes first and second transistors and first and second capacitors. The first end of the first transistor receives the clock signal, and the control end of the first transistor is coupled to the first control end. The first end of the second transistor is coupled to the second end of the first transistor, the second end of the second transistor is coupled to the first node, and the control end of the second transistor receives the switching signal. The first capacitor is coupled between the first control terminal and the first node. The second capacitor is coupled between the first node and the output end. The first voltage regulator is coupled to the first control terminal, and selects a signal according to the first mode and the second mode selection signal to provide a gate low voltage or a gate high voltage to adjust the first control signal. The second voltage regulator is coupled to the first control end, and provides a front gate drive signal or a start pulse wave signal according to the switching signal and the reverse clock signal to adjust the first control signal. The third voltage regulator is coupled between the first control terminal and the second control terminal, and selects a signal according to the second mode and the first control signal to provide a gate low voltage or a gate high voltage to adjust the second control signal. The fourth voltage regulator is coupled to the second control end to adjust the second control signal according to the reverse clock signal.

Based on the above, the shift register circuit of the gate driving device of the present invention can synchronously output the gate driving signal generated by the output stage circuit and the front and rear gate driving signals in the compensation phase. And in the writing phase, the gate driving signal generated by the output stage circuit and the front and rear gate driving signals are sequentially outputted, thereby improving the performance of the gate driving device.

The above described features and advantages of the invention will be apparent from the following description.

The term "coupled (or connected)" as used throughout the specification (including the scope of the claims) may be used in any direct or indirect connection. For example, if the first device is described as being coupled (or connected) to the second device, it should be construed that the first device can be directly connected to the second device, or the first device can be A connection means is indirectly connected to the second device. In addition, wherever possible, the elements and/ Elements/components/steps that use the same reference numbers or use the same terms in different embodiments may refer to the related description.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a gate driving device according to an embodiment of the present invention. The gate driving device comprises a plurality of shift temporary storage circuits coupled in series with each other, and generates a plurality of gate driving signals respectively. Taking the shift register circuit 100 of the Nth stage as an example, the shift register circuit 100 includes an output stage circuit 110, a compensation circuit 120, and a plurality of voltage regulators 130-160. The output stage circuit 110 has a control terminal CT1 and a control terminal CT2. The control terminal CT1 and the control terminal CT2 can respectively receive the control signal CS1 and the control signal CS2. The output stage circuit 110 charges the output terminal OUT according to the control signal CS1 and the control signal CS2 to provide the gate low voltage VGL or the gate high voltage VGH, thereby generating the Nth stage gate drive signal G[N].

In the present embodiment, the output stage circuit 110 includes transistors M1, M2. The first end of the transistor M1 receives the gate low voltage VGL, the second end of the transistor M1 is coupled to the output terminal OUT, and the control end of the transistor M1 is coupled to the control terminal CT1. The first end of the transistor M2 is coupled to the output terminal OUT, the second end of the transistor M2 receives the gate high voltage VGH, and the control end of the transistor M2 is coupled to the control terminal CT2.

The compensation circuit 120 is coupled between the control terminal CT1 and the output stage circuit 110. In the present embodiment, the compensation circuit 120 includes transistors M3, M4, capacitors C1, and C2. The first end of the transistor M3 receives the clock signal CLK, and the control end of the transistor M3 is coupled to the control terminal CT1. The first end of the transistor M4 is coupled to the second end of the transistor M3, the second end of the transistor M4 is coupled to the node P1, and the control end of the transistor M4 receives the switching signal CHA. In addition, the capacitor C1 is coupled between the control terminal CT1 and the node P1. The capacitor C2 is coupled between the node P1 and the output terminal OUT.

On the other hand, the voltage regulator 130 is coupled to the control terminal CT1. The voltage regulator 130 can determine the supply of the gate low voltage VGL or the gate high voltage VGH to the control terminal CT1 according to the mode selection signal SS1 and the mode selection signal SS2, so that the voltage regulator 130 can pass the gate low voltage VGL or the gate. The high voltage VGH is used to adjust the control signal CS1.

In the present embodiment, the voltage regulator 130 includes transistors M5, M6, and M7. The first end of the transistor M5 receives the gate low voltage VGL, the second end of the transistor M5 is coupled to the control terminal CT1, and the control terminal of the transistor M5 receives the mode selection signal SS1. The transistor M6 and the transistor M7 are connected in series with each other, wherein the transistor M6 receives the gate high voltage VGH and is controlled by the mode selection signal SS2 and is connected to the control terminal CT1 through the transistor M7. The transistor M7 is coupled to the control terminal CT1 and is controlled by the mode selection signal SS2. It should be noted that the transistor M7 in FIG. 1 can be omitted, and the illustration of FIG. 1 is merely illustrative and should not be used to limit the scope of the present invention.

The voltage regulator 140 is coupled to the control terminal CT1. The voltage regulator 140 can determine the front gate driving signal G[N-1] or the starting pulse signal ST to the control terminal CT1 according to the switching signal CHA and the reverse clock signal XCLK, so that the voltage regulator 140 can The control signal CS1 is adjusted by the front gate drive signal G[N-1] or the start pulse signal ST.

In the present embodiment, the voltage regulator 140 includes a transistor M8 and a transistor M9. The transistor M8 and the transistor M9 are connected in series with each other, wherein the transistor M8 receives the front gate drive signal G[N-1] or the start pulse signal ST and is controlled by the reverse clock signal XCLK. The transistor M9 is coupled to the control terminal CT1 and is controlled by the switching signal CHA.

In particular, in the present embodiment, when the shift register circuit 100 is operated in the compensation phase, the voltage regulator 140 can turn off the transistor M9 according to the switching signal CHA having a high voltage level. Thereby, in the compensation phase, the shift register circuit 100 can effectively isolate the influence between the front gate drive signal G[N-1] or the start pulse signal ST and the control signal CS1, thereby reducing the synchronization. The influence of the gate drive signal G[N] outputted by the output stage circuit 110 on the front gate drive signal G[N-1] or the start pulse signal ST.

On the other hand, the voltage regulator 150 is coupled between the control terminal CT1 and the control terminal CT2. The voltage regulator 150 can determine the supply of the gate low voltage VGL or the gate high voltage VGH to the control terminal CT2 according to the mode selection signal SS2 and the control signal CS1, so that the voltage regulator 150 can pass the gate low voltage VGL or the gate is high. The voltage VGH is used to adjust the control signal CS2.

In the present embodiment, the voltage regulator 150 includes transistors M10 to M13. The first end of the transistor M10 receives the gate low voltage VGL, the second end of the transistor M10 is coupled to the control terminal CT2, and the control terminal of the transistor M10 receives the mode selection signal SS2. The first end of the transistor M11 is coupled to the control terminal CT2, the second end of the transistor M11 receives the gate high voltage VGH, and the control terminal of the transistor M11 receives the control signal CS1. The first end of the transistor M12 is coupled to the control terminal CT1, and the control end of the transistor M12 is coupled to the control terminal CT2. The first end of the transistor M13 is coupled to the second end of the transistor M12, the second end of the transistor M13 receives the gate high voltage VGH, and the control end of the transistor M13 is coupled to the control terminal CT2.

The voltage regulator 160 is coupled to the control terminal CT2. The voltage regulator 160 can adjust the control signal CS2 according to the reverse clock signal XCLK. In the present embodiment, the voltage regulator 160 includes a transistor M14 and a transistor M15. The first end of the transistor M14 and the control terminal collectively receive the reverse clock signal XCLK. The first end of the transistor M15 is coupled to the second end of the transistor M14, the second end of the transistor M15 is coupled to the control terminal CT2, and the control terminal of the transistor M15 receives the reverse clock signal XCLK.

It is worth mentioning that the transistor M14 and the transistor M15 of the embodiment can form a diode according to the connection mode of the diode configuration. Wherein the cathode of the diode (ie, the first end of the transistor M14) receives the reverse clock signal XCLK, and the anode of the diode (ie, the second end of the transistor M15) is coupled to the control End CT2. Incidentally, the transistors M1 to M15 of the present embodiment are exemplified by a P-type transistor, but the embodiment of the present invention is not limited thereto. In some embodiments, the transistor M14 or M15 may omit one of them. For example, the transistor M14 can be omitted, and the first end and the control end of the transistor M15 receive the reverse clock signal XCLK, and the second end is coupled to the control terminal CT2.

For details of the operation of the shift register circuit 100, please refer to FIG. 2 and FIG. 3A to FIG. 3F simultaneously, wherein FIG. 2 is a waveform diagram of a gate driving device according to an embodiment of the present invention, and FIGS. 3A to 3F are in accordance with the present invention. An equivalent circuit diagram of the shift register circuit of the embodiment.

Referring to FIG. 2, in the embodiment, one pixel period TFR of the shift register circuit 100 can be divided into a compensation phase TC, a writing phase TR, and a voltage holding phase TVH, and a compensation phase TC, a writing phase TR, and The voltage holding phases TVH do not overlap each other. Wherein, after the writing phase TR is enabled in the compensation phase TC, the voltage holding phase TVH is enabled after the writing phase TR.

Referring to FIG. 2 and FIG. 3A simultaneously, specifically, when the shift temporary storage circuit 100 operates in the first sub-phase TC_1 of the compensation phase TC, the clock generator (not drawn) externally connected to the shift temporary storage circuit 100 A clock signal CLK having a high voltage level and a reverse clock signal XCLK having a low voltage level can be provided to the shift register circuit 100. In addition, the shift register circuit 100 can set the mode selection signal SS1 to a low voltage level state, and the set mode selection signal SS2 and the switching signal CHA are all in a high voltage level state.

In detail, the voltage regulator 130 can transmit the gate low voltage VGL to the control terminal CT1 according to the mode selection signal SS1, thereby lowering the voltage level of the control signal CS1 and synchronously turning on the transistor M3. Also, the transistor M4 and the transistor M9 can be turned off in accordance with the switching signal CHA. In this case, the voltage regulator 140 will not be able to transmit the preceding gate drive signal G[N-1] or the start pulse signal ST to the control terminal CT1. Thereby, the present embodiment can effectively isolate the influence between the front-stage gate drive signal G[N-1] or the start pulse wave signal ST and the control signal CS1.

On the other hand, in the first sub-phase TC_1, the voltage regulator 160 can be turned on according to the reverse clock signal XCLK and perform a charging operation on the control signal CS2. Then, the voltage regulator 150 can transmit the gate high voltage VGH to the control terminal CT2 according to the pulled down control signal CS1, thereby pulling the control signal CS2 to the voltage level of the gate high voltage VGH.

In other words, in the first sub-phase TC_1, the output stage circuit 110 can supply the gate low voltage VGL according to the pulled down control signal CS1 to charge the output terminal OUT, and enable the output stage circuit 110 to pass through the output terminal OUT. Correspondingly, a gate drive signal G[N] having a voltage level of the gate low voltage VGL is generated.

Next, please refer to FIG. 2 and FIG. 3B simultaneously. Specifically, when the shift register circuit 100 operates in the second sub-phase TC_2 of the compensation phase TC, the shift register circuit 100 can set the mode selection signal SS1 and select the mode. Both the signal SS2 and the switching signal CHA are in a high voltage level state. Moreover, an external clock generator (not drawn) can provide the clock signal CLK and the reverse clock signal XCLK in a periodically transition state to the shift register circuit 100.

In detail, the voltage regulator 130 may be turned off according to the mode selection signal SS1 and the mode selection signal SS2, and the transistor M4 and the transistor M9 may be continuously turned off according to the switching signal CHA. In addition, the transistor M3 can be continuously turned on in accordance with the pulled down control signal CS1. It is worth mentioning that in the second sub-phase TC_2, the compensation circuit 120 can be in a floating state based on the control terminal CT1 and the node P1, and the voltage of the control signal CS1 is caused by the coupling effect of the capacitor C1 and the capacitor C2. The level is adjusted to the sum of the voltage value of the gate low voltage VGL and a voltage value V1. Further, the voltage level on the node P1 is also synchronously adjusted to the voltage difference between the voltage value of the gate low voltage VGL and an offset value ΔV via the coupling effect. The voltage value V1 can be expressed as a voltage difference between the on-voltage |VTH5| of the transistor M5 and the offset value ΔV after the coupling effect. That is, the voltage level of the control signal CS1 at this time is VGL+V1=VGL+|VTH5|-ΔV, and the voltage level of the node P1 at this time is VGL-ΔV.

On the other hand, the voltage regulator 160 is periodically turned off in accordance with the reverse clock signal XCLK. Moreover, the voltage regulator 150 can provide the gate high voltage VGH to the control terminal CT2 according to the pulled down control signal CS1, so that the voltage level of the control signal CS2 can be maintained at the voltage value of the gate high voltage VGH.

In other words, in the second sub-phase TC_2, the output stage circuit 110 can provide the gate low voltage VGL according to the pulled down control signal CS1 to charge the output terminal OUT, and enable the output stage circuit 110 to pass through the output terminal OUT. Correspondingly, a gate drive signal G[N] having a voltage level of the gate low voltage VGL is generated.

Next, please refer to FIG. 2 and FIG. 3C simultaneously. Specifically, when the shift register circuit 100 operates in the third sub-phase TC_3 of the compensation phase TC, the shift register circuit 100 can set the mode selection signal SS1 and the switching signal. The CHA is continuously maintained at a high voltage level state, and the mode selection signal SS2 is set to a low voltage level state. In addition, an external clock generator (not shown) can provide a clock signal CLK with a high voltage level and a reverse clock signal XCLK with a low voltage level.

In detail, the voltage regulator 130 can provide the gate high voltage VGH to the control terminal CT1 according to the mode selection signal SS2, so that the voltage level of the control signal CS1 can be pulled up to the voltage value of the gate high voltage VGH. At the same time, the transistor M3 and the transistor M4 in the compensation circuit 120 can be disconnected according to the pulled control signal CS1 and the switching signal CHA, respectively, and the voltage regulator 140 can be continuously disconnected according to the switching signal CHA. open.

On the other hand, the voltage regulator 160 can be turned on in accordance with the reverse clock signal XCLK to perform a charging operation on the control signal CS2. Then, the voltage regulator 150 can provide the gate low voltage VGL to the control terminal CT2 according to the mode selection signal SS2, so that the voltage level of the control signal CS2 is adjusted to the voltage value of the gate low voltage VGL and a voltage value V2. sum. The voltage value V2 can be expressed as the turn-on voltage |VTH10| of the transistor M10. That is, the voltage level of the control signal CS2 at this time is VGL+V2=VGL+|VTH10|.

In other words, in the third sub-phase TC_3, the output stage circuit 110 can provide the gate high voltage VGH according to the pulled down control signal CS2 to charge the output terminal OUT, and enable the output stage circuit 110 to pass through the output terminal OUT. Correspondingly, a gate drive signal G[N] having a voltage level of the gate high voltage VGH is generated.

According to the description of FIG. 3A to FIG. 3C above, it can be clearly seen that in the compensation phase TC, the shift register circuit 100 can disconnect the previous gate by setting the switching signal CHA to a high voltage level state. The drive signal G[N-1] is transmitted to the path of the control terminal CT1, so that the gate drive signal G[N] will not be affected by the previous gate drive signal G[N-1], and the gate drive The signal G[N] can be output synchronously with the subsequent gate drive signal G[N+1], thereby improving the performance of the display gate driving device.

Referring to FIG. 2 and FIG. 3D simultaneously, specifically, when the shift register circuit 100 operates in the first sub-stage TR_1 of the write phase TR, the shift register circuit 100 can set the mode select signal SS1 and the mode select signal. SS2 is in a high voltage level state, and the switching signal CHA is set to a low voltage level state. In addition, an external clock generator (not drawn) can provide a clock signal CLK having a high voltage level and a reverse clock signal XCLK having a low voltage level to the shift register circuit 100.

In detail, the voltage regulator 130 can be turned off according to the mode selection signal SS1 and the mode selection signal SS2. Further, the transistor M3 and the transistor M4 in the voltage regulator 120 can be turned on according to the pulled control signal CS1 and the switching signal CHA, respectively. Unlike the compensation phase TC, in the write phase TR, the voltage regulator 140 can be turned on in accordance with the switching signal CHA and the reverse clock signal XCLK.

In this case, the voltage regulator 140 can transmit the pre-gate drive signal G[N-1] or the start pulse signal ST to the control terminal CT1 so that the voltage level of the control signal CS1 can be pulled down to the gate. The sum of the voltage value of the very low voltage VGL and a voltage value V3. The voltage value V3 can be expressed as the turn-on voltage |VTH8| of the transistor M8. That is, the voltage level of the control signal CS1 at this time is VGL+V3=VGL+|VTH8|. It should be noted that since the transistor M3 and the transistor M4 are both in an on state, the node P1 can pass through the conduction path formed by the transistor M3 and the transistor M4, and is synchronized according to the pulled clock signal CLK. The voltage level is pulled up to the gate high voltage VGH.

On the other hand, in the first sub-phase TR_1, the voltage regulator 160 can be continuously turned on in accordance with the inverted reverse clock signal XCLK, and the charging signal is continuously charged. Then, the voltage regulator 150 can transmit the gate high voltage VGH to the control terminal CT2 according to the pull-down control signal CS1, so that the voltage level of the control signal CS2 can be pulled up to the voltage value of the gate high voltage VGH.

In other words, in the first sub-phase TR_1, the output stage circuit 110 can generate the gate drive signal G[N] correspondingly according to the pulled down control signal CS1. The voltage level of the gate driving signal G[N] at this time is the sum of the voltage value of the gate low voltage VGL and a voltage value V4. The voltage value V4 can be expressed as the turn-on voltage |VTH8| of the transistor M8 and the turn-on voltage |VTH1| of the transistor M1. That is, the voltage level of the gate drive signal G[N] at this time is VGL+V4=VGL+|VTH8|+|VTH1|.

Referring to FIG. 2 and FIG. 3E simultaneously, specifically, when the shift temporary storage circuit 100 operates in the second sub-phase TR_2 of the writing phase TR, the shift register circuit 100 can set the mode selection signal SS1 and the mode selection signal. SS2 is continuously maintained at a high voltage level state, and the switching signal CHA is set to a low voltage level state. In addition, an external clock generator (not shown) can provide a clock signal CLK having a low voltage level and a reverse clock signal XCLK having a high voltage level to the shift register circuit 100.

In detail, the voltage regulator 130 may be continuously turned off according to the mode selection signal SS1 and the mode selection signal SS2, and the voltage regulator 140 may be turned off again according to the inverted reverse clock signal XCLK. Then, the transistor M3 and the transistor M4 of the compensation circuit 120 can be turned on according to the pulled control signal CS1 and the switching signal CHA, respectively.

It is worth mentioning that in the second sub-phase TR_2, the compensation circuit 120 can be based on the pulled clock signal CLK, so that the voltage level of the node P1 is synchronously pulled down to the voltage value of the gate low voltage VGL and The sum of the voltage values V5. The voltage value V5 can be expressed as the turn-on voltage |VTH3| of the transistor M3. That is, the voltage level of the node P1 at this time is VGL+|VTH3|. Then, the compensation circuit 120 can pass the coupling effect of the capacitor C1 according to the voltage level of the node P1 being pulled down, so that the voltage level of the control signal CS1 is synchronized to the voltage value of the gate low voltage VGL and a voltage. The sum of the values V6. Wherein, the voltage value V6 can be expressed as a voltage difference between the on-voltage |VTH8| of the transistor M8 and the offset value ΔV after the coupling effect. That is, the voltage level of the control signal CS1 at this time is VGL+V6=VGL+|VTH8|-ΔV.

On the other hand, the voltage regulator 160 can be turned off again depending on the inverted reverse clock signal XCLK. Next, the voltage regulator 150 can provide the gate high voltage VGH to the control terminal CT2 according to the pulled down control signal CS1 to maintain the voltage level of the control signal CS2 as the voltage value of the gate high voltage VGH.

In other words, in the second sub-stage TR_2, the output stage circuit 110 can supply the gate low voltage VGL according to the pulled down control signal CS1 to charge the output terminal OUT, and enable the output stage circuit 110 to pass through the output terminal OUT. Correspondingly, a gate drive signal G[N] having a voltage level of the gate low voltage VGL is generated.

Referring to FIG. 2 and FIG. 3F simultaneously, specifically, when the shift register circuit 100 operates in the voltage hold phase TVH, the shift register circuit 100 can set the mode select signal SS1 and the mode select signal SS2 to be high voltage. Bit state, and set the switching signal to continue to the low voltage level state. In addition, an external clock generator (not shown) can provide the clock signal CLK and the reverse clock signal XCLK in a periodically transition state to the shift register circuit 100.

In detail, the voltage regulator 130 can be kept turned off according to the mode selection signal SS1 and the mode selection signal SS2. At the same time, the voltage regulator 140 can be periodically turned on according to the reverse clock signal XCLK, and periodically charges the control signal CS1 to thereby pull up the control signal CS1. Next, the transistor M3 of the voltage regulator 120 can be turned off again in accordance with the pulled up control signal CS1.

On the other hand, the voltage regulator 160 can be periodically turned on according to the reverse clock signal XCLK, and periodically charges the control signal CS2 to lower the voltage level of the control signal CS2.

In other words, in the voltage holding phase TVH, the output stage circuit 110 can supply the gate low voltage VGH according to the pulled down control signal CS2 to charge the output terminal OUT, and make the output stage circuit 110 correspond to the output terminal OUT. A gate drive signal G[N] having a voltage level of a gate high voltage VGH is generated.

It should be noted that the above high voltage level may be the voltage value of the gate high voltage VGH, and the low voltage level may be the voltage value of the gate low voltage VGL.

According to the description of FIG. 3D to FIG. 3F described above, it can be clearly seen that in the writing phase TR, the shift register circuit 100 can pass the coupling effect of the capacitor C1 to enable the control signal CS1 to be pulled down synchronously, thereby enabling The gate driving signal G[N] and the subsequent gate driving signal G[N+1] may be sequentially outputted to improve the performance of the gate driving device.

In summary, the shift register circuit of the gate driving device of the present invention can synchronously output the gate driving signal generated by the output stage circuit and the front and rear gate driving signals in the compensation phase. And in the writing phase, the gate driving signal generated by the output stage circuit and the front and rear gate driving signals are sequentially outputted, thereby improving the performance of the gate driving device.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Shift register circuit

110‧‧‧Output stage circuit

120‧‧‧Compensation circuit

130～160‧‧‧Voltage regulator

CT1～CT2‧‧‧ control terminal

CS1～CS2‧‧‧ control signal

CHA‧‧‧Switching signal

C1, C2‧‧‧ capacitor

G[N-1]～G[N+1] ‧‧‧gate drive signal

M1～M15‧‧‧O crystal

OUT‧‧‧ output

P1‧‧‧ node

VGL‧‧‧ gate low voltage

VGH‧‧‧ gate high voltage

SS1~SS2‧‧‧ mode selection signal

ST‧‧‧Start pulse signal

TFR‧‧ ‧pixel period

TC‧‧‧Compensation phase

TR‧‧‧ write phase

TVH‧‧‧voltage hold phase

TC_1~TC_3, TR_1~TR_2‧‧‧ sub-stage

V1 ~ V6‧‧‧ voltage value

XCLK‧‧‧reverse clock signal

CLK‧‧‧ clock signal

1 is a schematic diagram of a gate driving device in accordance with an embodiment of the present invention. 2 is a waveform diagram of a gate driving device in accordance with an embodiment of the present invention. 3A through 3F are equivalent circuit diagrams of a shift register circuit in accordance with an embodiment of the present invention.

Claims (17)

A gate driving device includes: a plurality of shift temporary storage circuits, wherein the shift temporary storage circuits are coupled in series to generate a plurality of gate driving signals respectively, wherein the Nth stage shift temporary storage circuit comprises: An output stage circuit having a first control end and a second control end for receiving a first control signal and a second control signal respectively, according to the first control signal and the second control signal to provide a gate low voltage Or a gate high voltage charges an output terminal to generate an Nth-level gate drive signal; a compensation circuit coupled between the first control terminal and the output stage circuit, wherein the compensation circuit comprises: a first transistor receiving a clock signal, the control end of the first transistor being coupled to the first control terminal; a second transistor having a first end coupled to the first transistor The second end of the second transistor is coupled to a first node, and the control end of the second transistor receives a switching signal; a first capacitor coupled to the first control end and the first Between nodes; a second capacitor coupled between the first node and the output terminal; a first voltage regulator coupled to the first control terminal, according to a first mode selection signal and a second mode selection signal Providing the gate low voltage or the gate high voltage to adjust the first control signal; a second voltage regulator coupled to the first control terminal, according to the switching signal and a reverse clock signal to provide a a first gate signal or a start pulse signal to adjust the first control signal; a third voltage regulator coupled between the first control terminal and the second control terminal, and selecting according to the second mode a signal and the first control signal to provide the gate low voltage or the gate high voltage to adjust the second control signal; and a fourth voltage regulator coupled to the second control terminal, according to the reverse A pulse signal to adjust the second control signal. The gate driving device of claim 1, wherein in a compensation phase, the second voltage regulator is cut according to the switching signal, and the first voltage regulator provides the signal according to the first mode selection signal. The gate is low voltage to pull the first control signal low. The gate driving device of claim 2, wherein in the compensation phase, the fourth voltage regulator is turned on according to the reverse clock signal, and the third voltage regulator is configured according to the first control signal The gate high voltage is provided to pull the second control signal high. The gate driving device of claim 3, wherein in the compensation phase, the output stage circuit supplies the gate low voltage according to the first control signal to charge the output terminal, and generates the Nth Stage gate drive signal. The gate driving device of claim 2, wherein in a first sub-phase of a writing phase, the first voltage regulator is disconnected according to the first mode selection signal and the second mode selection signal Turning on, the second voltage regulator is turned on according to the switching signal and the inverted reverse clock signal to transmit the pre-gate driving signal or the starting pulse signal to lower the first control signal. The gate driving device of claim 5, wherein in the first sub-phase of the writing phase, the fourth voltage regulator is turned on according to the reverse clock signal, the third voltage adjustment The gate provides the gate high voltage according to the first control signal to boost the second control signal. The gate driving device of claim 5, wherein in a second sub-phase of the writing phase, the second voltage regulator is cut according to the inverted clock signal being pulled up, The first control signal is pulled down by an offset value according to the clock signal that is pulled low. The gate driving device of claim 7, wherein the output stage circuit supplies the gate low voltage according to the first control signal to charge the output terminal, and generates the Nth gate driving signal. . The gate driving device of claim 2, wherein in a voltage holding phase, the second voltage regulator is periodically turned on according to the reverse clock signal, and periodically the first control signal Charging, the first voltage regulator is kept turned off, and the fourth voltage regulator is periodically turned on according to the reverse clock signal, and periodically charges the second control signal. The gate driving device of claim 9, wherein in the voltage holding phase, the output stage circuit provides the gate high voltage according to the second control signal to generate the Nth gate driving signal. The gate driving device of claim 1, wherein the output stage circuit comprises: a third transistor, wherein the first end receives the gate low voltage, and the second end of the third transistor is coupled Up to the output end, the control end of the third transistor receives the first control signal; and a fourth transistor, the first end of which is coupled to the output end, and the second end of the fourth transistor receives the gate At a very high voltage, the control terminal of the fourth transistor receives the second control signal. The gate driving device of claim 1, wherein the first voltage regulator comprises: a third transistor, the first end of which receives the gate low voltage, and the second end of the third transistor The first mode control signal is coupled to the first control terminal, and the control terminal of the third transistor receives the first mode selection signal; and the at least one fourth transistor is coupled between the first control terminal and the gate high voltage. The control terminal of the at least one fourth transistor receives the second mode selection signal. The gate driving device of claim 1, wherein the second voltage regulator comprises: a third transistor, the first end of which receives the pre-gate driving signal or the starting pulse wave signal, The control terminal of the third transistor receives the reverse clock signal; and a fourth transistor having a first end coupled to the second end of the second transistor, the second end of the fourth transistor coupled Connected to the first control terminal, the control terminal of the fourth transistor receives the switching signal. The gate driving device of claim 1, wherein the third voltage regulator comprises: a third transistor, the first end of which receives the gate low voltage, and the second end of the third transistor And being coupled to the second control terminal, the control terminal of the third transistor receives the second mode selection signal; a fourth transistor having a first end coupled to the second control terminal, the fourth transistor The second end receives the gate high voltage, the control end of the fourth transistor receives the first control signal; a fifth transistor, the first end of which is coupled to the first control end, the fifth transistor The control terminal is coupled to the second control terminal; and a sixth transistor having a first end coupled to the second end of the fifth transistor, the second end of the sixth transistor receiving the gate high voltage The control end of the sixth transistor is coupled to the second control end. The gate driving device of claim 1, wherein the fourth voltage regulator comprises: a diode, the cathode receiving the reverse clock signal, and an anode coupled to the second control terminal. The gate driving device of claim 15, wherein the diode comprises: a third transistor, the first end and the control end receive the reverse clock signal; and a fourth transistor, The first end is coupled to the second end of the third transistor, the second end of the fourth transistor is coupled to the second control end, and the control end of the fourth transistor receives the reverse clock signal . The gate driving device of claim 1, wherein in a compensation phase, the gate driving signals are simultaneously enabled, and in a writing phase, the gate driving signals are sequentially enabled. During a voltage holding phase, the gate drive signals are maintained at a disabled voltage value, wherein the compensation phase, the write phase, and the voltage hold phase occur sequentially.