TWI398845B - Shift register - Google Patents

Description

Shift register

The invention relates to a displacement register, in particular to a displacement register capable of reducing leakage current caused by a bias effect.

Advanced display has become an important feature of today's consumer electronics products. LCD monitors have been widely used in a variety of electronic devices such as televisions, mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or notebook screens. . Low Temperature Poly-Silicon (LTPS) liquid crystal displays are currently the mainstream of consumer product development, and are mainly used in highly integrated features and high-quality displays.

Please refer to FIG. 1. FIG. 1 is a functional block diagram of a prior art liquid crystal display 10. The liquid crystal display 10 includes a liquid crystal display panel 12, a gate driver 14, and a source driver 16. The liquid crystal display panel 12 includes a plurality of pixels, and each of the pixels includes three pixel units 20 respectively representing three primary colors of red, green and blue (RGB). For a liquid crystal display panel 12 having a resolution of 1024×768, a total of 1024×768×3 pixel units 20 are required to be combined. The gate driver 14 outputs a scan signal so that the transistors 22 of each column are sequentially turned on, and the source driver 16 outputs corresponding data signals to an entire column of pixel units 20 to charge them to respective required voltages to display different Grayscale. After the same column is charged, the gate driver 14 turns off the scan signal of the column, and then the gate driver 14 outputs the scan signal to turn on the transistor 22 of the next column, and then the source driver 16 pairs the pixel unit of the next column. 20 charge and discharge. So in sequence, until all the pixel units 20 of the liquid crystal display panel 12 All charging is completed, and charging starts from the first column.

In the current liquid crystal display panel design, the gate driver 14 is equivalently a shift register, and the purpose is to output a scan signal to the liquid crystal display panel 12 at regular intervals. Taking a liquid crystal display panel 12 having a resolution of 1024 x 768 and an update frequency of 60 Hz as an example, the display time of each picture is about 1/60 = 16.67 ms. Therefore, the pulse period of each scanning signal is about 16.67 ms / 768 = 21.7 μs. The source driver 16 charges and discharges the pixel unit 20 to a desired voltage during the 21.7 μs period to display the corresponding gray scale.

Please refer to FIG. 2 and FIG. 3, FIG. 2 is a circuit diagram of a shift register unit of the prior art shift register, and FIG. 3 is a source-gate voltage difference V _GS and a drain current Id of the transistor. Diagram of the relationship. Figure 2 shows a shift register disclosed in U.S. Patent Publication No. 2008/0056431. When the transistors 403, 413 are turned off, although the gate-source voltage difference V _GS is equal to 0, it can be seen from Fig. 3 that there is still a slight leakage current, and the voltage of the node N5 has a leakage. . In this way, each stage of the shift register unit will cause the waveform of the output signal pulse to be lower and lower due to the influence of the leakage, thereby affecting the display quality. For the gate driver 14 of the high-resolution liquid crystal display panel manufactured by the amorphous germanium film process technology, the uniformity and stability of the components of the process have great variability. Therefore, after the liquid crystal display panel 12 is lit, the performance of the liquid crystal display panel 12 is often abnormal due to the stress of the internal transistor of the gate driver 14.

Therefore, the main object of the present invention is to provide an improvement in leakage current due to a bias effect. The shift register can still smoothly output waveforms under different process conditions to solve the above problems of the prior art.

In accordance with the above objects of the present invention, the present invention provides a shift register comprising a plurality of shift register units connected in series. Each shift register unit includes a boost circuit, a first clock pull-down module, and a second clock pull-down module. The boost circuit includes a first transistor, a second transistor, and a third transistor. The drain, the gate and the source of the first transistor are respectively coupled to the first clock signal, the first node, and the driving signal end. The drain, the gate and the source of the second transistor are respectively coupled to the first clock signal, the first node and an output signal terminal. The drain and the gate of the third transistor are coupled to one of the driving signal terminals of the previous stage shift register unit, and the source thereof is coupled to the first node. The first clock pull-down module includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a first driving circuit. The drain, the gate and the source of the fourth transistor are respectively coupled to the first node, the second node and the output node of the boosting circuit. The drain, the gate and the source of the fifth transistor are respectively coupled to the output node, the second node, and the first power voltage. The drain, the gate and the source of the sixth transistor are respectively coupled to the driving signal terminal, the second node, and the first power voltage. The drain, the gate and the source of the seventh transistor are respectively coupled to the second node, the output node, and the first power voltage.

The second clock pull-down module includes an eighth transistor, a ninth transistor, a tenth transistor, and a second driving circuit. The drain, the gate and the source of the eighth transistor are respectively coupled to the driving signal terminals of the first node, a third node and the shifting temporary storage unit of the previous stage. The ninth transistor has a drain, a gate and a source coupled to the output node, the second clock signal and the first power voltage. The drain, the gate and the source of the tenth transistor are respectively coupled to the driving signal terminal and the second clock signal And the first supply voltage. In addition, the phase of the first clock signal and the second clock signal are different by 180 degrees. The voltage level of the first power voltage is lower than the first clock signal or the lowest voltage level of the second clock signal.

According to an embodiment of the invention, the first driving circuit comprises an eleventh transistor, a twelfth transistor, and a thirteenth transistor. The drain and the gate of the eleventh transistor are coupled to the first clock signal, and the source thereof is coupled to a fourth node. The drain of the twelfth transistor is coupled to the fourth node, and the gate and the source are coupled to a second clock signal. The drain, the gate and the source of the thirteenth transistor are respectively coupled to the first clock signal, the fourth node and the second node. The second driving circuit includes a fourteenth transistor, a fifteenth transistor, and a fifteenth transistor. The drain and the gate of the fourteenth transistor are coupled to the second clock signal, and the source thereof is coupled to the first node. The drain of the fifteenth transistor is coupled to the fifth node, and the gate and the source are coupled to the first clock signal. The drain, the gate and the source of the fifteenth transistor are respectively coupled to the second clock signal, the fifth node and the third node.

In another embodiment, the second driving circuit further includes a seventeenth transistor, wherein the drain, the gate and the source are respectively coupled to the driving signal of the third node and the previous stage shift register unit. And the first supply voltage.

In yet another embodiment. The first driving circuit includes an eleventh transistor, and the drain, the gate and the source are respectively coupled to the first clock signal, a second power voltage, and the second node. The second driving circuit includes a twelfth transistor, and the drain, the gate and the source are respectively coupled to the second clock signal, the second power voltage, and the third node.

The above and other objects, features and advantages of the present invention will become more apparent and understood.

Please refer to FIG. 4, which is a circuit diagram of the shift register unit 100(n) of the first embodiment of the shift register of the present invention. The shift register of this embodiment can be applied to a gate driver of a liquid crystal display. The shift register includes a plurality of cascade-connected shift register units 100(n). The shift register unit 100(n) is configured to use the first clock signal CK, the second clock signal XCK, and a shift register unit 100(n-1) before each shift register unit 100(n). The driving signal pulse of the driving signal terminal ST(n-1) outputs the scanning signal pulse and the driving signal pulse from the output terminal OUT(n) and the driving signal terminal ST(n) of each shift register unit 100(n), respectively. . After the first stage shift register unit 100(1) receives the trigger start pulse Vst from the drive signal terminal ST(0), the shift register unit 100(1) is separated by a system clock cycle. An output signal pulse ST(1) is generated. Next, each shift register unit 100(n) is based on the first clock signal CK, the second clock signal XCK, and each shift register unit 100(n). The driving signal pulse outputted by the previous shift register unit 100(n-1) at the driving signal terminal ST(n-1) is applied to each shift register unit 100(n) every other system clock. The output terminal OUT(n) outputs an output signal pulse, which is a scan signal pulse, which is used to turn on the corresponding pixel transistor. The phase of the first clock signal CK and the second clock signal XCK are 180 degrees out of phase.

Each shift register unit 100(n) includes a pull-up circuit 102, a first clock pull-down module 104, and a second clock pull-down module 106. The boosting circuit 102 is coupled to the first clock signal CK for providing an output signal pulse at the output terminal OUT(n). The lifting module 102 includes a first transistor T1, a second transistor T2, and a third transistor T3. The drain, the gate and the source of the transistor T1 are respectively coupled to the first clock signal CK, the first node Q, and the driving signal terminal ST(n). The drain, the gate and the source of the transistor T2 are respectively coupled to the first clock signal CK, the first node Q, and the output signal terminal ST(n). The drain and the gate of the transistor T3 are coupled to the driving signal terminal ST(n-1) of the previous stage shift register unit 100(n-1), and the source thereof is coupled to the first node Q1. In the present invention, the low voltage level V _{L of the} clock signals CK and XCK is less than the voltage level of the DC power supply voltage V _SS . For example, the low voltage level V _{L of the} clock signals CK and XCK may be -12V, and the voltage level of the DC power supply voltage V _SS can be -9V.

The first clock pull-down module 104 is configured to receive the first clock signal CK, and turn on the first clock pull-down module 104, which includes a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, Seven transistors T7 and a first driving circuit 110. The drain, the gate and the source of the transistor T4 are respectively coupled to the first node Q, the second node K, and the output node OUT(n). The drain, the gate and the source of the fifth transistor T5 are respectively coupled to the output node OUT(n), the second node K, and the first power voltage V _SS . The drain, the gate and the source of the transistor T6 are respectively coupled to the driving signal terminal ST(n), the second node K, and the first power voltage V _SS . The drain, the gate and the source of the transistor T7 are respectively coupled to the second node K, the output node OUT(n) and the first power voltage V _SS . The first driving circuit 110 includes an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13. The drain and the gate of the transistor T11 are coupled to the first clock signal CK, and the source thereof is coupled to the fourth node S. The gate of the transistor T12 is coupled to the fourth node S, and the gate and the source are coupled to the second clock signal XCK. The drain, the gate and the source of the transistor T13 are respectively coupled to the first clock signal CK, the fourth node S and the second node K.

The second clock pull-down module 106 is configured to receive the second clock signal XCK, and turn on the second clock pull-down module 106, which includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a Two drive circuit 112. The drain, the gate and the source of the transistor T8 are respectively coupled to the first node Q, the third node P, and the driving signal terminal ST(n-1) of the previous stage shift register unit 100(n-1). The drain, the gate and the source of the ninth transistor T9 are respectively coupled to the output node OUT(n), the second clock signal XCK, and the first power voltage V _SS . The drain, the gate and the source of the transistor T10 are respectively coupled to the driving signal terminal ST(n), the second clock signal XCK and the first power voltage V _SS . The second driving circuit 112 is coupled to the gate of the transistor T8 for pulling down the voltage of the first node Q. The second driving circuit 112 includes a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, and a seventeenth transistor T17. The drain and the gate of the transistor T14 are both coupled to the second clock signal XCK, and the source thereof is coupled to the first node (N). The gate of the transistor T15 is coupled to the fifth node N, and the gate and the source are coupled to the first clock signal CK. The drain, the gate and the source of the transistor T16 are respectively coupled to the second clock signal XCK, the fifth node N and the third node P. The drain, the gate and the source of the transistor T17 are respectively coupled to the third node P, the driving signal terminal ST(n-1) of the previous stage shift register unit 100(n-1), and the first power voltage. V _SS .

Please refer to FIG. 4 and FIG. 5 at the same time. FIG. 5 is a timing chart of each signal and node of FIG. During the period t0-t1, the first clock signal CK is at a low voltage level, and the second clock signal XCK is at a high voltage level. The pinning signal from the driving signal terminal ST(n-1) of the previous stage shift register unit 100(n-1) is also at a high voltage level, so that the transistor T3 turns on. At this time, the potential of the node Q starts to be pulled high. At the same time, the voltage level output by the first driving circuit 110 at the node K is the low voltage level V _L , so the transistors T4, T5, and T6 are turned off. However, the output of the second driving circuit 112 at the node P is the high voltage level V _H , so the transistors T9 and T10 respectively turn on the low voltage level V _SS to the output terminal OUT(n) and the driving signal terminal ST(n). . The transistor T8 turns on the high voltage level V _H to the node Q.

Please be careful, because the gate potential of the closed non-conducting transistors T4, T5, T6 is equal to V _L , which is exactly the lowest voltage level of the first clock signal CK, and the potential of the source is equal to the power supply voltage V _SS Therefore, at this time, the gate-source voltage difference Vgs of the transistors T4, T5, and T6 is lower than 0V. For example, if the low voltage level V _{L of the} clock signal CK is -12V, and the voltage level of the DC power supply voltage V _SS is -9V, then the gate-source voltage difference of the transistors T4, T5, and T6 is at this time. Vgs is equal to -3V. Referring to Fig. 3, when the gate-source voltage difference Vgs of the transistor is -3V, the value of the drain current Id is much smaller than the value of the drain-source voltage difference Vgs at 0V. In other words, the voltage of the node Q decreases by the decrease of the leakage current of the transistor T4, so the waveforms of the output of the driving signal terminal ST(n) and the output terminal OUT(n) controlled by the transistors T1 and T2 can be working normally.

During the period t1-t2, the first clock signal CK is at the high voltage level V _H , so that the voltage level output by the first driving circuit 110 at the node K is the high voltage level V _H , so the transistors T4, T5, The T6 system turns on. At the same time, the driving signal of the driving signal terminal ST(n-1) of the second clock signal XCK and the previous stage shift register unit 100(n-1) is at the low voltage level V _L , and the potential of the node P is at this time. The low voltage level V _L , so the transistors T8, T9, T10 are closed and non-conducting. However, the potential of the node Q may float due to the floating effect, and jumps from the level V ₂ to the level V ₁ as the first clock signal CK rises due to the capacitive effect. When the potential of the node Q jumped level V _1, transistors T1 and T2 are turned ON when the first clock signal CK, resulting in the output terminal OUT (n) and the drive signal terminal ST (n) outputs a high voltage level .

Please turn off the non-conducting transistors T8, T9, T10. Since the potential of the gate is equal to V _L , it is exactly the lowest voltage level of the second clock signal XCK, and the potential of the source is equal to the power supply voltage V. _SS . Therefore, the gate-source voltage difference Vgs of the transistors T8, T9, and T10 is lower than 0V. For example, if the low voltage level V _{L of the} clock signals CK and XCK is -12V, and the DC power supply voltage V _SS When the voltage level is -9V, the gate-source voltage difference Vgs of the transistors T8, T9, and T10 is equal to -3V. Referring to Fig. 3, when the gate-source voltage difference Vgs of the transistor is -3V, the value of the drain current Id is much smaller than the value of the gate-source voltage difference Vgs at 0V, and the voltage of the node Q is The leakage current of the transistor T8 is reduced and the amount of decrease is smaller, so the output waveform can operate normally.

During the period t2-t3, the first clock signal CK is at a low voltage level, and the second clock signal XCK is at a high voltage level. The driving signal from the driving signal terminal ST(n-1) of the previous stage shift register unit 100(n-1) is also at a low voltage level, so that the transistor T3 is turned off. At the same time, the voltage level output by the first driving circuit 110 at the node K is the low voltage level V _L , so the transistors T4, T5, and T6 are turned off. However, the output of the second driving circuit 112 at the node P is the high voltage level V _H , so the transistors T9 and T10 respectively turn on the low voltage level V _SS to the output terminal OUT(n) and the driving signal terminal ST(n). . Transistor T8 turns on to pull the potential of node Q down to V _SS . The shift register of this embodiment can be applied to a gate driver of a liquid crystal display.

Please refer to FIG. 6. FIG. 6 is a circuit diagram of the shift register unit 200(n) of the second embodiment of the shift register of the present invention. Each shift register unit 200(n) includes a pull-up circuit 102, a first clock pull-down module 104, and a second clock pull-down module 206. The circuit structure of the boost circuit 102 and the first clock pull-down module 104 of the shift register unit 200(n) of the present embodiment is the same as the shift register unit 100(n) shown in FIG. 4, and the second The circuit configuration of the transistors T8, T9, and T10 of the clock pull-down module 206 is the same as that of the shift register unit 100(n) shown in FIG. 4, and therefore its operation will not be described herein. The second driving circuit 212 includes a fourteenth transistor T14, a fifteenth transistor T15, and a sixteenth transistor T16. The drain and the gate of the transistor T14 are coupled to the second clock signal XCK, and the source thereof is coupled to the first node (N). The gate of the transistor T15 is coupled to the fifth node N, and the gate and the source are coupled to the first clock signal CK. The drain, the gate and the source of the transistor T16 are respectively coupled to the second clock signal XCK, the fifth node N and the third node P. The second driving circuit 212 shown in FIG. 6 and the second driving circuit 112 shown in FIG. 4 are all coupled to the gate of the transistor T8 and used to turn on the transistor when receiving the second clock signal XCK. T8. In this embodiment, the low voltage level V _{L of the} clock signals CK and XCK is less than the voltage level of the DC power supply voltage V _SS . The operation of the shift register unit 200(n) is similar to that of the shift register unit 100(n), and the timing chart of the output voltage change corresponding to each node is identical to that of FIG. I will not repeat them here.

Please refer to FIG. 7. FIG. 7 is a circuit diagram of the shift register unit 300(n) of the third embodiment of the shift register of the present invention. Each shift register unit 300(n) includes a pull-up circuit 102, a first clock pull-down module 304, and a second clock pull-down module 306. The lifting circuit 102 of the shift register unit 300(n) of the present embodiment is the same as the shift register unit 100(n) shown in FIG. 4, and the transistors T4-T7 of the first clock pull-down circuit 304, and The circuit structure of the transistors T8-T10 of the second clock pull-down module 306 is the same as that of the shift register unit 100(n) shown in FIG. 4, and therefore its operation will not be described herein. The first driving circuit 310 includes an eleventh transistor T11, and the drain, the gate and the source are respectively coupled to the first clock signal CK, the second DC power voltage V _DD and the second node K. The first driving circuit 310 shown in FIG. 7 and the first driving circuit 110 shown in FIG. 4 are all coupled to the gate of the transistor T4, and are used to turn on the transistor when receiving the first clock signal CK. T4. The second driving circuit 312 includes a twelfth transistor T12, and the drain, the gate and the source are respectively coupled to the second clock signal XCK, the second power voltage V _DD and the third node P. The second driving circuit 312 shown in FIG. 7 and the second driving circuit 112 shown in FIG. 4 are all coupled to the gate of the transistor T8, and are used to turn on the transistor when receiving the second clock signal XCK. T8. In this embodiment, the low voltage level V _{L of the} clock signals CK and XCK is less than the voltage level of the DC power supply voltage V _SS . The operation of the shift register unit 300(n) is similar to that of the shift register unit 100(n), and the timing chart of the output voltage change corresponding to each node is identical to that of FIG. I will not repeat them here.

Please refer to FIG. 8. FIG. 8 is a circuit diagram of the shift register unit 400(n) of the fourth embodiment of the shift register of the present invention. Each shift register unit 400(n) includes a pull-up circuit 102, a first clock pull-down module 404, and a second clock pull-down module 406. The boosting circuit 102 of the shift register unit 400(n) of the present embodiment is the same as the shift register unit 100(n) shown in FIG. 4, and the transistors T4-T7 and the first of the first clock pull-down circuit 404. The circuit structure of the transistors T8-T10 of the two-clock pull-down module 406 is the same as that of the shift register unit 100(n) shown in FIG. 4, and therefore its operation will not be described herein. The first oscillating circuit 410 includes an eleventh transistor T11, and the drain, the gate and the source are respectively coupled to the first clock signal CK, the second DC power voltage V _DD and the second node K. The first driving circuit 410 shown in FIG. 8 and the first driving circuit 110 shown in FIG. 4 are all coupled to the gate of the transistor T4, and are used to turn on the transistor when receiving the first clock signal CK. T4. The second driving circuit 412 of the embodiment is substantially a clock generator for the second clock signal XCK, so that the drain and the source of the transistor T8 are directly coupled to the second clock signal XCK, that is, The gate of the transistor T8 is coupled to the node P, and the node P is directly coupled to the second clock signal XCK, and is no longer connected to other physical circuits. The transistor T8 turns on when it receives the second clock signal XCK. In this embodiment, the low voltage level V _{L of the} clock signals CK and XCK is less than the voltage level of the DC power supply voltage V _SS . The operation of the shift register unit 400(n) is similar to that of the shift register unit 100(n), and the timing chart of the output voltage change corresponding to each node is identical to that of FIG. I will not repeat them here.

Compared to the prior art, the present invention shift register in each stage in the shift register unit, utilizing the clock signal CK, XCK low voltage level V _L is less than the DC supply voltage line V _SS voltage level of the The characteristics are such that when the transistors T4 and T8 are turned off, the gate-source voltage difference Vgs is lower than 0V. Since the gate-source voltage difference Vgs of the transistor is below 0V, the value of the leakage current is much smaller than the value of the drain current of the gate-source voltage difference Vgs at 0V. Therefore, the voltage of the node Q is reduced by the leakage current of the transistors T4 and T8 being smaller, so as to control the power of the driving signal terminal ST(n) and the output terminal OUT(n) according to the voltage of the node Q. The output waveforms of the crystals T1 and T2 can be greatly improved. Even if the transistor has a slight difference in the gate-source voltage difference Vgs at 0V due to process variations, as long as the gate-source voltage difference Vgs is reduced to -3V or lower, the leakage current can even exceed 100 times, so the difference in leakage current caused by the difference in process of the transistor is even more insignificant.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be variously modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

10‧‧‧LCD display

12‧‧‧LCD panel

14‧‧‧ Gate Driver

16‧‧‧Source Driver

20‧‧‧ pixel unit

22‧‧‧Optoelectronics

100(n)‧‧‧Shift register unit

200(n)‧‧‧Shift register unit

300(n)‧‧‧Shift register unit

400(n)‧‧‧Shift register unit

T1-T17‧‧‧O crystal

102‧‧‧Upgrading circuit

104, 204‧‧‧ first clock pull-down module

106‧‧‧Second clock pull-down module

110, 310‧‧‧ first drive circuit

112, 212‧‧‧second drive circuit

410‧‧‧First drive circuit

312, 412‧‧‧ second drive circuit

CK‧‧‧ first clock signal

XCK‧‧‧ second clock signal

P, Q, K‧‧‧ nodes

N, S‧‧‧ nodes

OUT(n)‧‧‧ output

ST(n), ST(n-1)‧‧‧ drive signal end

C1, C2‧‧‧ capacitor

Figure 1 is a functional block diagram of a prior art liquid crystal display.

Figure 2 is a circuit diagram of a shift register unit of a prior art shift register.

Figure 3 is a plot of source-gate voltage difference versus leakage current for a transistor.

Figure 4 is a circuit diagram of a shift register unit of the first embodiment of the shift register of the present invention.

Figure 5 is a timing diagram of each signal and node of Figure 4.

Figure 6 is a circuit diagram of a shift register unit of the second embodiment of the shift register of the present invention.

Figure 7 is a circuit diagram of a shift register unit of the third embodiment of the shift register of the present invention.

Figure 8 is a circuit diagram of a shift register unit of a fourth embodiment of the shift register of the present invention.

100(n)‧‧‧Shift register unit

C1, C2‧‧‧ capacitor

T1-T17‧‧‧O crystal

102‧‧‧Upgrading circuit

104‧‧‧First clock pull-down module

106‧‧‧Second clock pull-down module

110‧‧‧First drive circuit

112‧‧‧Second drive circuit

CK‧‧‧ first clock signal

XCK‧‧‧ second clock signal

P, Q, K‧‧‧ nodes

N, S‧‧‧ nodes

OUT(n)‧‧‧ output

ST(n), ST(n-1)‧‧‧ drive signal end

Claims (17)

A shift register includes: a plurality of shift temporary storage units, wherein the plurality of shift temporary storage units are coupled in series, and each shift temporary storage unit is configured to use a first clock a signal, a second clock signal, and one of the shift register units of each of the shift register units drive a signal pulse to output an output signal pulse of each shift register unit, each shift register unit The method includes: a pull-up module, configured to provide the output signal according to the first clock signal, comprising: a first transistor, wherein the drain, the gate and the source are respectively coupled to The first clock signal, a first node, and a driving signal end; a second transistor having a drain, a gate and a source coupled to the first clock signal, the first node, and an output a third transistor having a drain and a gate coupled to a driving signal terminal of the previous stage shift register unit, the source of which is coupled to the first node; and a first clock pull-down module (pull-down module), configured to receive the first clock signal, and turn on the first clock pulldown The module includes: a fourth transistor having a drain, a gate, and a source coupled to the first node, a second node, and an output node of the boosting circuit; and a fifth transistor; The drain, the gate and the source are respectively coupled to the output node, the second node and a first power voltage; and a sixth transistor has a drain, a gate and a source coupled to the driving signal end respectively , a second node and the first power supply voltage; a seventh transistor having a drain, a gate and a source coupled to the second node, the output node and the first power supply voltage, respectively; and a first driving circuit a second transistor connected to the gate of the fourth transistor for receiving the first clock signal; a second clock pull-down module for receiving the second clock The signal, the second clock pull-down module is turned on, comprising: an eighth transistor, wherein the drain, the gate and the source are respectively coupled to the first node, the third node, and the previous stage shift register One of the cells drives a signal terminal; a ninth transistor having a drain, a gate and a source coupled to the output node, the second clock signal and the first power supply voltage, respectively; a tenth transistor; The drain, the gate and the source are respectively coupled to the driving signal terminal, the second clock signal and the first power voltage; and a second driving circuit coupled to the gate of the eighth transistor, When the second clock signal is received, the eighth transistor is turned on, wherein the first clock signal is The second is the lowest voltage level of the clock signal line is lower than the voltage level of the first power supply voltage, the first pull-down clock module is actuated when the second line module is interacting with the drop-down pulse. The shift register according to claim 1, wherein the first driving circuit comprises: an eleventh transistor, wherein the drain and the gate are coupled to the first clock signal, and the source thereof Coupled to a fourth node; a twelfth transistor having a drain coupled to the fourth node, a gate and a source coupled to a second clock signal; a thirteenth transistor having a drain, a gate and a source The poles are respectively coupled to the first clock signal, the fourth node and the second node. The shift register according to claim 2, wherein the second driving circuit comprises: a fourteenth transistor, wherein the drain and the gate are coupled to the second clock signal, and the source thereof Coupling to the first node; a fifteenth transistor, the drain is coupled to the fifth node, the gate and the source are coupled to the first clock signal; and a sixteenth transistor, The drain, the gate and the source are respectively coupled to the second clock signal, the fifth node and the third node. The shift register according to claim 3, wherein the second driving circuit further comprises: a seventeenth transistor, wherein the drain, the gate and the source are respectively coupled to the third node, One of the previous stage shift register units drives the signal terminal and the first power supply voltage. The shift register according to claim 1, wherein the first driving circuit comprises: an eleventh transistor, wherein the drain, the gate and the source are respectively coupled to the first clock signal a second supply voltage and the second node. The shift register according to claim 5, wherein the second driving circuit comprises: a twelfth transistor, wherein the drain, the gate and the source are respectively coupled to the second clock signal The second power voltage and the third node. The shift register according to claim 5, wherein the third node is coupled to the first Two-clock signal. The shift register of claim 1, wherein the first clock signal and the second clock signal are 180 degrees out of phase. The shift register as described in claim 1 is applied to a liquid crystal display. A shift register unit includes: a pull-up module for providing the output signal according to a first clock signal, comprising: a first transistor, a drain, a gate The pole and the source are respectively coupled to the first clock signal, a first node, and a driving signal terminal, and a second transistor has a drain, a gate and a source coupled to the first clock signal respectively a first transistor and an output signal terminal; a third transistor having a drain and a gate coupled to one of the driving signal terminals of the previous stage shift register unit, the source of which is coupled to the first node; a first clock pull-down module is configured to receive the first clock signal and turn on the first clock pull-down module, comprising: a fourth transistor, the drain, the gate and the source are respectively coupled Connected to the first node, a second node, and an output node of the boosting circuit; a fifth transistor having a drain, a gate, and a source coupled to the output node, the second node, and a first a power supply voltage; a sixth transistor, wherein the drain, the gate and the source are respectively coupled to the driving signal terminal, The second node and the first power voltage; a seventh transistor, the drain, the gate and the source are respectively coupled to the second node, the output node and the first power voltage; and a first driving circuit coupled to the fourth transistor a gate for opening the fourth transistor when receiving the first clock signal; a second clock pull-down module for receiving a second clock signal, turning on the second clock pull-down mode The group includes: an eighth transistor having a drain, a gate and a source coupled to the first node, a third node, and a driving signal terminal of the first stage shift register unit; a transistor, the drain, the gate and the source are respectively coupled to the output node, the second clock signal and the first power voltage; and a tenth transistor, the drain, the gate and the source are respectively coupled Connecting to the driving signal terminal, the second clock signal and the first power voltage; and a second driving circuit coupled to the gate of the eighth transistor for receiving the second clock signal Turning on the eighth transistor, wherein the first clock signal or the lowest voltage of the second clock signal Lower than the bit line voltage level of the first power supply voltage, the first pull-down clock module is actuated when the second line module is interacting with the drop-down pulse. The shift register unit of claim 10, wherein the first driving circuit comprises: an eleventh transistor, wherein the drain and the gate are coupled to the first clock signal, and the source thereof Coupled to a fourth node; a twelfth transistor having a drain coupled to the fourth node, a gate and a source coupled to a second clock signal; a thirteenth transistor having a drain, a gate and a source The poles are respectively coupled to the first clock signal, the fourth node and the second node. The shift register unit of claim 11, wherein the second driving circuit comprises: a fourteenth transistor, wherein the drain and the gate are coupled to the second clock signal, and the source thereof Coupling to the first node; a fifteenth transistor, the drain is coupled to the fifth node, the gate and the source are coupled to the first clock signal; and a sixteenth transistor, The drain, the gate and the source are respectively coupled to the second clock signal, the fifth node and the third node. The shift register unit of claim 12, wherein the second drive circuit further comprises: a seventeenth transistor, wherein the drain, the gate and the source are respectively coupled to the third node, One of the previous stage shift register units drives the signal terminal and the second power supply voltage. The shifting temporary storage unit of claim 10, wherein the first driving circuit comprises: an eleventh transistor, wherein the drain, the gate and the source are respectively coupled to the first clock signal a second supply voltage and the second node. The shift register unit of claim 14, wherein the second drive circuit package The circuit includes a twelfth transistor, and the drain, the gate and the source are respectively coupled to the second clock signal, the second power voltage, and the third node. The shift register unit of claim 14, wherein the third node is coupled to the second clock signal. The shift register unit of claim 10, wherein the phase of the first clock signal and the second clock signal are different by 180 degrees.