TWI449010B - Display device of the drive circuit - Google Patents

Description

Display device driving circuit

The invention relates to a driving circuit, in particular to a driving circuit of a display device.

Since the liquid crystal display has been developed to the generation of thin display, and the gate driver on Array (GOA) is more simplifies the design of the driving circuit on the liquid crystal display, GOA technology is widely used in the field of liquid crystal display. Technology, especially on large-size thinned substrates, and on the basis of GOA technology, the reaction efficiency of liquid crystal displays is better, making GOA technology application ratio very high, so the technical field of liquid crystal displays is for gate drive circuit substrates. More and more research and development, and continuous improvement.

Please refer to FIG. 1A and FIG. B, which are schematic diagrams of a driving circuit of a conventional display device and a driving unit thereof. As shown in FIG. 1A, the conventional driving circuit 10 includes a clock generator 11 and a plurality of driving units (the first driving unit 12, a second driving unit 13, and a third driving unit 14 and one). The fourth driving unit 15 is configured as an example, wherein the clock generator 11 generates a first clock signal C1, a second clock signal C2 and a third clock signal C3, respectively, and the first driving unit 12 is coupled. An input signal INPUT is coupled to the third clock signal C3, the first driving unit 12 outputs a first output signal O1, and the second driving unit 13 is coupled to the first clock signal C1 and coupled to the first output signal O1. The second driving unit 13 outputs a second output signal O2, and the third driving unit 14 is coupled to the second clock signal C2 and coupled to the second output signal O2. The driving unit 14 outputs a third output signal O3, the fourth driving unit 15 is coupled to the third clock signal C3 and coupled to the third output signal O3, and the fourth driving unit 15 outputs a fourth output signal O4.

As shown in FIG. B, it is a schematic diagram of an equivalent circuit of a single driving unit, wherein each driving unit includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth The transistor M4 is connected to a capacitor Cb. The first end of the first transistor M1 is short-circuited and coupled to the output signal On-1 of the previous stage driving unit, and the third end of the first transistor M1 is coupled to the second circuit. A first end of one of the crystals M2, a second end of the third transistor M3, and a first end of the capacitor Cb. The second end of the second transistor M2 is coupled to a clock signal (which is one of the clock signals C1, C2, and C3), and the third end of the second transistor M2 is coupled to the fourth battery. The second end of one of the crystals M4 and the second end of the capacitor Cb generate an output signal On. The first end of the third transistor M3 is coupled to the output signal On+2 of the second stage driving unit, and the third end of the third transistor M3 is coupled to the ground end. The first end of the fourth transistor M4 is coupled to the voltage signal V _{CLK of the} clock signal, and the third end of the fourth transistor M4 is coupled to the ground end.

As shown in the second figure, it is a signal waveform diagram of the conventional driving circuit 10, wherein the first driving unit 12, the second driving unit 13, and the third driving unit 14 are made by the clock signals C1, C2, and C3. The four driving units 15 sequentially output the output signals O1, O2, O3, and O4. However, since the driving times t1, t2, t3, and t4, the output signals O1, O2, O3, and O4 are due to the first transistor M1 of the driving unit. The short-circuit conduction design causes the first transistor M1 to operate in a saturation section, and the output signal is related to the voltage of the capacitor Cb, so the output voltage is slowly boosted to a high level, and further, due to the first transistor M1 The short-circuit conduction design causes the output signal of the first driving unit 12 to be the difference between the supply voltage and the threshold voltage, thus affecting the operation of the second transistor M2.

Therefore, the present invention provides a driving circuit for a display device, which can provide a better driving operation and can provide a better turn-on voltage for conducting a crystal and providing a better output signal to solve the above-mentioned problems. Drive unit drive problem.

The main purpose of the present invention is to provide a driving circuit for a display device, which uses the output signal of the driving module to drive the charging and discharging unit of the next-stage driving module to achieve fast charging and provide a better turn-on voltage.

The invention provides a driving circuit for a display device, comprising a first control unit, a first charging and discharging unit, a second control unit and a second charging and discharging unit. The first control unit is coupled to the first input signal, the one-two input signal, and the first clock signal, and generates a first control signal according to the first input signal, the second input signal, and the first clock signal; The first charging and discharging unit is coupled to the first clock signal, a second clock signal, and the first control unit, and generates a first signal according to the first clock signal, the second clock signal, and the first control signal. An output signal is coupled to the first control signal, the first output signal, and the second clock signal, and generates a signal according to the first control signal, the first output signal, and the second clock signal a second control signal; and the second charging and discharging unit is coupled to the first clock signal, a second clock signal, and the second control unit according to the first clock signal, the second clock signal, and the first The second control signal generates a second output signal.

10‧‧‧Custom drive circuit

11‧‧‧ Clock Generator

12‧‧‧First drive unit

13‧‧‧Second drive unit

14‧‧‧ Third drive unit

15‧‧‧fourth drive unit

20‧‧‧Drive circuit

22‧‧‧First drive module

221‧‧‧Optoelectronics

222‧‧‧Optoelectronics

223‧‧‧Optoelectronics

224‧‧‧Optoelectronics

225‧‧‧Optoelectronics

226‧‧‧Optoelectronics

227‧‧‧Optoelectronics

228‧‧‧Optoelectronics

229‧‧‧Optoelectronics

230‧‧‧ Capacitance

231‧‧‧ Capacitance

24‧‧‧Second drive module

241‧‧‧Optoelectronics

242‧‧‧Optoelectronics

243‧‧‧Optoelectronics

244‧‧‧Optoelectronics

245‧‧‧Optoelectronics

246‧‧‧Optoelectronics

247‧‧‧Optoelectronics

248‧‧‧Optoelectronics

249‧‧‧Optoelectronics

250‧‧‧ Capacitance

251‧‧‧ Capacitance

30‧‧‧Drive circuit

32‧‧‧First drive module

34‧‧‧Second drive module

36‧‧‧ Third drive module

38‧‧‧Fourth drive module

A1‧‧‧First control signal

A2‧‧‧second control signal

A3‧‧‧ third control signal

A4‧‧‧ fourth control signal

An‧‧‧second control signal

An-1‧‧‧ first control signal

An-2‧‧‧ first input signal

B1‧‧‧First feedback control signal

B2‧‧‧Second feedback control signal

B3‧‧‧ Third feedback control signal

B4‧‧‧ Fourth feedback control signal

Bn‧‧‧ feedback control signal

Bn-1‧‧‧ signal

Bn+1‧‧‧ signal

C1‧‧‧ first clock

C2‧‧‧ second clock

C3‧‧‧ third clock

Cb‧‧‧ capacitor

CLK‧‧‧ first clock signal

INPUT‧‧‧ input signal

M1‧‧‧first transistor

M2‧‧‧second transistor

M3‧‧‧ third transistor

M4‧‧‧ fourth transistor

O1‧‧‧ first output signal

O2‧‧‧second output signal

O3‧‧‧ third output signal

O4‧‧‧ fourth output signal

OUT1‧‧‧ first output signal

OUT2‧‧‧second output signal

OUT3‧‧‧ third output signal

OUT4‧‧‧ fourth output signal

OUTn‧‧‧second output signal

OUTn-1‧‧‧ first output signal

OUTn-2‧‧‧Second input signal

OUTn+1‧‧‧ third output signal

On-1‧‧‧ output signal

On‧‧‧Output signal

On+2‧‧‧ output signal

V _CLK ‧‧‧ voltage

Vss‧‧‧ reference level

T1‧‧‧ drive time

T2‧‧‧ drive time

T3‧‧‧ drive time

T4‧‧‧ drive time

XCLK‧‧‧second clock signal

The first A is a schematic diagram of a conventional driving circuit; the first B is a schematic diagram of a driving unit of the first A; the second is a signal waveform of a conventional driving circuit; 3 is a schematic diagram of a preferred embodiment of the present invention; FIG. 3B is a signal waveform diagram of a preferred embodiment of the present invention; and FIG. 4 is a block diagram of another embodiment of the present invention.

For a better understanding and understanding of the structural features and the achievable effects of the present invention, please refer to the preferred embodiment and the detailed description as follows: please refer to Figure 3A, which is A circuit diagram of an embodiment of the invention. As shown in the figure, the present invention is a driving circuit 20, which is applied to a plurality of driving modules. The driving circuit 20 of the present embodiment is illustrated by a first driving module 22 and a second driving module 24. However, the present invention is not limited thereto, and the number of the driving modules is determined according to the size of the display area of the display device, wherein the first driving module 22 includes a plurality of transistors 221, 222, 223, 224, 225, 226, 227, 228. The second drive module 24 includes a plurality of transistors 241, 242, 243, 244, 245, 246, 247, 248, 249 and a plurality of capacitors 250, 251.

In the first driving module 22, the transistor 221 and the transistor 222 form a first control unit. The first end of the transistor 221 is coupled to a first input signal An-2, and the first end of the transistor 222. The first clock signal CLK is coupled to the second end of the transistor 222, and the second end of the transistor 221 is coupled to a second input signal OUTn-2. The first control signal An-1; the transistor 223, the transistor 224 and the capacitor 230 form a first charge and discharge unit, and the first end of the transistor 223 is coupled to the first control signal An-1, and the second transistor 223 One end of the transistor 230 is coupled to the first control signal An-1, and the second end of the transistor 223 is coupled to a second clock signal XCLK. , transistor The third end of the transistor 223 is coupled to the second end of the capacitor 230 and the second end of the transistor 224. The first end of the transistor 224 is coupled to the first clock signal CLK, one of the transistors 224. The third end is coupled to a reference level Vss, wherein the transistor 223 is used as a pull-up circuit of the first driving module 22, and the transistor 224 is used as a pull-down circuit of the first driving module 22.

Continuing the above, the transistor 225, the transistor 226 and the capacitor 231 are used as a first noise-free unit. The first end of the capacitor 231 is coupled to the first clock signal CLK, and the capacitor 231 is first. The first end of one of the transistors 225 is coupled to the first end of the transistor 225, the first end of the transistor 225 is coupled to the first input signal An-2, and the second end of the transistor 226 is coupled to the second end. The third output of the transistor 225 and the transistor 226 are coupled to the reference level Vss, wherein the transistor 225 and the capacitor 231 are coupled to the first control signal An-1. A signal Bn-1 is formed between the transistor 227 as a clearing unit of the first driving module 22, and the first end of the transistor 227 is coupled to the output signal of the second driving module 24, and one of the transistors 227 The second end is also coupled to the first control signal An-1, and the third end of the transistor 227 is also coupled to the reference level Vss, wherein the output signal of the second driving module 24 is a second output signal OUTn . In addition, the transistor 228 and the transistor 229 form a first feedback output unit, and the first end of the transistor 228 and the transistor 229 are coupled to the feedback control signal of the next driving module, that is, the second driving module 24 One of the feedback control signals Bn, the second end of the transistor 228 and the transistor 229 is coupled to the output end of the first control unit, that is, coupled to the first control signal An-1, and the third end of the transistor 228. The third end of the transistor 229 is coupled to the reference level Vss. The third end of the transistor 229 is also coupled to the reference level Vss.

In the second driving module 24, the transistor 241 and the transistor 242 form a second control unit. The first end of the transistor 241 is coupled to the first control signal An-1. The first end of the body 242 is coupled to the second clock signal XCLK, and the second end of the transistor 241 and the second end of the transistor 242 are coupled to the first output signal OUTn-1, and the third of the transistor 241 and the transistor 242. The terminal system outputs a second control signal An; the transistor 243, the transistor 244 and the capacitor 250 form a second charge and discharge unit, and the first end of the transistor 243 is coupled to the second control signal An, and the first of the transistors 243 The first end of the capacitor 250 is coupled to the second control signal An. The second end of the transistor 243 is coupled to the first clock signal CLK, and the transistor 243 is coupled to the first end of the capacitor 250. A third end is coupled to the second end of one of the capacitors 250 and the second end of the transistor 244. The first end of the transistor 244 is coupled to the second clock signal XCLK, and the third of the transistors 244 is third. The terminal is coupled to a reference level Vss, wherein the transistor 243 is used as a pull-up circuit of the second driving module 24, and the transistor 244 is used as a pull-down circuit of the second driving module 24.

Continuing the above, the transistor 245, the transistor 246 and the capacitor 251 are used as a second noise-free unit. The first end of the capacitor 251 is coupled to the second clock signal XCLK, and the capacitor 251 is first. The first end of one of the transistors 245 is coupled to the first end of the transistor 246, and the first end of the transistor 245 is coupled to the first control signal An-1, and the second end of the transistor 246 is coupled to the second end. Connected to the control output of the second control unit, that is, coupled to the second control signal An, the third end of the transistor 245 and the transistor 246 is coupled to the reference level Vss; the transistor 247 is used as the second driving module. The first end of one of the transistors 247 is coupled to the output signal of the next driving module (not shown). The second end of the transistor 247 is also coupled to the first control signal An-1. The third end of the transistor 247 is also coupled to the reference level Vss, wherein the output signal of the next driving module is a third output signal OUTn+1.

As shown in FIG. B, the first clock signal CLK and the second clock signal XCLK are pulse signals of opposite clocks, so the pulse signal fluctuations of each driving time are different. In the first driving time T1, the first clock signal CLK is off, and the second time pulse is The number XCLK is turned on, and the first driving module 22 is caused to generate the first control signal An-1, and the first control signal An-1 is associated with the first output signal OUTn-1, so when the first control signal An-1 When the signal is a high level signal, the first output signal OUTn-1 is turned into a high level signal. Since the first driving module 22 does not have the previous stage driving unit, the first output signal OUTn-1 is regarded as a dummy signal, and the second control signal An of the second driving module 24 is associated with the first output signal OUTn-1, so when the first output signal OUTn-1 is a high level signal, The second control signal An changes to a high level signal.

When the second driving time T2 is continued, the first clock signal CLK is turned on, and the second clock signal XCLK is turned off, and the second control signal An is caused to be a superimposed high level signal, so that the second output signal is OUTn is generated very quickly, so that the next-stage driving unit is also affected by the high-level signal of the second superimposed signal, such as the second driving module 24, so that the output signal OUTn+1 is also generated rapidly. The feedback control signal Bn of the second driving module 24 corresponds to the output signal OUTn. Therefore, the first driving module 22 maintains the first output signal OUTn-1 at the level of Vss according to the feedback control signal Bn, and the second driving. The same is true for the module 24, that is, the second driving module 24 maintains the second output signal OUTn at the level of Vss according to the feedback control signal Bn+1.

Please refer to the fourth figure, which is a block diagram of another embodiment of the present invention. As shown in FIG. 4A, the driving circuit 30 of the present invention includes a clock generator (not shown) and a plurality of driving modules. The first driving module 32 and the second driving module 34 are in the embodiment. The three driving module 36 and the fourth driving module 38 are exemplified, but the present invention is not limited thereto, and the display device sets a corresponding number of driving modules according to the display area.

The clock generator of the driving circuit 30 generates the first clock signal CLK and the second clock signal XCLK, and the first driving module 32, the second driving module 34, the third driving module 36 and the fourth driving module 38 receiving the first clock signal CLK and the second clock signal respectively The XCLK is coupled to the reference level Vss at the same time, but each driving module and the adjacent driving module are oppositely arranged in the manner of connecting the clock signals. The electrical operation of the first driving module 32 is electrically operated as the first driving module 22 of the previous embodiment, and the second driving module 34, the third driving module 36 and the fourth driving module 38 are electrically operated. The electrical operation is the same as that of the second zone dynamic module 24 of the previous embodiment. Therefore, the first driving module 32 receives and generates a first control signal A1 and a first output signal OUT1 according to the clock signal CLK, XCLK and the reference level Vss, and the second driving module 34 is based on the clock signal CLK, The XCLK, the first control signal A1, and the reference level Vss generate and output a second control signal A2, a second output signal OUT2 and a first feedback control signal B1, and the first feedback control signal B1 is transmitted to The first driving module 32 controls the first driving module 32 to output the first output signal OUT1 corresponding to the reference level Vss.

The third driving module 36 generates and outputs a third control signal A3, a third output signal OUT3 and a second feedback control signal B2 according to the clock signal CLK, XCLK, the second control signal A2 and the reference level Vss. The second feedback control signal B2 is transmitted to the second driving module 34 to feedback the second output signal OUT2 that controls the second driving module 34 to output the corresponding reference level Vss. The fourth driving module 38 generates and outputs a fourth control signal A4, a fourth output signal OUT4 and a third feedback control signal B3 according to the clock signal CLK, XCLK, the third control signal A3 and the reference level Vss. The third feedback control signal B3 is transmitted to the third driving module 36 to feedback the third output signal OUT3 that controls the third driving module 36 to output the corresponding reference level Vss. Similarly, the fourth driving module 38 also outputs a third output signal OUT3 corresponding to the reference level Vss according to a fourth feedback control signal B4.

Since the first driving module 32 fails to receive the output signal output by the driving module of the previous stage, the first output signal OUT1 of the first driving module 32 has a slower charging and discharging than the output signal of the subsequent driving module. Time, and subsequent drive modules are all before The output signal of the first-level driving module accelerates the control signal, thereby accelerating the charging and discharging speed of the driving module, and the electrical comparison of the output signals is shown in Table 1 below.

It can be seen from the above that the driving circuit of the present invention provides the control signal and the output signal to the next-level driving module by the driving module to speed up the charging and discharging speed of the next-level driving module, and the control signal is controlled by the next-level driving module. The unit does not use the short circuit design, and the transistor in the control unit is not in the saturated working area, so the charging and discharging efficiency is faster. Moreover, the present invention further utilizes the noiseless unit to set the capacitance so that the driving module corresponds to the output. When the output signal of the Vss level is used, the direct current signal can be prevented from flowing directly to the Vss reference potential, thereby preventing the DC stress from remaining in the circuit, thereby improving the durability of the driving circuit.

In summary, the driving circuit of the display device of the present invention mainly uses the output signal and the control signal of the driving module to output to the next-stage driving module, so that the output signal of the next-level driving module can have better charging and discharging time. And the feedback control signal of the next-level driving module enables the driving module to maintain the output signal at a low level or a reference level according to the feedback control signal. This allows the drive circuit It has better control efficiency and higher accuracy.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

22‧‧‧First drive module

221‧‧‧Optoelectronics

222‧‧‧Optoelectronics

223‧‧‧Optoelectronics

224‧‧‧Optoelectronics

225‧‧‧Optoelectronics

226‧‧‧Optoelectronics

227‧‧‧Optoelectronics

228‧‧‧Optoelectronics

229‧‧‧Optoelectronics

230‧‧‧ Capacitance

231‧‧‧ Capacitance

24‧‧‧Second drive module

241‧‧‧Optoelectronics

242‧‧‧Optoelectronics

243‧‧‧Optoelectronics

244‧‧‧Optoelectronics

245‧‧‧Optoelectronics

246‧‧‧Optoelectronics

247‧‧‧Optoelectronics

248‧‧‧Optoelectronics

249‧‧‧Optoelectronics

250‧‧‧ Capacitance

251‧‧‧ Capacitance

Claims (10)

A driving circuit for a display device, comprising: a first driving module, receiving a first input signal, a second input signal, a first clock signal and a second clock signal, the first driving mode The group includes: a first control unit that receives the first input signal, the second input signal, and the first clock signal, and the first control unit is configured according to the first input signal, the second input signal, and the first The first charging and discharging unit is coupled to the first control unit and receives the first clock signal and the second clock signal, and the first charging and discharging unit is configured according to the first a first clock signal, the second clock signal and the first control signal generate a first output signal; and a second driving module receives the first clock signal, the second clock signal, the first Controlling the signal and the first output signal, the second driving module includes: a second control unit, receiving the first control signal, the first output signal and the second clock signal, the second control unit is configured according to the second control unit First control signal, the first Generating a second signal a control signal and the second clock signal, the first control signal drives the second control unit increases the first And a second charging and discharging unit coupled to the second control unit and receiving the first clock signal and the second clock signal, the second charging and discharging unit according to the first clock The signal, the second clock signal and the second control signal generate a second output signal, wherein the second control signal that increases the level drives the second charging and discharging unit to reduce the charging time and increase the second output signal. Current. The driving circuit of claim 1, wherein the first control unit comprises: a first transistor, a first end coupled to the first input signal, and a second end of the first transistor The first input signal is coupled to the second input signal; and the first transistor is coupled to the first clock signal, and the second end of the second transistor is coupled to the second input signal, the first The transistor and the third end of the second transistor output the first control signal. The driving circuit of claim 1, wherein the first charging and discharging unit comprises: a first transistor, a first end of which is coupled to the first control signal, and a second one of the first transistors The first end of the second clock signal is coupled to the second clock signal; a first end of the capacitor is coupled to the first control signal; and a second transistor is coupled to the first clock No. a third end of the first transistor, a second end of the capacitor, and a second end of the second transistor output the first output signal, and the third end of the second transistor is coupled to the third end Then take a reference level. The driving circuit of claim 1, wherein the second control unit comprises: a first transistor, a first end coupled to the first control signal, and a second end of the first transistor The first output signal is coupled to the first output signal; and a second transistor is coupled to the second clock signal, and the second end of the second transistor is coupled to the first output signal, the first The transistor and the third end of the second transistor output the second control signal. The driving circuit of claim 1, wherein the second charging and discharging unit comprises: a first transistor, a first end coupled to the second control signal, and a second one of the first transistors The first end is coupled to the first clock signal; a first end of the capacitor is coupled to the second control signal; and a second transistor is coupled to the second clock signal by a first end, the first a third end of the transistor, a second end of the capacitor, and a second end of the second transistor output the first output signal, and a third end of the second transistor is coupled to a reference level . The driving circuit of the first aspect of the invention, wherein the second driving module further comprises: a noise-free unit coupled to the second clock signal, the second control unit and a reference level Output a feedback control signal. The driving circuit of claim 6, wherein the noise-free unit is provided with a capacitor, a first transistor and a second transistor, and the first end of the capacitor is coupled to the second clock signal. a first end of the first transistor is coupled to the second control unit, and a first end of the second transistor is coupled to a second end of the first transistor and a second end of the capacitor The third control signal is output, and the first transistor and the third end of the second transistor are coupled to the reference level. The driving circuit of the sixth aspect of the invention, wherein the first driving module further comprises: a feedback output unit coupled to the noise-free unit, the first control unit and the reference level The feedback control signal outputs the first output signal. The driving circuit of claim 8, wherein the feedback output unit is provided with a third transistor and a fourth transistor, and the third transistor is coupled to the first end of the fourth transistor. a third control signal, the third transistor and the second end of the fourth transistor are coupled to the first control unit, and the third end of the third transistor is coupled to the reference level, the fourth transistor One of the third ends outputs the first output signal. The driving circuit of the first aspect of the invention, wherein the first driving module further comprises: a clearing unit, wherein a first end is coupled to the second output signal, and the second end of the clearing unit is coupled The first control list The third end of the clearing unit is coupled to a reference level.