KR20080058570A - Gate driving circuit and liquid crystal display including the same - Google Patents

Abstract

A gate driving circuit and an LCD(Liquid Crystal Display) device including the same are provided to reduce the size of a gate driver by implementing a reset transistor at an output stage of a dummy shift register. A gate driving circuit includes plural shift registers(SR1-SRn), a dummy shift register(SRn+1), and a signal supply line. The shift registers include a reset terminal for inputting a reset signal and a reset connection line, which is formed between the reset terminal and a pull-up unit for controlling outputs of gate signals, and sequentially output the gate signals. The dummy shift register having a reset unit for outputting the reset signal outputs the reset signal to the shift register. The signal supply line supplies signals to the shift register and the dummy shift register.

Description

Gate driving circuit and liquid crystal display including the same {GATE DRIVING CIRCUIT AND LIQUID CRYSTAL DISPLAY INCLUDING THE SAME}

1 is a plan view illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a block diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram illustrating a gate driving circuit of the liquid crystal display shown in FIGS. 1 and 2.

FIG. 4 is a circuit diagram illustrating the interior of the gate driving circuit shown in FIG. 3.

<Brief Description of Drawings>

10: liquid crystal panel 20: gate driving circuit

21: pull-up part 22: pull-down part

23: drive unit 24: holding unit

25: switching unit 27: ripple prevention unit

28: reset section 29: reset connection line

30: signal supply line 40: data PCB

50: data TCP 60: data drive circuit

70: level shifter 100: power supply

200: timing controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate drive circuit and a liquid crystal display device including the same, and more particularly, to a gate drive circuit having a high yield and reduced size by preventing defects in the gate drive circuit during a manufacturing process, and a liquid crystal display device including the same. will be.

In general, a liquid crystal display device includes a liquid crystal panel for displaying an image, a backlight assembly for supplying light to the liquid crystal panel, and a panel driver for driving the liquid crystal panel.

The liquid crystal panel includes a thin film transistor substrate on which a thin film transistor array is formed and a color filter substrate on which a color filter array is formed with a liquid crystal interposed therebetween facing the thin film transistor substrate.

The backlight assembly supplies light to the liquid crystal panel through a light source such as a light emitting diode or a lamp.

The panel driver includes a gate driver circuit for driving a gate line of the liquid crystal panel, a data driver circuit for driving a data line, a timing controller for supplying control signals and data signals, and a power supply unit for supplying a power signal.

The gate driving circuit is formed integrally with the thin film transistor substrate in the form of an amorphous silicon gate (ASG). The gate driving circuit is formed of a plurality of shift registers connected in a cascade manner, and each shift register selectively outputs a gate on voltage and a gate off voltage to one gate line. The data driving circuit is mounted on a data TCP (Tape Carrier Package) hereinafter referred to as a "PCB" connected to the liquid crystal panel and the data printed circuit board (hereinafter referred to as "PCB") to transfer the data voltage to the data line. Supply.

Here, a reset transistor is formed in the remaining shift registers except for the last shift register of the gate driving circuit. That is, when the gate signal is supplied from the last shift register, the gate signal is supplied to the remaining shift registers as a reset signal to reset all the shift registers.

However, when the reset transistors are formed in the respective shift registers, there is a problem in that the yield of the thin film transistor substrate is increased and the yield decreases.

In order to solve the above technical problem, the present invention is to provide a gate driving circuit and a liquid crystal display including the same, the yield is improved by preventing the defective gate driving circuit is improved.

In order to solve the above technical problem, the present invention includes a reset connection line is formed between the reset terminal to which the reset signal is input and the pull-up unit for controlling the output of the reset terminal and the gate signal, are connected to each other sequentially A plurality of shift registers outputting the gate signals to the plurality of shift registers; A dummy shift register configured to provide a reset unit configured to output the reset signal, and supply a reset signal to the plurality of shift registers; And a signal supply line unit configured to supply signals to the plurality of shift registers and the dummy shift register.

The reset unit may include: a gate reset transistor configured to supply the reset signal to the plurality of shift registers; And a magnetic reset transistor for resetting the dummy shift register.

The signal supply line unit may include first and second clock lines for supplying first and second clocks supplied from the outside; A ground voltage line for supplying a ground voltage; And a start signal line for supplying a start pulse to the first shift register and the dummy shift register, and a reset signal supply line connecting the output of the gate reset transistor and the reset terminals.

The plurality of shift registers may include an input terminal for receiving a carry signal from a previous shift register, first and second clock input terminals to which the first and second clocks are input, and a gate signal from a next shift register. A control terminal receiving an input, an output terminal for outputting the first clock as the gate signal, and a carry terminal for outputting the first clock as a carry signal, and the dummy shift register includes the input terminal, the first and second terminals. And a clock input terminal and the output terminal, and a control terminal to which the start pulse is input.

The plurality of shift registers may include a pull-up unit configured to output the first clock as the gate signal; A pull-down part configured to discharge the gate signal to the ground voltage in response to the carry signal of the next shift register; A holding unit which maintains the gate signal in the ground voltage state; A switching unit turning off the holding unit in response to the first clock and turning on the holding unit in response to the second clock; And a driving unit to turn on the pull-up unit in response to the carry signal of the previous stage shift register and to turn off the pull-up unit in response to the gate signal of the next stage shift register.

In this case, the dummy shift register may include the pull-up part, the holding part, the latching part, and the driving part; And a pull-down part which discharges the gate signal to the ground voltage in response to the start pulse, and when the first clock is output as the gate signal from the pull-up part, turns on the gate reset transistor to generate the reset signal. The dummy shift register is reset by supplying the plurality of shift registers and driving the magnetic reset transistor.

In order to solve the above technical problem, the present invention provides a liquid crystal panel for displaying an image; A gate driving circuit driving a gate line of the liquid crystal panel; And a data driving circuit driving a data line of the liquid crystal panel, wherein the gate driving circuit includes a reset terminal to which a reset signal is input, and a reset connection line formed between the reset terminal and the pull-up unit, and is connected to each other independently. A plurality of shift registers for sequentially outputting a gate signal, a reset unit for outputting the reset signal are formed, a dummy shift register for supplying a reset signal to the plurality of shift registers, and a signal for the plurality of shift registers and the dummy shift register. It provides a liquid crystal display device comprising a signal supply line portion for supplying.

The reset unit may include: a gate reset transistor configured to supply the reset signal to the plurality of shift registers; And a magnetic reset transistor for resetting the dummy shift register.

And a level shifter configured to generate and supply the first and second clocks, a ground voltage, and a start pulse to the gate driving circuit.

In this case, the signal supply line unit may include first and second clock lines for supplying first and second clocks supplied from the outside; A ground voltage line for supplying a ground voltage; And a start signal line for supplying a start pulse to the first shift register and the dummy shift register, and a reset signal supply line connecting the output of the gate reset transistor and the reset terminals.

The dummy shift register may further include a pull-up part configured to output the first clock as the gate signal, a pull-down part configured to discharge the gate signal to the ground voltage in response to the start pulse, and maintain the gate signal in the ground voltage state. A holding unit to turn off the holding unit in response to the first clock, a switching unit to turn on the holding unit in response to the second clock, and a turn-on unit in response to the carry signal of the previous shift register. And a driving unit to turn off the pull-up unit in response to the gate signal of the next shift register, and turn on the gate reset transistor when the first clock is output as the gate signal from the pull-up unit. The reset signal is supplied to the plurality of shift registers, and To the set driving transistor is characterized in that for resetting the dummy shift register.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view illustrating a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 2 is a block diagram illustrating the liquid crystal display shown in FIG. 1, and FIG. 3 is a liquid crystal display shown in FIGS. 1 and 2. A block diagram showing a gate drive circuit of the device.

1 to 3, a liquid crystal panel 10 for displaying an image, a gate driving circuit 20 for supplying a gate on / off voltage to a gate line GL of the liquid crystal panel 10, and a liquid crystal panel 10. The control signal is supplied to each of the data driving circuit 60, the gate driving circuit 20, and the data driving circuit 60, which supplies a data voltage to the data line DL of the data line DL, and the pixel data is supplied to the data driving circuit 60. And a timing controller 200 for supplying a signal.

Specifically, the liquid crystal panel 10 includes a thin film transistor substrate on which a thin film transistor array is formed, and a color filter substrate facing the liquid crystal with a color filter array formed therebetween.

The display area of the thin film transistor substrate includes a pixel thin film transistor TFT and a pixel thin film transistor formed at each intersection of the gate line GL and the data line DL, the gate line GL, and the data line DL formed to cross each other. And a pixel electrode connected to the TFT).

The gate line GL supplies a gate signal supplied from the gate driving circuit 20 to the pixel thin film transistor TFT to turn the pixel thin film transistor TFT on or off.

The data line DL is formed to cross the gate line GL, and supplies the data voltage supplied from the data driving circuit 60 to the pixel thin film transistor TFT.

The pixel thin film transistor TFT is formed on a gate electrode connected to the gate line GL, a gate electrode, and a semiconductor layer overlapping the gate electrode to be formed on the gate insulating layer to form a channel, an ohmic contact layer formed on the semiconductor layer, and an ohmic contact layer. A source electrode connected to the data line DL and a drain electrode formed to face the source electrode, wherein the drain electrode is electrically connected to the pixel electrode. The pixel thin film transistor TFT is turned on when the gate-on voltage is supplied from the gate line GL to supply the data voltage supplied from the data line to the pixel electrode.

In this case, a storage electrode overlapping the pixel electrode may be further included to charge the data voltage supplied to the pixel electrode for one frame. The storage electrode is formed in parallel with the gate line GL to supply a storage voltage to form a pixel electrode and a storage capacitor.

The color filter substrate includes a black matrix formed in correspondence with the gate line GL, the data line DL, the pixel thin film transistor TFT, and the storage electrode, a color filter formed in the pixel region, and a common electrode forming a vertical electric field with the pixel electrode. It includes.

The black matrix prevents light leakage from the gate line GL, the data line DL, the pixel thin film transistor TFT, and the storage electrode.

In the color filter, red, green, and blue color resins are formed in the pixel region to display the color of light transmitted through the liquid crystal.

The common electrode supplied with the common voltage is formed to face the pixel electrode with the liquid crystal interposed therebetween to form a liquid crystal capacitor.

Here, the liquid crystal panel 10 includes a display area for displaying an image and a non-display area adjacent to the display area. In this case, the gate driving circuit 20 and the data driving circuit 60 are preferably formed in the non-display area.

The timing controller 200 generates a gate control signal G_CS and a data control signal D_CS through a synchronization signal input from the outside and supplies the generated gate control signal G_CS and the data control signal D_CS to the gate driving circuit 20 and the data driving circuit 60. The timing controller 200 supplies the pixel data signal input from the outside to the data driving circuit 60. The gate control signal G_CS includes signals such as a gate start signal STV, a gate shift clock CPV, an output control signal OE, and the like. The data control signal D_CS includes signals such as a data start pulse D_STV, a data shift clock D_CPV, and a polarity control signal POL. In this case, the gate control signal G_CS is supplied to the level shifter 70.

The power supply unit 100 generates power signals such as a gate-on voltage VON, a gate-off voltage VOFF, an analog driving voltage AVDD, and the gate-on voltage VON and the gate-off voltage VOFF are level shifters. 70, and the analog driving voltage AVDD is supplied to the data driving circuit 60.

The data driving circuit 60 converts the digital data signal into an analog data signal in response to the data control signal D_CS from the timing controller 200 and sequentially gates the gate-on voltage to the gate line GL of the liquid crystal panel 10. Each time VON is supplied, a data voltage converted into an analog signal is sequentially supplied to the data line DL. The data driving circuit 60 includes a shift register, a latch unit, a digital-analog converter, an output buffer unit, and a gamma voltage supply unit. The shift register generates a sampling signal while sequentially shifting the data start pulse from the timing controller 200 in accordance with the data shift clock. The latch unit sequentially latches R, G, and B data signals input from the timing controller 200 in response to the sampling signal, and simultaneously outputs data of one horizontal line to the digital-analog converter. The digital-analog converter selects a gamma voltage corresponding to the data from the latch unit among the gamma voltages supplied from the gamma voltage supply unit and outputs it as an analog data voltage, and the output buffer unit buffers the data signal from the digital-analog converter. Supply to the line DL. In this case, the gamma voltage supply unit may further include a high gray gamma voltage supply unit generating a high gray voltage and a low gray gamma voltage supply unit generating a low gray voltage. For example, the pixel data of an arbitrary frame outputs a high gradation voltage generated by the high gradation gamma voltage supply unit, and then the low gradation voltage generated by the low gradation gamma voltage supply unit is supplied to the digital-analog converter in the next frame. That is, the gamma voltage supply unit selects the high gray gamma voltage or the low gray gamma voltage according to the polarity control signal POL and repeatedly supplies the gamma voltages of the high gray level and the low gray level in units of frames.

As shown in FIG. 1, the data driving circuit 60 is mounted on the data TCP 50 and connected to the data PCB 40. The data PCB 40 includes a timing controller 200 and a power supply unit 100. The image signal, the control signal, and the power signal generated by the timing controller 200 and the power supply unit 100 mounted on the data PCB 40 are supplied to the data driving circuit 60 mounted on the data TCP 50, and the data Supply to the liquid crystal panel 10 via the signal line formed in the TCP (50).

The level shifter 70 generates a first clock CKV, a second clock CKVB, and a start pulse STVP and supplies it to the gate driving circuit 20. For this purpose, the level shifter 70 may include a gate shift clock CPV and an output control signal OE supplied from the timing controller 200, a gate on voltage VON and a gate off voltage VOFF supplied from the power supply unit 100. ) Generates a first clock CKV and a second clock CKVB. In this case, the level shifter 70 is formed of a logic circuit that performs an OR operation to generate the first clock CKV. The level shifter 70 generates an clock by ORing the gate shift clock CPV and the output control signal OE supplied from the timing controller 200 through an OR operation. The level shifter 70 outputs the first clock CKV in synchronization with the clock generated by the OR operation, the gate-on voltage VON and the gate-off voltage VOFF supplied from the power supply unit 100. In addition, the level shifter 70 further includes a logic circuit for inverting the first clock CKV to output the second clock CKVB having the inverted form of the first clock CKV. The first clock CKV and the second clock CKVB thus output are supplied to the gate driving circuit 20. In addition, the gate start pulse STV supplied from the timing controller 200 is converted into a start pulse STVP and supplied to the gate driving circuit 20. The level shifter 70 is mounted on the data PCB 40 as shown in FIG. 1 and is supplied to the gate driving circuit 20 through any one of the data TCP 50.

The gate driving circuit 20 is applied to the first clock CKV supplied from the level shifter 70, the second clock CKVB and the start pulse STVP, and the gate off voltage VOFF supplied from the power supply unit 100. As a result, gate signals for driving the gate lines GL are sequentially supplied. To this end, the gate driving circuit 20 includes a plurality of shift registers SR1 to SRn and a dummy shift register SRn + 1 connected in series. Then, the signal from the level shifter 70 is transmitted to the input terminal IN of the shift register SR, and reset signals are supplied to the plurality of shift registers SR1 to SRn from the dummy shift register SRn + 1. It includes a signal supply line unit 30 to. The gate driving circuit 20 is formed in the same process when the pixel thin film transistor TFT is formed on the thin film transistor substrate.

The shift registers SR1 to SRn + 1 included in the gate driving circuit 20 selectively output the first clock CKV and the second clock CKVB, which are input from the level shifter 70, to the gate line GL. Supply a gate signal. The dummy shift register SRn + 1 supplies a reset signal to the first to nth shift registers SR1 to SRn.

For example, each of the plurality of shift registers SR1 to SRn includes an input terminal IN, a control terminal CT, a ground voltage terminal VSS, an output terminal OUT, a reset terminal RE, and a carry terminal CR, a first clock terminal CK1, and a second clock terminal CK2. The dummy shift register SRn + 1 includes an input terminal IN, a control terminal CT, a ground voltage terminal VSS, an output terminal OUT, and first and second clock terminals CK1 and CK2. do.

The input signal IN is applied with a carry signal output from the carry terminal CR of the previous shift register, and the control terminal CT is applied with a gate signal output from the output terminal OUT of the next shift register. Here, the start pulse STVP is input to the input terminal IN of the first shift register SR1. The ground voltage terminal VSS is supplied with the ground voltage VSS or the gate-off voltage VOFF. The control signal CT is supplied with the gate signal of the next shift register. At this time, the start pulse STVP is supplied to the control terminal CT of the dummy shift register SRn + 1.

The carry signal output from the carry terminal CR drives the next shift register. The first clock CKV is input to the first clock terminal CK1, and the second clock CKVB is input to the second clock terminal CK2. The reset terminal RE receives a reset signal supplied from the reset transistor TR6 of the dummy shift register SRn + 1 to reset the first to nth shift registers SR1 to SRn.

The signal supply line unit 30 is formed adjacent to the shift registers SR1 to SRn + 1 and includes a first clock line 31, a second clock line 32, a ground voltage line 33, and a reset line ( 35) a start signal line 34;

The start signal line 34 supplies the start pulse STVP supplied from the level shifter 70 to the first shifter register SR1 and the dummy shift register SRn + 1. The first clock line 31 and the second clock line 32 supply the first clock CKV and the second clock CKVB to the shift registers SR1 to SRn + 1. The ground voltage line 33 receives the ground voltage VSS or the gate-off voltage VOFF from the power supply unit 100 and supplies the ground voltage VSS to the shift registers SR1 to SRn. The reset line 35 supplies the reset signal output from the dummy shift register SRn + 1 to the first to nth shift registers SR1 to SRn.

4 is an internal circuit diagram of the gate driving circuit 20 shown in FIG. 3.

Referring to FIG. 4, the shift register SR includes a pull-up part 21, a pull-down part 22, a driver 23, a holding part 24, a switching part 25, a carry part 26, and a ripple prevention part. And (27).

The pull-up unit 21 pulls up the gate signal output from the output terminal OUT to the first clock CKV provided through the first clock terminal CK1. The pull-down unit 22 pulls down the gate signal pulled up in response to the carry signal from the second shift register SR2 to the ground voltage Voff provided through the ground voltage terminal VSS. The pull-up unit 21 is a first transistor TR1 having a gate electrode connected to the first node N1, a drain electrode connected to the first clock terminal CK1, and a source electrode connected to the output terminal OUT. Is done.

The pull-down part 22 includes a second transistor TR2 having a gate electrode connected to the control terminal CT, a drain electrode connected to the output terminal OUT, and a source electrode connected to the ground voltage terminal VSS.

The driving unit 23 turns on the pull-up unit 21 in response to the start pulse STVP provided through the input terminal IN, and drives the pull-up unit 21 in response to a carry signal of the second shift register SR2. Turn off. Here, the driving unit 23 includes a buffer unit, a charging unit and a discharge unit. The buffer part includes a fourth transistor TR4 having a gate and a drain electrode commonly connected to the input terminal IN, and a source electrode connected to the first node N1. The charging unit includes a first electrode C1 connected to the first node N1 and a second electrode connected to the second node N2. The discharge part includes a ninth transistor TR9 having a gate electrode connected to the control terminal CT, a drain electrode connected to the first node N1, and a source electrode connected to the ground voltage terminal VSS. When the fourth transistor TR4 is turned on in response to the start pulse STVP, the start pulse STVP is charged in the first capacitor C1. When the first capacitor C1 is charged with a charge equal to or greater than the threshold voltage of the first transistor TR1, the first transistor TR1 is turned on to output the first clock CKV provided to the first clock terminal CK1. Output as (OUT). Subsequently, when the ninth transistor TR9 is turned on in response to the carry signal of the second shift register SR2 input through the control terminal CT, the charge charged in the first capacitor C1 is ground voltage terminal VSS. Discharged to ground voltage (Voff) provided by

The holding part 24 includes third and fifth transistors TR3 and TR5 to hold the gate signal to the ground voltage Voff state. The gate electrode of the third transistor TR3 is connected to the third node N3, the drain electrode is connected to the second node N2, and the source electrode is connected to the ground voltage terminal VSS. The gate electrode of the fifth transistor TR5 is connected to the second clock terminal CK2, the drain electrode is connected to the second node N2, and the source electrode is connected to the ground voltage terminal VSS.

The switching unit 25 includes seventh, eighth, twelfth, and thirteenth transistors TR7, TR8, TR12, and TR13, and second and third capacitors C2 and C3 to drive the holding unit 24. To control. The gate electrode and the drain electrode of the twelfth transistor TR12 are connected to the first clock terminal CK1, and the source electrode is connected to the third node N3. The drain electrode of the seventh transistor TR7 is connected to the first clock terminal CK1, the gate electrode is connected to the drain electrode through the second capacitor C2, and the source electrode is connected to the third node N3. It is connected to the gate electrode through the third capacitor C3. The drain electrode of the thirteenth transistor TR13 is connected to the source electrode of the twelfth transistor TR12, the gate electrode is connected to the second node N2, and the source electrode is connected to the ground voltage terminal VSS. The drain electrode of the eighth transistor TR8 is connected to the third node N3, the gate electrode is connected to the second node N2, and the source electrode is connected to the ground voltage terminal VSS. At this time, when the first clock CKV in the high state is output as the gate signal to the output terminal OUT, the potential of the second node N2 is increased to the high state. When the potential of the second node N2 rises to a high state, the eighth and thirteenth transistors TR8 and TR13 are turned on. At this time, even when the seventh and twelfth transistors TR7 and TR12 are turned on by the first clock CKV provided to the first clock terminal CK1, the seventh and twelfth transistors TR7 and TR12 are turned off. The output signal is discharged to the ground voltage Voff through the eighth and thirteenth transistors TR8 and TR13. Therefore, while the gate signal of the high state is output, the potential of the third node N3 is kept low, so the third transistor TR3 maintains the turn-off state.

Thereafter, when the gate signal is discharged through the ground voltage terminal VSS in response to the carry signal of the second shift register SR2 input through the control terminal CT, the potential of the second node N2 is set to a low state. Gradually falls. Accordingly, the eighth and 113th transistors TR8 and TR13 are turned off, and the potential of the third node N3 is set to a high state by signals output from the seventh and twelfth transistors TR7 and TR12. Is raised. As the potential of the third node N3 is increased, the third transistor TR3 is turned on, and the potential of the second node N2 is discharged to the ground voltage Voff through the third transistor TR3. In this state, when the fifth transistor TR5 is turned on by the second clock CKVB provided to the second clock terminal CK2, the potential of the second node N2 turns off the ground voltage terminal VSS. Discharge more reliably.

As a result, the third and fifth transistors TR3 and TR5 of the holding part 24 hold the potential of the second node N2 in the ground voltage Voff state.

The switching unit 25 determines a time point at which the third transistor TR3 is turned on.

The carry part 26 is a fourteenth transistor TR14 having a drain electrode connected to the first clock terminal CK1, a gate electrode connected to the first node N1, and a source electrode connected to the carry terminal CR. Is done. The fourteenth transistor TR14 is turned on as the potential of the first node N1 is increased to output the first clock CKV input to the drain electrode to the carry terminal CR.

The ripple prevention unit 27 is composed of the tenth and eleventh transistors TR11. The drain electrode of the eleventh transistor TR11 is connected to the input terminal IN, the gate electrode is connected to the second clock terminal, and the source electrode is connected to the first node N1. The drain electrode of the tenth transistor TR10 is connected to the first node N1, the gate electrode is connected to the second clock terminal CK2, and the source electrode is connected to the second node N2. Accordingly, the ripple prevention unit 27 prevents the ripple due to noise inputted through the input terminal IN of the gate signal maintained at the ground voltage VSS state.

Here, the first to nth shift registers SR1 to SRn have a reset connection line 29 for supplying a reset signal between the reset terminal and the first node N1. The reset connection line 29 resets the first node N1 to the ground voltage VSS state when a reset signal is supplied from the dummy shift register SRn + 1.

The reset unit 28 is formed only in the dummy shift register SRn + 1 to supply a reset signal. The reset unit includes a gate reset transistor for resetting the first to nth shift registers and a magnetic reset transistor for resetting the dummy shift registers. The gate electrode of the gate reset transistor TR6 is connected to the output terminal OUT, the drain electrode is connected to the ground voltage terminal VSS, and the source electrode is connected to the reset line 35. That is, after the gate signals are sequentially output from the first to nth shift registers SR1 to SRn, the first to nth shift registers SR1 to SRn by the output signals of the n + 1 th shift register SRn + 1. The input terminal IN of the shift register is reset to the state of the ground voltage VSS by supplying to the first node N1. Therefore, the circuit unit 351 may start operation again in a state where all the shift registers SR1 to SRn are initialized.

The gate electrode of the self reset transistor TR15 is connected to the output terminal OUT, the drain electrode is connected to the ground voltage terminal VSS, and the source electrode is connected to the first node N1. Accordingly, the first clock CKV charged in the first node N1 is supplied to the ground voltage terminal VSS to reset the dummy shift register Sq + 1.

 Accordingly, the gate driving circuit 20 is formed by removing the reset transistors formed in the first to nth shift registers SR1 to SRn and forming the reset transistor TR6 at the output terminal of the dummy shift register SRn + 1. Can reduce the size.

The gate driving circuit and the liquid crystal display including the same according to the present invention remove the reset transistor included in each shift register of the gate driving circuit, and form a reset part connected to the output terminal of the last shift register to remove the dummy shift register and the remaining shift registers. Can be reset. Accordingly, the size of the gate driving circuit can be reduced.

In addition, since the reset transistor is removed from the plurality of shift registers, the yield of the transistor may be improved by reducing the defect rate of the transistor generated in the manufacturing process of the thin film transistor substrate of the liquid crystal display.

In the detailed description of the present invention described above with reference to the preferred embodiment of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge of the present invention described in the claims It will be understood that various modifications and changes can be made in the present invention without departing from the spirit and scope of the invention.

Claims (11)

A plurality of shift registers including a reset terminal to which a reset signal is input, and a reset connection line formed between the reset terminal and a pull-up part controlling the output of the gate signal, the plurality of shift registers being connected to each other and sequentially outputting the gate signal; A dummy shift register configured to provide a reset unit configured to output the reset signal, and supply a reset signal to the plurality of shift registers; And And a signal supply line unit configured to supply signals to the plurality of shift registers and the dummy shift register. The method of claim 1, The reset unit may include a gate reset transistor configured to supply the reset signal to the plurality of shift registers; And And a magnetic reset transistor for resetting the dummy shift register. The method of claim 2, The signal supply line unit First and second clock lines supplying first and second clocks supplied from an external source; A ground voltage line for supplying a ground voltage; And A start signal line for supplying a start pulse to the first shift register and the dummy shift register; And a reset signal supply line connecting the output of the gate reset transistor and the reset terminals. The method of claim 4, wherein The plurality of shift registers may include an input terminal for receiving a carry signal from a previous shift register, first and second clock input terminals for receiving the first and second clocks, and a gate signal from a next shift register. A terminal, an output terminal for outputting the first clock as the gate signal, and a carry terminal for outputting the first clock as a carry signal, The dummy shift register includes the input terminal, the first and second clock input terminals, and the output terminal, and includes a control terminal to which the start pulse is input. The method of claim 4, wherein The plurality of shift registers may include a pull-up unit configured to output the first clock as the gate signal; A pull-down part configured to discharge the gate signal to the ground voltage in response to the carry signal of the next shift register; A holding unit which maintains the gate signal in the ground voltage state; A switching unit turning off the holding unit in response to the first clock and turning on the holding unit in response to the second clock; And And a driver configured to turn on the pull-up unit in response to the carry signal of the previous stage shift register and to turn off the pull-up unit in response to the gate signal of the next stage shift register. The method of claim 5, wherein The dummy shift register The pull-up part, the holding part, the latching part, and the driving part; And A pull-down part configured to discharge the gate signal to the ground voltage in response to the start pulse; When the first clock is output from the pull-up unit as the gate signal, the gate reset transistor is turned on to supply the reset signal to the plurality of shift registers, and the magnetic reset transistor is driven to reset the dummy shift register. Gate driving circuit, characterized in that. A liquid crystal panel for displaying an image; A gate driving circuit driving a gate line of the liquid crystal panel; A data driving circuit driving a data line of the liquid crystal panel; The gate driving circuit includes a reset terminal to which a reset signal is input, a reset connection line formed between the reset terminal and the pull-up part, and includes a plurality of shift registers that are connected to each other and sequentially output gate signals, and the reset signal. And a dummy shift register for outputting a reset signal to the plurality of shift registers and a signal supply line portion for supplying a signal to the plurality of shift registers and the dummy shift register. The method of claim 7, wherein The reset unit may include a gate reset transistor configured to supply the reset signal to the plurality of shift registers; And And a magnetic reset transistor for resetting the dummy shift register. The method of claim 8, And a level shifter configured to generate and supply the first and second clocks, a ground voltage, and a start pulse to the gate driving circuit. The method of claim 9, The signal supply line unit First and second clock lines supplying first and second clocks supplied from an external source; A ground voltage line for supplying a ground voltage; And A start signal line for supplying a start pulse to the first shift register and the dummy shift register; And a reset signal supply line connecting the output of the gate reset transistor and the reset terminals. The method of claim 10, The dummy shift register may include a pull-up unit configured to output the first clock as the gate signal, a pull-down unit configured to discharge the gate signal to the ground voltage in response to the start pulse, and to hold the gate signal at the ground voltage state. A holding unit turning off the holding unit in response to the first clock, a switching unit turning on the holding unit in response to the second clock, and turning on the pull-up unit in response to the carry signal of the previous shift register; A driving unit to turn off the pull-up unit in response to the gate signal of the next stage shift register, When the first clock is output from the pull-up unit as the gate signal, the gate reset transistor is turned on to supply the reset signal to the plurality of shift registers, and the magnetic reset transistor is driven to reset the dummy shift register. And a liquid crystal display device.

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