CN101303895A - shift register - Google Patents

Abstract

The invention discloses a shift buffer consisting of a plurality of shift buffer units connected in series. Every shift buffer unit consists of a boosting circuit, a boosting drive circuit, a pull-down circuit and a pull-down drive circuit; wherein, the boosting circuit is coupled with a first frequency signal used for providing output signals; the boosting drive circuit is used for conduction when receiving the drive signal pulse of the previous level shift buffer unit and a second frequency signal as well as for non conduction when receiving a third frequency signal; the pull-down drive circuit is coupled with an input node of the pull-down circuit and used for the conduction of the pull-down circuit when receiving the first frequency signal as well as for non conduction of the pull-down circuit when receiving the third frequency signal or the output signal of the boosting drive circuit.

Description

shift register

technical field

The invention relates to a shift register, in particular to a shift register which utilizes precharging to prolong the charging time of pixels.

Background technique

Displays with advanced functions have gradually become an important feature of today's consumer electronics products. Liquid crystal displays have gradually become widely used in various electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or notebook computer screens. monitor with high resolution color screen.

Please refer to FIG. 1 . FIG. 1 is a functional block diagram of a liquid crystal display 10 in the prior art. The liquid crystal display 10 includes a liquid crystal display panel 12 , a gate driver 14 and a source driver 16 . The liquid crystal display panel 12 includes a plurality of pixels, and each pixel includes three pixel units 20 respectively representing three primary colors of red, green, and blue (RGB). Taking a liquid crystal display panel 12 with a resolution of 1024×768 as an example, a total of 1024×768×3 pixel units 20 are required to be combined. The gate driver 14 outputs scanning signals to turn on the transistors 22 in each column sequentially, and at the same time, the source driver 16 outputs corresponding data signals to a whole column of pixel units 20 to charge them to their respective required voltages to display different grays. order. After the charging of the same row is completed, the gate driver 14 will turn off the scan signal of the row, and then the gate driver 14 will output the scan signal to turn on the transistor 22 of the next row, and then the pixel unit 20 of the next row will be turned on by the source driver 16. Perform charge and discharge. Continue in this order until all the pixel units 20 of the liquid crystal display panel 12 are fully charged, and then start charging from the first row.

In current liquid crystal display panel design, the gate driver 14 is equivalent to a shift register (shift register), and its purpose is to output scan signals to the liquid crystal display panel 12 at regular intervals. Taking a liquid crystal display panel 12 with a resolution of 1024×768 and an update frequency of 60 Hz as an example, the display time of each picture is about 1/60=16.67 ms. So the pulse wave of each scanning signal is about 16.67ms/768=21.7μs. The source driver 16 charges and discharges the pixel unit 20 to the required voltage during the 21.7 μs to display the corresponding gray scale.

However, for the gate driver 14 used in the high-resolution liquid crystal display panel manufactured by the amorphous silicon thin film process technology, it is often because the transistor 22 of the pixel unit 20 is turned on for a short time, resulting in insufficient charging time of the liquid crystal capacitor, or The abnormal behavior of the liquid crystal display panel 12 is caused by the stress of the internal transistors of the gate driver 14 . As shown in FIG. 2 , FIG. 2 is a signal timing diagram of a shift register in the prior art. As shown in FIG. 2 , the output scan signal OUT-N of the shift register disclosed in US Patent Publication No. 7,310,402 cannot reach the high voltage logic level quickly. Since the transistor corresponding to the pixel must be at a high voltage logic level to effectively turn on and conduct, the effective charging time of the shift register in the prior art is very short, which may cause the transistor to be turned off before the pixel reaches the desired voltage. . As a result, display quality will suffer.

The shift register disclosed in US Pat. No. 5,222,082 includes a plurality of shift register units, and each shift register unit is used to delay an input signal to output an output signal according to a frequency signal. The next-stage shift register unit takes the output signal of the upper-stage shift register unit as an input signal, and then delays the output to become its own output signal. However, the gate voltage of the transistor of the shift register unit will remain at a high voltage for a long time after the delayed output, and will not return to a low voltage level until the next scan cycle, so that the threshold voltage of the transistor will be A shift occurs. In addition, when the transistor is in the positive bias, the longer the bias time of the forward bias, the greater the impact on the threshold voltage shift of the transistor, which will affect the effective operation of the transistor and affect the service life of the transistor. Finally, it may even lead to a shortened service life of the shift register.

In order to improve the operation of the transistor due to the gate voltage of the above-mentioned transistor being at a high voltage level (that is, forward bias voltage) for a long time, generally speaking, an attempt is made to keep the gate voltage of the transistor at a high voltage for a period of time After the state of the voltage level, it returns to the low voltage level. The shift register of US Patent No. 5,517,542 utilizes the output signal OUT _{n+2 of the shift register unit of stage N+2} to control the signal of the shift register unit of stage N. The shift register of US Patent Publication No. 6,845,140 utilizes the output signal of the N+1th stage shift register unit to control the signal of the Nth stage shift register unit. The shift register unit of the shift register of these two architectures utilizes the output signal of the shift register unit of the next stage (or the next two stages) so that the gate voltage of the transistor is converted from a high voltage level to a low voltage level. In this way, the gate voltage of the transistor will not remain at a high voltage level for a long time, so the purpose of reducing the bias effect can be achieved. However, these two architectures transmit the control signal to the current shift register unit by using the output signal of the shift register unit of the next stage (or the next two stages), so signal interference is unavoidable.

Contents of the invention

Therefore, an object of the present invention is to provide a pre-charged shift register, which can not only prolong the charging time of pixels, but also prolong the display life of the shift register, so as to solve the above-mentioned problems in the prior art.

According to the above object of the present invention, the present invention provides a shift register comprising a plurality of shift register units connected in series. Each shift register unit is used for driving according to a first frequency signal, a second frequency signal, a third frequency signal, a fourth frequency signal and a shift register unit before each shift register unit The signal pulse outputs the output signal of each shift register unit, and each shift register unit includes a boost circuit, a boost drive circuit, a pull-down circuit and a pull-down drive circuit. The boost circuit is coupled to the first frequency signal for providing the output signal. The boost driving circuit is used for conducting when receiving the driving signal pulse of the shift register unit of the previous stage and the second frequency signal, and is used for not conducting when receiving the third frequency signal. The pull-down circuit is used to provide a power supply voltage. The pull-down drive circuit is coupled to an input node of the pull-down circuit, and is used to turn on the pull-down circuit when receiving the first frequency signal, and is used to not turn on the pull-down circuit when receiving the third frequency signal or the output signal of the boost drive circuit. Turn on the pull-down circuit.

Another object of the present invention is to provide a shift register unit comprising a boost circuit, a boost drive circuit, a pull-down circuit, and a pull-down drive circuit. The boost circuit is coupled to the first frequency signal for providing the output signal. The boost driving circuit is used for conducting when receiving the driving signal pulse of the shift register unit of the previous stage and the second frequency signal, and is used for not conducting when receiving the third frequency signal. The pull-down circuit is used to provide a power supply voltage. The pull-down drive circuit is coupled to an input node of the pull-down circuit, and is used to turn on the pull-down circuit when receiving the first frequency signal, and is used to not turn on the pull-down circuit when receiving the third frequency signal or the output signal of the boost drive circuit. Turn on the pull-down circuit.

Description of drawings

FIG. 1 is a functional block diagram of a prior art liquid crystal display;

FIG. 2 is a signal timing diagram of a prior art shift register;

Fig. 3 is the circuit diagram of the shift buffer unit of the shift register of the present invention;

FIG. 4 is a timing diagram of signals and nodes of the shift register unit in FIG. 3 .

[Description of main component symbols]

10 liquid crystal display 12 liquid crystal display panel

14 gate drivers 16 source drivers

20 pixel unit 22 transistors

100[n] shift buffer unit T1-T11 transistors

102 boost circuit 104 boost drive circuit

106 pull-down circuit 108 pull-down drive circuit

CKO first frequency signal CKE second frequency signal

XCKO third frequency signal XCKE fourth frequency signal

P, Q node OUT(n) output terminal

ST(n), ST(n-1) drive signal terminal

Detailed ways

Please refer to FIG. 3 . FIG. 3 is a circuit diagram of the shift register unit 100 in the shift register of the present invention. The shift register of this embodiment is applicable to liquid crystal displays. The shift register includes a plurality of cascade-connected shift register units 100[n]. The shift register unit 100[n] is used for a first clock signal CKO, a second clock signal CKE, a third clock signal XCKO, a fourth clock signal XCKE and each shift register unit 100[n] A driving signal pulse of one shift register unit 100[n−1] outputs a scan signal of each shift register unit 100[n]. After the first-stage shift register unit 100[1] receives a trigger start pulse Vst from the input terminal ST(0), the shift register unit 100[1] will output an output every one standard frequency (clock cycle). Signal pulse ST(1), next, each shift buffer unit 100[n] is based on the first frequency signal CKO, the second frequency signal CKE, the third frequency signal XCKO, the fourth frequency signal XCKE and each shift The drive signal pulse output by a shift register unit 100[n-1] before the buffer unit 100[n] at the drive signal terminal ST(n-1) is transmitted at every other standard frequency in each shift register unit The output terminal OUT(n) of 100[n] outputs an output signal, which is the scan signal pulse, and is used to turn on the corresponding pixel transistor. The phase difference between the first frequency signal CKO and the second frequency signal CKE is 180 degrees, the phase difference between the third frequency signal XCKO and the fourth frequency signal XCKE is 180 degrees, and the phase difference between the first frequency signal CKO and the third frequency signal XCKO is 90 degrees , the phase difference between the second frequency signal CKE and the fourth frequency signal XCKE is 90 degrees.

Each shift register unit 100[n] includes a pull-up circuit 102, a pull-up driving circuit 104, a pull-down circuit 106, and a pull-up driving circuit (pull-down driving circuit) 108. The boost circuit 102 is coupled to the first clock signal CKO for providing an output signal at the output terminal OUT(N). The boost drive circuit 104 is used to turn on when receiving the driving signal pulse of the shift buffer unit 100[n-1] of the previous stage and the second frequency signal (CKE), and is used to receive the third frequency signal (XCKO) Not conducting. The pull-down circuit 106 is used to provide a power voltage Vss. The pull-down driving circuit 108 is used to turn on the pull-down circuit 106 when receiving the first frequency signal CKO, and is used to turn off the pull-down circuit 106 when receiving the third frequency signal XCKO or the output signal of the boost driving circuit 104 .

The boost circuit 102 includes a first transistor T1 and a second transistor T2. The drain of the first transistor T1 is coupled to the first frequency signal CKO, the gate of the first transistor T1 is coupled to the input node Q of the boost circuit 102 , and the source of the first transistor T1 is coupled to an output node OUTN. The drain of the second transistor T2 is coupled to the first frequency signal CKO, the gate of the second transistor T2 is coupled to the input node Q of the boost circuit 102, and the source of the second transistor T2 is coupled to a driving signal terminal ST ( N).

The boost driving circuit 104 includes a third transistor T3, a capacitor C1, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. The drain and gate of the third transistor T3 are coupled to the drive signal terminal ST(N-1) of the shift register unit 100[n-1] of the previous stage, and the source of the third transistor T3 is coupled to the boosting circuit 102 input node Q. One end of the capacitor C1 is coupled to the input node Q of the boost circuit 102 , and the other end is coupled to the second clock signal CKE. The drain of the fourth transistor T4 is coupled to the input node Q of the boost circuit 102 , the gate of the fourth transistor T4 is coupled to the third frequency signal XCKO, and the source of the fourth transistor T4 is coupled to the power supply voltage VSS. The drain of the fifth transistor T5 is coupled to the driving signal terminal ST(N), the gate of the fifth transistor T5 is connected to the third frequency signal XCKO and the source is connected to the power supply voltage VSS. The drain of the sixth transistor T6 is coupled to the output node OUT(N), the gate of the sixth transistor T6 is connected to the third frequency signal (XCKO), and the source of the sixth transistor T6 is connected to the power supply voltage VSS.

The pull-down circuit 106 includes a seventh transistor T7 and an eighth transistor T8. The drain of the seventh transistor T7 is coupled to the input node Q of the boost circuit 102 , the gate of the seventh transistor T7 is coupled to the input node P of the pull-down circuit 106 , and the source of the seventh transistor T7 is coupled to the power supply voltage VSS. The drain of the eighth transistor T8 is coupled to the driving signal terminal ST(N), the gate of the eighth transistor T8 is coupled to the input node P of the pull-down circuit 106 , and the source of the eighth transistor T8 is coupled to the power supply voltage VSS.

The pull-down driving circuit 108 includes a ninth transistor T9 , a tenth transistor T10 and an eleventh transistor T11 . The drain and the gate of the ninth transistor T9 are coupled to the first clock signal CKO, and the source of the ninth transistor T9 is coupled to the input node P of the pull-down circuit 106 . The drain of the tenth transistor T10 is connected to the input node P of the pull-down circuit 106 , the gate of the tenth transistor T10 is coupled to the third frequency signal XCKO, and the source of the tenth transistor T10 is coupled to the power supply voltage VSS. The drain of the eleventh transistor T11 is coupled to the input node P of the pull-down circuit 106, the gate of the eleventh transistor T11 is coupled to the input node Q of the boost circuit 102, and the source of the eleventh transistor T11 is coupled to the power supply voltage VSS.

Please refer to FIG. 3 and FIG. 4 at the same time. FIG. 4 is a timing diagram of each signal and node in FIG. 3 . During the period t0-t1, the first clock signal CKO and the fourth clock signal XCKE are at a high voltage logic level, and the second clock signal CKE and the third clock signal XCKO are at a low voltage logic level. The driving signal from the driving signal terminal ST(n−1) of the previous stage shift register unit 100[n−1] is also at a high voltage logic level, so that the transistor T3 is turned on. At this time, the potential of the node Q starts to be pulled high, causing the transistors T1 and T2 to be turned on to conduct the first frequency signal CKO, so that the potential of the output terminal OUT(n) also starts to rise toward the high voltage logic level. At this time, because the third frequency signal XCKO is at a low-voltage logic level, the transistors T4, T5, and T6 are not conducting, while the first frequency signal CKO and the fourth frequency signal XCKE are at a high-voltage logic level, so the transistors T9, T10 is turned on, so that the potential of the input node P of the pull-down circuit 106 is raised to a high voltage logic level, so the transistors T7 and T8 of the pull-down circuit 106 are both turned on. Therefore, the potential of the driving signal terminal ST(n) still maintains a low voltage logic level. At this time, the capacitor C1 stores the potential difference between the node Q and the second clock signal CKE.

During the period t1-t2, the first clock signal CKO and the second clock signal CKE are at a high voltage logic level, and the third clock signal XCKO and the fourth clock signal XCKE are at a low voltage logic level. Because the driving signal from the driving signal terminal ST(n−1) of the previous stage shift register unit 100[n−1] is also at a low voltage logic level, the transistor T3 is not turned on. But because the second frequency signal CKE is at a high-voltage logic level, the potential of the node Q floats and rises with the potential difference stored in the capacitor C1, so the potential of the node Q is still at a high-voltage logic level so that the transistors T1 and T2 are turned on The first frequency signal CKO is turned on, so that the output terminal OUT(n) continues to maintain a high voltage logic level. At the same time, the transistors T7 and T8 of the pull-down circuit 106 are not turned on, so the potential of the driving signal terminal ST(n) will be at a high voltage logic level due to the first frequency signal CKO, and output to the shift buffer of the next stage Unit 100[n+1].

During the period t2-t3, the second clock signal CKE and the third clock signal XCKO are at a high voltage logic level, and the first clock signal CKO and the fourth clock signal XCKE are at a low voltage logic level. At this time, neither the boost circuit 102 nor the pull-down circuit 106 is turned on, but the transistors T4, T5, and T6 are turned on, so the potential of the output terminal OUT(n) will be pulled down to a low voltage logic level, and the drive signal terminal ST The potential of (n) is maintained as a low voltage logic level.

The shift register of this embodiment can be applied to a gate driver of a liquid crystal display.

Compared with the prior art, in the shift register of the present invention, in each stage of shift register unit, when the start signal enters the shift register unit of this stage, the shift register unit of this stage starts to generate the output scanning signal, thus At this time, the transistor corresponding to the pixel will be slightly turned on in advance, so that the data signal of the upper stage starts to be input, so as to achieve the effect of precharging. When the timing of the data signal of the shift register unit of this stage arrives, the output scan signal has reached the full maximum voltage, so that the transistor in the pixel can be fully turned on, and the correct data signal can be quickly input. In addition, the cycle change of the frequency signal itself from the highest voltage to the lowest voltage is used to greatly reduce the falling time of the output scanning signal. In addition, the shift register of the present invention adopts a lower frequency, utilizes the frequency of half the frequency of the initial signal to drive the transistor, and utilizes a lower frequency to drive the operating life of the circuit, therefore, the shift register circuit can not only A better output waveform is produced, and a longer circuit operating life can be obtained to pass the reliability test. Since the power consumption is directly proportional to the operating frequency, the power consumption generated by the lower operating frequency is relatively lower, so it also saves more power. In addition, the start signal of each level of shift buffer unit is generated by the upper level of shift buffer unit, and does not need to be driven by the output signal of the next level of shift buffer unit, so no additional design is required Level shift buffer unit, reducing practical application problems.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make various corresponding modifications according to the present invention without departing from the spirit and essence of the present invention. Changes and deformations, but these corresponding changes and deformations should fall within the scope of protection of the appended claims of the present invention.

Claims (14)

1. an offset buffer is characterized in that, comprises:

A plurality of shift cache units, these a plurality of shift cache units connect in the mode of series connection, each shift cache unit is used for exporting according to a drive signal impulse of the previous shift cache unit of a first frequency signal, a second frequency signal, one the 3rd frequency signal, one the 4th frequency signal and this each shift cache unit the output signal of this each shift cache unit, and each shift cache unit comprises:

One promotes circuit (pull-up circuit) is coupled to this first frequency signal, is used to provide this output signal;

One promotes driving circuit (pull-up driving circuit), be coupled to this lifting circuit, be used for conducting when this drive signal impulse of the shift cache unit that receives previous stage and this second frequency signal, and be used for not conducting when receiving the 3rd frequency signal;

One pull-down circuit (pull-down circuit) is used to provide a supply voltage; And

One drop-down driving circuit (pull-down driving circuit), be coupled to input node and this pull-down circuit of this pull-down circuit, be used for this pull-down circuit of conducting when receiving this first frequency signal, and be used for when receiving the 3rd frequency signal or this lifting driving circuit output signal this pull-down circuit of not conducting.

2. offset buffer as claimed in claim 1 is characterized in that, this lifting circuit comprises:

One the first transistor, the drain electrode of this first transistor are coupled to this first frequency signal, and the grid of this first transistor is coupled to the input node of this lifting circuit, and the source electrode of this first transistor is coupled to an output node; And

One transistor seconds, the drain electrode of this transistor seconds are coupled to this first frequency signal, and the grid of this transistor seconds is coupled to the input node of this lifting circuit, and the source electrode of this transistor seconds is coupled to a drive signal end.

3. offset buffer as claimed in claim 2 is characterized in that, this lifting driving circuit comprises:

One the 3rd transistor, the 3rd transistor drain and grid are coupled to the drive signal end of the shift cache unit of previous stage, and the 3rd transistorized source electrode is coupled to the input node of this lifting circuit;

One electric capacity, one end are coupled to the input node of this lifting circuit, and the other end is coupled to this second frequency signal;

One the 4th transistor T, 4, the four transistor drain are coupled to the input node of this lifting circuit, and the 4th transistorized grid is coupled to the 3rd frequency signal, and the 4th transistorized source electrode is coupled to this supply voltage;

One the 5th transistor T, 5, the five transistor drain are coupled to this drive signal end, and the 5th transistorized grid is connected to the 3rd frequency signal and source electrode is connected to supply voltage; And

One the 6th transistor, the 6th transistor drain is coupled to this output node, and the 6th transistorized grid is connected to the 3rd frequency signal, and the 6th transistorized source electrode is connected to this supply voltage.

4. offset buffer as claimed in claim 3 is characterized in that, this pull-down circuit comprises:

One the 7th transistor, the 7th transistor drain are coupled to the input node of this lifting circuit, and the 7th transistorized grid is coupled to the input node of this pull-down circuit, and the 7th transistorized source electrode is coupled to this supply voltage;

One the 8th transistor T, 8, the eight transistor drain are coupled to this drive signal end, and the 8th transistorized grid is coupled to the input node of this pull-down circuit, and the 8th transistorized source electrode is coupled to this supply voltage.

5. offset buffer as claimed in claim 4 is characterized in that, this drop-down driving circuit comprises:

One the 9th transistor, the 9th transistor drain and grid are coupled to this first frequency signal, and the 9th transistorized source electrode is coupled to the input node of this pull-down circuit;

The tenth transistor, the tenth transistor drain are connected to the input node of this pull-down circuit, and the tenth transistorized grid is coupled to the 3rd frequency signal, and the tenth transistorized source electrode is coupled to this supply voltage;

The 11 transistor, the 11 transistor drain is coupled to the input node of this pull-down circuit, and the 11 transistorized grid is coupled to the input node of this lifting circuit, and the 11 transistorized source electrode is coupled to this supply voltage.

6. offset buffer as claimed in claim 1, it is characterized in that, this first frequency signal is spent with the phasic difference mutually 180 of this second frequency signal, the 3rd frequency signal is spent with the phasic difference mutually 180 of the 4th frequency signal, this first frequency signal is spent with the phasic difference mutually 90 of the 3rd frequency signal, and this second frequency signal is spent with the phasic difference mutually 90 of the 4th frequency signal.

7. offset buffer as claimed in claim 1 is characterized in that this bit shift register is applied to a LCD.

8. a shift cache unit is characterised in that, comprises:

One promotes circuit is coupled to this first frequency signal, is used to provide this output signal;

One promotes driving circuit is used for conducting when this drive signal impulse of the shift cache unit that receives previous stage and this second frequency signal, and is used for not conducting when receiving the 3rd frequency signal;

One pull-down circuit is used to provide a supply voltage; And

One drop-down driving circuit is coupled to one of this pull-down circuit and imports node, is used in this this pull-down circuit of first frequency signal conduction of reception, and is used for when receiving the 3rd frequency signal or this lifting driving circuit output signal this pull-down circuit of not conducting.

9. shift cache unit as claimed in claim 8 is characterized in that, this lifting circuit comprises:

One the first transistor, the drain electrode of this first transistor are coupled to this first frequency signal, and the grid of this first transistor is coupled to the input node of this lifting circuit, and the source electrode of this first transistor is coupled to an output node; And

One transistor seconds, the drain electrode of this transistor seconds are coupled to this first frequency signal, and the grid of this transistor seconds is coupled to the input node of this lifting circuit, and the source electrode of this transistor seconds is coupled to a drive signal end.

10. shift cache unit as claimed in claim 9 is characterized in that, this lifting driving circuit comprises:

One the 3rd transistor, the 3rd transistor drain and grid are coupled to the drive signal end of the displacement buffer unit of previous stage, and the 3rd transistorized source electrode is coupled to the input node of this lifting circuit;

One electric capacity, one end are coupled to the input node of this lifting circuit, and the other end is coupled to this second frequency signal;

One the 4th transistor, the 4th transistor drain are coupled to the input node of this lifting circuit, and the 4th transistorized grid is coupled to the 3rd frequency signal, and the 4th transistorized source electrode is coupled to this supply voltage;

One the 5th transistor, the 5th transistor drain are coupled to this drive signal end, and the 5th transistorized grid is connected to this second frequency signal and source electrode is connected to supply voltage; And

One the 6th transistor T, 6, the six transistor drain are coupled to this output node, and the 6th transistorized grid is connected to the 3rd frequency signal, and the 6th transistorized source electrode is connected to this supply voltage.

11. shift cache unit as claimed in claim 10 is characterized in that, this pull-down circuit comprises:

One the 7th transistor, the 7th transistor drain are coupled to the input node of this lifting circuit, and the 7th transistorized grid is coupled to the input node of this pull-down circuit, and the 7th transistorized source electrode is coupled to this supply voltage;

One the 8th transistor, the 8th transistor drain are coupled to this drive signal end, and the 8th transistorized grid is coupled to the input node of this pull-down circuit, and the 8th transistorized source electrode is coupled to this supply voltage.

12. shift cache unit as claimed in claim 11 is characterized in that, this drop-down driving circuit comprises:

One the 9th transistor, the 9th transistor drain and grid are coupled to this first frequency signal, and the 9th transistorized source electrode is coupled to the input node of this pull-down circuit;

The tenth transistor, the tenth transistor drain are connected to the input node of this pull-down circuit, and the tenth transistorized grid is coupled to the 3rd frequency signal, and the tenth transistorized source electrode is coupled to this supply voltage;

The 11 transistor, the 11 transistor drain is coupled to the input node of this pull-down circuit, and the 11 transistorized grid is coupled to the input node of this lifting circuit, and the 11 transistorized source electrode is coupled to this supply voltage.

13. shift cache unit as claimed in claim 8, it is characterized in that, this first frequency signal is spent with the phasic difference mutually 180 of this second frequency signal, the 3rd frequency signal is spent with the phasic difference mutually 180 of the 4th frequency signal, this first frequency signal is spent with the phasic difference mutually 90 of the 3rd frequency signal, and this second frequency signal is spent with the phasic difference mutually 90 of the 4th frequency signal.

14. shift cache unit as claimed in claim 8 is characterized in that, this drive signal impulse is a triggering initial pulse.

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