CN101303895A - Shift buffer - Google Patents
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- CN101303895A CN101303895A CNA2008101266577A CN200810126657A CN101303895A CN 101303895 A CN101303895 A CN 101303895A CN A2008101266577 A CNA2008101266577 A CN A2008101266577A CN 200810126657 A CN200810126657 A CN 200810126657A CN 101303895 A CN101303895 A CN 101303895A
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Abstract
The invention discloses a shift buffer consisting of a plurality of shift buffer units connected in series. Every shift buffer unit consists of a boosting circuit, a boosting drive circuit, a pull-down circuit and a pull-down drive circuit; wherein, the boosting circuit is coupled with a first frequency signal used for providing output signals; the boosting drive circuit is used for conduction when receiving the drive signal pulse of the previous level shift buffer unit and a second frequency signal as well as for non conduction when receiving a third frequency signal; the pull-down drive circuit is coupled with an input node of the pull-down circuit and used for the conduction of the pull-down circuit when receiving the first frequency signal as well as for non conduction of the pull-down circuit when receiving the third frequency signal or the output signal of the boosting drive circuit.
Description
Technical field
The present invention relates to a kind of offset buffer, refer in particular to a kind of offset buffer that utilizes precharge to prolong the duration of charging of pixel.
Background technology
Function advanced person's display gradually becomes the valuable feature of consumption electronic product now, and wherein LCD has become the display that various electronic equipments such as mobile phone, PDA(Personal Digital Assistant), digital camera, computer screen or the widespread use of mobile computer screen institute have the high-resolution color screen gradually.
See also Fig. 1, Fig. 1 is the functional block diagram of the LCD 10 of prior art.LCD 10 comprises a display panels 12, a gate drivers (gate driver) 14 and source electrode driver (source driver) 16.Display panels 12 comprises a plurality of pixels (pixel), and each pixel comprises three and represents the trichromatic pixel cell of RGB (RGB) 20 to constitute respectively.With the display panels 12 of one 1024 * 768 resolution, need 1024 * 768 * 3 pixel cells 20 to combine altogether.Gate drivers 14 output scanning signals make the transistor 22 of each row open in regular turn, and the pixel cell 20 of data-signal to a permutation that 16 outputs of source electrode driver simultaneously are corresponding makes it be charged to required separately voltage, to show different GTGs.After the charging of same row finished, the sweep signal that gate drivers 14 just will be listed as was closed, then gate drivers 14 again the output scanning signal transistor 22 of next column is opened, the pixel cell 20 by 16 pairs of next columns of source electrode driver discharges and recharges again.So go down in regular turn, all charge up to all pixel cells 20 of display panels 12 and finish, again since the first row charging.
In the design of present display panels, gate drivers 14 equivalences are gone up and are offset buffers (shiftregister), its purpose promptly every a fixed intervals output scanning signal to display panels 12.With the display panels 12 of one 1024 * 768 resolution and the renewal frequency of 60Hz is example, and the demonstration time of each picture is about 1/60=16.67ms.So the pulse wave of each sweep signal is about 16.67ms/768=21.7 μ s.Source electrode driver 16 then in the time of this 21.7 μ s, discharges and recharges required voltage with pixel cell 20, to demonstrate corresponding GTG.
Yet; for the gate drivers 14 of the high-resolution liquid crystal display panel that is used in the manufacturing of amorphous silicon membrane technology; usually can be too short because of transistor 22 ON time of pixel cell 20; cause liquid crystal capacitance duration of charging deficiency, or bias voltage (stress) problem of gate drivers 14 internal transistors and cause the performance of display panels 12 to take place unusual.As shown in Figure 2, Fig. 2 is the signal timing diagram of the offset buffer of prior art.As shown in Figure 2, United States Patent (USP) announces the 7th, 310, and the output scanning signal OUT-N of the offset buffer of No. 402 exposure can't arrive high voltage logic position standard apace.Because the transistor of respective pixel must could effectively be opened conducting in high voltage logic position standard,, might cause also no show of pixel to want voltage preceding with regard to just not conducting of transistor so the effective duration of charging of the offset buffer of prior art is very of short duration.Thus, display quality can be affected.
United States Patent (USP) announces the 5th, 222, and No. 082 described offset buffer comprises a plurality of shift cache units, and each shift cache unit is to be used for according to frequency signal, input signal is postponed output and is output signal.The shift cache unit of next stage then with the output signal of the shift cache unit of upper level as input signal, postponing output again becomes the output signal of self.Yet, the transistorized grid voltage of shift cache unit can still maintain high voltage for a long time after postponing output, up to just can return back to the accurate position of low-voltage before the scan cycle next time, thus, can cause transistorized critical voltage to be offset (shift).In addition, when transistor was in positive bias, the bias voltage time of positive bias was long more also big more to transistor critical voltage degrees of offset influence, and this can influence transistorized effective running, related influence transistorized serviceable life.Last even can cause shorten the serviceable life of offset buffer.
Influence transistorized running in order to improve above-mentioned transistorized grid voltage because of the state that is in the accurate position of high voltage (that is positive bias) for a long time, in general, after can attempting to allow transistorized grid voltage only keep the state of the accurate position of high voltage of a period of time, just return back to the accurate position of low-voltage.United States Patent (USP) announces the 5th, 517, and No. 542 offset buffer utilizes the output signal OUT of the shift cache unit of N+2 level
N+2Remove to control the signal of the shift cache unit of N level.United States Patent (USP) announces the 6th, 845, and No. 140 offset buffer utilizes the output signal of the shift cache unit of N+1 level to remove to control the signal of the shift cache unit of N level.The shift cache unit of the offset buffer of these two kinds of frameworks is to utilize the output signal of shift cache unit of next stage (or down two-stage) so that transistorized grid voltage is converted to the accurate position of low-voltage by the accurate position of high voltage, thus the grid voltage of electric crystal not president's time dimension be held in the accurate position of high voltage, so can reach the purpose of reduction bias effect.But these two kinds of frameworks are to utilize the output signal transfer control signal of the shift cache unit of next stage (or following two-stage) to arrive current shift cache unit, so the interference of signal is also unavoidable.
Summary of the invention
Therefore, one of the present invention purpose is to provide a kind of precharge offset buffer, not only can prolong the duration of charging of pixel, also can elongate the performance life-span of offset buffer simultaneously, to solve the problem of above-mentioned prior art.
According to above-mentioned purpose of the present invention, the invention provides a kind of offset buffer, it comprises a plurality of shift cache units that connect with series system.Each shift cache unit is to be used for exporting according to a drive signal impulse of the previous shift cache unit of a first frequency signal, a second frequency signal, one the 3rd frequency signal, one the 4th frequency signal and this each shift cache unit the output signal of this each shift cache unit, and each shift cache unit comprises one and promotes circuit, and promote driving circuit, a pull-down circuit and a drop-down driving circuit.This lifting circuit is coupled to this first frequency signal, is used to provide this output signal.This lifting driving circuit is used for conducting when this drive signal impulse of the shift cache unit that receives previous stage and this second frequency signal, and is used for not conducting when receiving the 3rd frequency signal.This pull-down circuit is used to provide a supply voltage.This drop-down driving circuit is coupled to an input node of this pull-down circuit, is used in this this pull-down circuit of first frequency signal conduction of reception, and is used for when receiving the 3rd frequency signal or this lifting driving circuit output signal this pull-down circuit of not conducting.
Another object of the present invention is that providing a kind of shift cache unit to comprise one promotes circuit, lifting driving circuit, a pull-down circuit and a drop-down driving circuit.This lifting circuit is coupled to this first frequency signal, is used to provide this output signal.This lifting driving circuit is used for conducting when this drive signal impulse of the shift cache unit that receives previous stage and this second frequency signal, and is used for not conducting when receiving the 3rd frequency signal.This pull-down circuit is used to provide a supply voltage.This drop-down driving circuit is coupled to an input node of this pull-down circuit, is used in this this pull-down circuit of first frequency signal conduction of reception, and is used for when receiving the 3rd frequency signal or this lifting driving circuit output signal this pull-down circuit of not conducting.
Description of drawings
Fig. 1 is the functional block diagram of prior art LCD;
Fig. 2 is the signal timing diagram of prior art offset buffer;
Fig. 3 is the circuit diagram of the shift cache unit of offset buffer of the present invention;
Fig. 4 is each signal of shift cache unit among Fig. 3 and the sequential chart of node.
[primary clustering symbol description]
10 LCD, 12 display panels
14 gate drivers, 16 source electrode drivers
20 pixel cells, 22 transistors
100[n] shift cache unit T1-T11 transistor
102 promote circuit 104 promotes driving circuit
106 pull-down circuits, 108 drop-down driving circuits
CKO first frequency signal CKE second frequency signal
XCKO the 3rd frequency signal XCKE the 4th frequency signal
P, Q node OUT (n) output terminal
ST (n), ST (n-1) drive signal end
Embodiment
See also Fig. 3, Fig. 3 is the circuit diagram of shift cache unit 100 in the offset buffer of the present invention.The offset buffer of present embodiment is applicable to LCD.Offset buffer comprises the shift cache unit 100[n of a plurality of serial connections (cascade-connected)].Shift cache unit 100[n] be used for according to a first frequency signal CKO, a second frequency signal CKE, one the 3rd frequency signal XCKO, one the 4th frequency signal XCKE and each shift cache unit 100[n] previous shift cache unit 100[n-1] a drive signal impulse export each shift cache unit 100[n] sweep signal.As first order shift cache unit 100[1] after input end ST (0) receives a triggering initial pulse Vst, shift cache unit 100[1] will produce output signal pulses ST (1) every a standard frequency (clock cycle) output, next, each shift cache unit 100[n] be according to first frequency signal CKO, second frequency signal CKE, the 3rd frequency signal XCKO, the 4th frequency signal XCKE and each shift cache unit 100[n] previous shift cache unit 100[n-1] in the drive signal impulse of drive signal end ST (n-1) output, with every the mode of a standard frequency at this each shift cache unit 100[n] output terminal OUT (n) output one output signal, this output signal promptly scans signal pulse, is used for opening corresponding pixel transistor.First frequency signal CKO spends with the phasic difference mutually 180 of second frequency signal CKE, the 3rd frequency signal XCKO spends with the phasic difference mutually 180 of the 4th frequency signal XCKE, first frequency signal CKO spends with the phasic difference mutually 90 of the 3rd frequency signal XCKO, and second frequency signal CKE spends with the phasic difference mutually 90 of the 4th frequency signal XCKE.
Each shift cache unit 100[n] comprise one and promote circuit (pull-up circuit) 102, and promote driving circuit (pull-up driving circuit) 104, one pull-down circuit (pull-down circuit) 106 and one drop-down driving circuit (pull-down driving circuit) 108.Promote circuit 102 and be coupled to first frequency signal CKO, be used for providing output signal at output terminal OUT (N).Promoting driving circuit 104 is used at the shift cache unit 100[n-1 that receives previous stage] drive signal impulse and conducting during second frequency signal (CKE), be used for not conducting when receiving the 3rd frequency signal (XCKO).Pull-down circuit 106 is used to provide a supply voltage Vss.Drop-down driving circuit 108 is used for conducting pull-down circuit 106 when receiving first frequency signal CKO, and is used for when receiving the 3rd frequency signal XCKO or promoting driving circuit 104 output signals not conducting pull-down circuit 106.
Pull-down circuit 106 comprises one the 7th transistor T 7 and one the 8th transistor T 8.The drain electrode of the 7th transistor T 7 is coupled to the input node Q that promotes circuit 102, and the grid of the 7th transistor T 7 is coupled to the input node P of pull-down circuit 106, and the source electrode of the 7th transistor T 7 is coupled to supply voltage VSS.The drain electrode of the 8th transistor T 8 is coupled to drive signal end ST (N), and the grid of the 8th transistor T 8 is coupled to the input node P of pull-down circuit 106, and the source electrode of the 8th transistor T 8 is coupled to supply voltage VSS.
Drop-down driving circuit 108 comprises one the 9th transistor T 9,1 the tenth transistor T 10 and 1 the 11 transistor T 11.The drain electrode of the 9th transistor T 9 and grid are coupled to first frequency signal CKO, and the source electrode of the 9th transistor T 9 is coupled to the input node P of pull-down circuit 106.The drain electrode of the tenth transistor T 10 is connected to the input node P of pull-down circuit 106, and the grid of the tenth transistor T 10 is coupled to the 3rd frequency signal XCKO, and the source electrode of the tenth transistor T 10 is coupled to supply voltage VSS.The drain electrode of the 11 transistor T 11 is coupled to the input node P of pull-down circuit 106, and the grid of the 11 transistor T 11 is coupled to the input node Q that promotes circuit 102, and the source electrode of the 11 transistor T 11 is coupled to supply voltage VSS.
Please also refer to Fig. 3 and Fig. 4, Fig. 4 is the sequential chart of each signal and node among Fig. 3.During period t0-t1, first frequency signal CKO and the 4th frequency signal XCKE are in the accurate position of high voltage logic, and second frequency signal CKE and the 3rd frequency signal XCKO are in the accurate position of low logic voltage.From previous stage shift cache unit 100[n-1] the drive signal of drive signal end ST (n-1) also be in the accurate position of high voltage logic, make transistor T 3 can open (turn on) conductings.This moment, the current potential of node Q began to be drawn high, and caused transistor T 1, the T2 conducting first frequency signal CKO that also is unlocked, and made the current potential of output terminal OUT (n) also begin to rise towards the accurate position of high voltage logic.This moment is because the 3rd frequency signal XCKO is in the accurate position of low logic voltage, so transistor T 4, T5, T6 are not conductings, and first frequency signal CKO and the 4th frequency signal XCKE are in the accurate position of high voltage logic, so transistor T 9, T10 conducting, make the current potential of input node P of pull-down circuit 106 be promoted to the accurate position of high voltage logic, so the transistor T 7 of pull-down circuit 106, all conductings of T8.So the current potential of drive signal end ST (n) still keeps the accurate position of low logic voltage.At this moment, the potential difference (PD) between capacitor C 1 meeting storage node Q and the second frequency signal CKE.
During period t1-t2, first frequency signal CKO and second frequency signal CKE are in the accurate position of high voltage logic, and the 3rd frequency signal XCKO and the 4th frequency signal XCKE are in the accurate position of low logic voltage.Because from previous stage shift cache unit 100[n-1] the drive signal of drive signal end ST (n-1) also be in the accurate position of low logic voltage, so transistor T 3 can not conductings.But because second frequency signal CKE is in the accurate position of high voltage logic, so the current potential of node Q is float lifting along with the potential difference (PD) of capacitor C 1 storage, therefore the current potential of node Q still is in the accurate position of high voltage logic and makes and make output terminal OUT (n) continue to keep the accurate position of high voltage logic by transistor T 1, the T2 conducting first frequency signal CKO that is unlocked.Simultaneously, the transistor T 7 of pull-down circuit 106, not conducting of T8 so the current potential of drive signal end ST (n) can be in the accurate position of high voltage logic because of the event of first frequency signal CKO, and export the shift cache unit 100[n+1 of next stage to].
During period t2-t3, second frequency signal CKE and the 3rd frequency signal XCKO are in the accurate position of high voltage logic, and first frequency signal CKO and the 4th frequency signal XCKE are in the accurate position of low logic voltage.At this moment, promote circuit 102 and pull-down circuit 106 neither conductings, and transistor T 4, T5, T6 are conductings, so the current potential of output terminal OUT (n) can be pulled down to the accurate position of low logic voltage, the current potential of drive signal end ST (n) then is maintained the accurate position of low logic voltage.
The offset buffer of present embodiment can be applicable to the gate drivers of LCD.
Compared to prior art, offset buffer of the present invention is in each grade shift cache unit, when start signal enters shift cache unit at the corresponding levels, shift cache unit at the corresponding levels begins to produce the output scanning signal, this moment, the transistor of respective pixel can be opened in advance a little, make the data-signal of upper level begin input, to reach precharge effect.When the data-signal sequential of shift cache unit at the corresponding levels then, the output scanning signal has arrived ceiling voltage completely, is able to the transistor in the pixel is opened fully, and imports correct data-signal fast.Utilize frequency signal itself to change in addition, make significantly reduce the fall time of this output scanning signal by the cycle that ceiling voltage drops to minimum voltage.Offset buffer of the present invention in addition adopts lower frequency, utilize the frequency of half frequency of start signal to come driving transistors, utilize lower frequency to drive the operation lifetime that can prolong circuit, therefore, this shift cache circuit not only can produce output waveform preferably, and can be arranged to pass through reliability test the long circuit operation life-span again.Because consumed power is directly proportional with operating frequency, the power consumption that lower operating frequency produces is also relatively low, therefore also relatively power saving.The start signal of each grade shift cache unit is produced by the upper level shift cache unit in addition, and need not drive by the output signal of next stage shift cache unit, so, reduce the problem in the practical application not needing again the additional designs grade shift cache unit of drawing up.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (14)
1. an offset buffer is characterized in that, comprises:
A plurality of shift cache units, these a plurality of shift cache units connect in the mode of series connection, each shift cache unit is used for exporting according to a drive signal impulse of the previous shift cache unit of a first frequency signal, a second frequency signal, one the 3rd frequency signal, one the 4th frequency signal and this each shift cache unit the output signal of this each shift cache unit, and each shift cache unit comprises:
One promotes circuit (pull-up circuit) is coupled to this first frequency signal, is used to provide this output signal;
One promotes driving circuit (pull-up driving circuit), be coupled to this lifting circuit, be used for conducting when this drive signal impulse of the shift cache unit that receives previous stage and this second frequency signal, and be used for not conducting when receiving the 3rd frequency signal;
One pull-down circuit (pull-down circuit) is used to provide a supply voltage; And
One drop-down driving circuit (pull-down driving circuit), be coupled to input node and this pull-down circuit of this pull-down circuit, be used for this pull-down circuit of conducting when receiving this first frequency signal, and be used for when receiving the 3rd frequency signal or this lifting driving circuit output signal this pull-down circuit of not conducting.
2. offset buffer as claimed in claim 1 is characterized in that, this lifting circuit comprises:
One the first transistor, the drain electrode of this first transistor are coupled to this first frequency signal, and the grid of this first transistor is coupled to the input node of this lifting circuit, and the source electrode of this first transistor is coupled to an output node; And
One transistor seconds, the drain electrode of this transistor seconds are coupled to this first frequency signal, and the grid of this transistor seconds is coupled to the input node of this lifting circuit, and the source electrode of this transistor seconds is coupled to a drive signal end.
3. offset buffer as claimed in claim 2 is characterized in that, this lifting driving circuit comprises:
One the 3rd transistor, the 3rd transistor drain and grid are coupled to the drive signal end of the shift cache unit of previous stage, and the 3rd transistorized source electrode is coupled to the input node of this lifting circuit;
One electric capacity, one end are coupled to the input node of this lifting circuit, and the other end is coupled to this second frequency signal;
One the 4th transistor T, 4, the four transistor drain are coupled to the input node of this lifting circuit, and the 4th transistorized grid is coupled to the 3rd frequency signal, and the 4th transistorized source electrode is coupled to this supply voltage;
One the 5th transistor T, 5, the five transistor drain are coupled to this drive signal end, and the 5th transistorized grid is connected to the 3rd frequency signal and source electrode is connected to supply voltage; And
One the 6th transistor, the 6th transistor drain is coupled to this output node, and the 6th transistorized grid is connected to the 3rd frequency signal, and the 6th transistorized source electrode is connected to this supply voltage.
4. offset buffer as claimed in claim 3 is characterized in that, this pull-down circuit comprises:
One the 7th transistor, the 7th transistor drain are coupled to the input node of this lifting circuit, and the 7th transistorized grid is coupled to the input node of this pull-down circuit, and the 7th transistorized source electrode is coupled to this supply voltage;
One the 8th transistor T, 8, the eight transistor drain are coupled to this drive signal end, and the 8th transistorized grid is coupled to the input node of this pull-down circuit, and the 8th transistorized source electrode is coupled to this supply voltage.
5. offset buffer as claimed in claim 4 is characterized in that, this drop-down driving circuit comprises:
One the 9th transistor, the 9th transistor drain and grid are coupled to this first frequency signal, and the 9th transistorized source electrode is coupled to the input node of this pull-down circuit;
The tenth transistor, the tenth transistor drain are connected to the input node of this pull-down circuit, and the tenth transistorized grid is coupled to the 3rd frequency signal, and the tenth transistorized source electrode is coupled to this supply voltage;
The 11 transistor, the 11 transistor drain is coupled to the input node of this pull-down circuit, and the 11 transistorized grid is coupled to the input node of this lifting circuit, and the 11 transistorized source electrode is coupled to this supply voltage.
6. offset buffer as claimed in claim 1, it is characterized in that, this first frequency signal is spent with the phasic difference mutually 180 of this second frequency signal, the 3rd frequency signal is spent with the phasic difference mutually 180 of the 4th frequency signal, this first frequency signal is spent with the phasic difference mutually 90 of the 3rd frequency signal, and this second frequency signal is spent with the phasic difference mutually 90 of the 4th frequency signal.
7. offset buffer as claimed in claim 1 is characterized in that this bit shift register is applied to a LCD.
8. a shift cache unit is characterised in that, comprises:
One promotes circuit is coupled to this first frequency signal, is used to provide this output signal;
One promotes driving circuit is used for conducting when this drive signal impulse of the shift cache unit that receives previous stage and this second frequency signal, and is used for not conducting when receiving the 3rd frequency signal;
One pull-down circuit is used to provide a supply voltage; And
One drop-down driving circuit is coupled to one of this pull-down circuit and imports node, is used in this this pull-down circuit of first frequency signal conduction of reception, and is used for when receiving the 3rd frequency signal or this lifting driving circuit output signal this pull-down circuit of not conducting.
9. shift cache unit as claimed in claim 8 is characterized in that, this lifting circuit comprises:
One the first transistor, the drain electrode of this first transistor are coupled to this first frequency signal, and the grid of this first transistor is coupled to the input node of this lifting circuit, and the source electrode of this first transistor is coupled to an output node; And
One transistor seconds, the drain electrode of this transistor seconds are coupled to this first frequency signal, and the grid of this transistor seconds is coupled to the input node of this lifting circuit, and the source electrode of this transistor seconds is coupled to a drive signal end.
10. shift cache unit as claimed in claim 9 is characterized in that, this lifting driving circuit comprises:
One the 3rd transistor, the 3rd transistor drain and grid are coupled to the drive signal end of the displacement buffer unit of previous stage, and the 3rd transistorized source electrode is coupled to the input node of this lifting circuit;
One electric capacity, one end are coupled to the input node of this lifting circuit, and the other end is coupled to this second frequency signal;
One the 4th transistor, the 4th transistor drain are coupled to the input node of this lifting circuit, and the 4th transistorized grid is coupled to the 3rd frequency signal, and the 4th transistorized source electrode is coupled to this supply voltage;
One the 5th transistor, the 5th transistor drain are coupled to this drive signal end, and the 5th transistorized grid is connected to this second frequency signal and source electrode is connected to supply voltage; And
One the 6th transistor T, 6, the six transistor drain are coupled to this output node, and the 6th transistorized grid is connected to the 3rd frequency signal, and the 6th transistorized source electrode is connected to this supply voltage.
11. shift cache unit as claimed in claim 10 is characterized in that, this pull-down circuit comprises:
One the 7th transistor, the 7th transistor drain are coupled to the input node of this lifting circuit, and the 7th transistorized grid is coupled to the input node of this pull-down circuit, and the 7th transistorized source electrode is coupled to this supply voltage;
One the 8th transistor, the 8th transistor drain are coupled to this drive signal end, and the 8th transistorized grid is coupled to the input node of this pull-down circuit, and the 8th transistorized source electrode is coupled to this supply voltage.
12. shift cache unit as claimed in claim 11 is characterized in that, this drop-down driving circuit comprises:
One the 9th transistor, the 9th transistor drain and grid are coupled to this first frequency signal, and the 9th transistorized source electrode is coupled to the input node of this pull-down circuit;
The tenth transistor, the tenth transistor drain are connected to the input node of this pull-down circuit, and the tenth transistorized grid is coupled to the 3rd frequency signal, and the tenth transistorized source electrode is coupled to this supply voltage;
The 11 transistor, the 11 transistor drain is coupled to the input node of this pull-down circuit, and the 11 transistorized grid is coupled to the input node of this lifting circuit, and the 11 transistorized source electrode is coupled to this supply voltage.
13. shift cache unit as claimed in claim 8, it is characterized in that, this first frequency signal is spent with the phasic difference mutually 180 of this second frequency signal, the 3rd frequency signal is spent with the phasic difference mutually 180 of the 4th frequency signal, this first frequency signal is spent with the phasic difference mutually 90 of the 3rd frequency signal, and this second frequency signal is spent with the phasic difference mutually 90 of the 4th frequency signal.
14. shift cache unit as claimed in claim 8 is characterized in that, this drive signal impulse is a triggering initial pulse.
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| CN2008101266577A CN101303895B (en) | 2008-06-17 | 2008-06-17 | Shift buffer |
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| CN2008101266577A CN101303895B (en) | 2008-06-17 | 2008-06-17 | Shift buffer |
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| CN101976581A (en) * | 2010-01-18 | 2011-02-16 | 友达光电股份有限公司 | Shift register circuit |
| US7953201B2 (en) | 2008-12-12 | 2011-05-31 | Au Optronics Corp. | Shift register with pre-pull-down module to suppress a spike |
| US20110234577A1 (en) * | 2010-03-24 | 2011-09-29 | Au Optronics Corporation | Shift register with low power consumption |
| CN103035297A (en) * | 2012-10-12 | 2013-04-10 | 友达光电股份有限公司 | Shift register |
| CN104252853A (en) * | 2014-09-04 | 2014-12-31 | 京东方科技集团股份有限公司 | Shift register unit, driving method, gate drive circuit and display device |
| CN106157893A (en) * | 2016-09-09 | 2016-11-23 | 京东方科技集团股份有限公司 | Shift register cell and driving method, drive circuit and display device |
| WO2020192476A1 (en) * | 2019-03-26 | 2020-10-01 | 京东方科技集团股份有限公司 | Multi-path selection circuit and driving method, and multi-path selection unit and display apparatus |
| CN111785205A (en) * | 2020-08-03 | 2020-10-16 | 四川遂宁市利普芯微电子有限公司 | Pre-charging circuit of common cathode LED display screen driving chip |
| CN115083348A (en) * | 2022-07-22 | 2022-09-20 | 合肥京东方显示技术有限公司 | GOA unit, driving method thereof and GOA circuit |
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| TWI298478B (en) * | 2002-06-15 | 2008-07-01 | Samsung Electronics Co Ltd | Method of driving a shift register, a shift register, a liquid crystal display device having the shift register |
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| US7953201B2 (en) | 2008-12-12 | 2011-05-31 | Au Optronics Corp. | Shift register with pre-pull-down module to suppress a spike |
| CN101976581B (en) * | 2010-01-18 | 2013-04-10 | 友达光电股份有限公司 | Shift register circuit |
| CN101976581A (en) * | 2010-01-18 | 2011-02-16 | 友达光电股份有限公司 | Shift register circuit |
| US20110234577A1 (en) * | 2010-03-24 | 2011-09-29 | Au Optronics Corporation | Shift register with low power consumption |
| US8537094B2 (en) * | 2010-03-24 | 2013-09-17 | Au Optronics Corporation | Shift register with low power consumption and liquid crystal display having the same |
| CN103035297B (en) * | 2012-10-12 | 2015-04-29 | 友达光电股份有限公司 | Shift register |
| CN103035297A (en) * | 2012-10-12 | 2013-04-10 | 友达光电股份有限公司 | Shift register |
| CN104252853A (en) * | 2014-09-04 | 2014-12-31 | 京东方科技集团股份有限公司 | Shift register unit, driving method, gate drive circuit and display device |
| CN106157893A (en) * | 2016-09-09 | 2016-11-23 | 京东方科技集团股份有限公司 | Shift register cell and driving method, drive circuit and display device |
| WO2020192476A1 (en) * | 2019-03-26 | 2020-10-01 | 京东方科技集团股份有限公司 | Multi-path selection circuit and driving method, and multi-path selection unit and display apparatus |
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| CN111785205B (en) * | 2020-08-03 | 2023-08-25 | 四川遂宁市利普芯微电子有限公司 | Pre-charging circuit of common-cathode LED display screen driving chip |
| WO2023019866A1 (en) * | 2021-08-16 | 2023-02-23 | 惠科股份有限公司 | Driving circuit of display panel and driving device |
| US11978377B2 (en) | 2021-08-16 | 2024-05-07 | HKC Corporation Limited | Driving circuit and driving device for display panel |
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