CN101364446B - Shift buffer - Google Patents
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- CN101364446B CN101364446B CN2008101612565A CN200810161256A CN101364446B CN 101364446 B CN101364446 B CN 101364446B CN 2008101612565 A CN2008101612565 A CN 2008101612565A CN 200810161256 A CN200810161256 A CN 200810161256A CN 101364446 B CN101364446 B CN 101364446B
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Abstract
The invention discloses a shift register, which comprises a plurality of serially connected shift register units. Each shift register unit comprises a lifting circuit for providing an output signal, a lifting driving circuit and a pull-down circuit. The lifting driving circuit comprises a control circuit and a first transistor. The grid electrode of the control circuit is coupled with an input node of the lifting circuit of an earlier stage shift register, and the drain electrode of the control circuit is coupled with a second frequency signal. The grid electrode of the first transistor is coupled with the source electrode of the control circuit, the drain electrode of the first transistor is coupled with the driving signal end of the earlier stage shift register, and the source electrode of the first transistor is coupled with the input node. The pull-down circuit is used for providing the voltage at the input node of the lifting circuit to a power supply voltage. The shift register can improve the characteristic shift resistance of the transistor.
Description
Technical field
The present invention relates to a kind of offset buffer, refer in particular to a kind of offset buffer that can increase transistor characteristic drift resistivity.
Background technology
Function advanced person's display gradually becomes the valuable feature of consumption electronic product now, and wherein LCD has become the display that various electronic equipments such as mobile phone, PDA(Personal Digital Assistant), digital camera, computer screen or the widespread use of mobile computer screen institute have the high-resolution color screen gradually.
See also Fig. 1, Fig. 1 is the functional block diagram of the LCD 10 of prior art.LCD 10 comprises a display panels 12, a gate drivers (gate driver) 14 and source electrode driver (source driver) 16.Display panels 12 comprises a plurality of pixels (pixel), and each pixel comprises three and represents the trichromatic pixel cell of RGB (RGB) 20 to constitute respectively.With the display panels 12 of one 1024 * 768 resolution, need 1024 * 768 * 3 pixel cells 20 to combine altogether.Gate drivers 14 output scanning signals make the transistor 22 of each row open in regular turn, and the pixel cell 20 of data-signal to a permutation that 16 outputs of source electrode driver simultaneously are corresponding makes it be charged to required separately voltage, to show different GTGs.After the charging of same row finished, the sweep signal that gate drivers 14 just will be listed as was closed, then gate drivers 14 again the output scanning signal transistor 22 of next column is opened, the pixel cell 20 by 16 pairs of next columns of source electrode driver discharges and recharges again.So go down in regular turn, all charge up to all pixel cells 20 of display panels 12 and finish, again since the first row charging.
In the design of present display panels, gate drivers 14 equivalences are offset buffer (shiftregister), its purpose promptly every a fixed intervals output scanning signal to display panels 12.With the display panels 12 of one 1024 * 768 resolution and the renewal frequency of 60Hz is example, and the demonstration time of each picture is about 1/60=16.67ms.So the pulse of each sweep signal is about 16.67ms/768=21.7 μ s.Source electrode driver 16 then in the time of this 21.7 μ s, discharges and recharges required voltage with pixel cell 20, to demonstrate corresponding GTG.
Yet, for the gate drivers 14 that adopts the amorphous silicon membrane technology, after lighting display panels 12, usually can cause the performance of display panels 12 to take place unusual because of bias voltage (stress) problem.See also Fig. 2, Fig. 2 announces the 5th, 410 for United States Patent (USP), the circuit diagram of No. 583 described offset buffers.Offset buffer shown in Figure 2 comprises a plurality of shift cache units, and shift cache unit is used for according to frequency signal C1, C3, input signal INPUT is postponed to export output terminal to and be output signal OUTPUT, the shift cache unit of next stage then with the output signal OUTPUT of upper level shift cache unit as input signal INPUT, postponing output again becomes output signal OUTPUT.The output signal OUTPUT of each shift cache unit is the delay output of input signal INPUT.Yet the grid and the drain electrode of the transistor 18 of shift cache unit couple, and promptly are equivalent to diode.Thus, when transistor characteristic generation drift (shift), because the grid of transistor 18-source electrode pressure reduction Vgs is fixed as zero uncontrollable its voltage-current characteristic, may cause transistor 18 leakage currents excessive and influence the electric charge preservation of node P1, cause circuit erroneous action.This can influence transistorized effective running, and is last even can cause shorten the serviceable life of offset buffer.
Summary of the invention
A purpose of the present invention is to provide a kind of offset buffer, can increase the resistivity of transistor characteristic drift.
According to above-mentioned purpose of the present invention, the invention provides a kind of offset buffer and comprise a plurality of shift cache units, these a plurality of shift cache units connect in the mode of series connection.Each shift cache unit comprises one and promotes circuit, a lifting driving circuit and a pull-down circuit.This lifting circuit is coupled to a first frequency signal, is used to provide an output signal.This lifting driving circuit is coupled to this lifting circuit, and it comprises a control circuit and a first transistor.The grid of this control circuit be coupled to previous stage shift cache unit the lifting circuit one the input node, the drain electrode of this control circuit is coupled to a second frequency signal.The grid of this first transistor is coupled to the source electrode of this control circuit, the drain electrode of this first transistor is coupled to a drive signal end of the previous stage shift cache unit of this each shift cache unit, and the source electrode of this first transistor is coupled to an input node of this lifting circuit.This pull-down circuit is used to provide voltage to one supply voltage of the input node of this lifting circuit.
Another object of the present invention promotes circuit, a lifting driving circuit and a pull-down circuit for providing a kind of shift cache unit to comprise one.This lifting circuit is coupled to a first frequency signal, is used to provide an output signal.This lifting driving circuit is coupled to this lifting circuit, and it comprises a control circuit and a first transistor.The grid of this control circuit be coupled to previous stage shift cache unit the lifting circuit one the input node, the drain electrode of this control circuit is coupled to a second frequency signal.The grid of this first transistor is coupled to the source electrode of this control circuit, the drain electrode of this first transistor is coupled to a drive signal end of the previous stage shift cache unit of this each shift cache unit, and the source electrode of this first transistor is coupled to an input node of this lifting circuit.This pull-down circuit is used to provide voltage to one supply voltage of the input node of this lifting circuit.
According to the present invention, this lifting driving circuit comprises one the 3rd transistor in addition, the 3rd transistorized grid is coupled to this first frequency signal, the 3rd transistor drain is coupled to the source electrode of this control circuit, and the 3rd transistorized source electrode is coupled to a drive signal end of the next stage shift cache unit of this each shift cache unit.
According to the present invention, this lifting circuit comprises one the 4th transistor and one the 5th transistor, the 4th transistor drain is coupled to this first frequency signal, and the 4th transistorized grid is coupled to the input node of this lifting circuit, and the 4th transistorized source electrode is coupled to an output node.The 5th transistor drain is coupled to this first frequency signal, and the 5th transistorized grid is coupled to this input node, and the 5th transistorized source electrode is coupled to a drive signal end.
According to the present invention, this pull-down circuit comprises one the 6th transistor, and its drain electrode, grid and source electrode are respectively coupled to this drive signal end and this supply voltage of next stage shift cache unit of this input node, this each shift cache unit of this lifting circuit.
Description of drawings
Fig. 1 is the functional block diagram of the LCD of prior art;
Fig. 2 announces the 5th, 410 for United States Patent (USP), the circuit diagram of No. 583 described offset buffers;
Fig. 3 is the calcspar of the shift cache unit of offset buffer of the present invention;
Fig. 4 A is the circuit diagram of the shift cache unit of first embodiment of the present invention;
The circuit diagram of the shift cache unit 200 (n) of the offset buffer of second embodiment that Fig. 4 B is;
Fig. 5 is each signal of Fig. 4 A and the sequential chart of node;
Fig. 6 A is the circuit diagram of shift cache unit of the offset buffer of the third embodiment of the present invention;
Fig. 6 B is the circuit diagram of shift cache unit of the offset buffer of the fourth embodiment of the present invention.
Wherein, description of drawings:
10 LCD, 12 display panels
14 gate drivers, 16 source electrode drivers
20 pixel cells, 22 transistors
100 (n) shift cache unit T1-T6 transistor
102 promote circuit 104,204 promotes driving circuit
106 pull-down circuit CK first frequency signals
XCK second frequency signal P, Q node
OUT (n) output terminal 108 control circuits
200 (n) shift cache unit 300 (n) shift cache unit
400 (n) shift cache unit, 1081 first input ends
1,082 second output terminals 1083 the 3rd output terminal
ST (n), ST (n-1), ST (n+1) drive signal end
Embodiment
See also Fig. 3, Fig. 3 is the calcspar of the shift cache unit 100 (n) of offset buffer of the present invention.The offset buffer of present embodiment is applicable to LCD.Offset buffer comprises the shift cache unit 100 (n) of a plurality of serial connections (cascade-connected).Shift cache unit 100 (n) is used for exporting according to a drive signal impulse of the previous stage shift cache unit 100 (n-1) of a first frequency signal CK, a second frequency signal XCK4 and each shift cache unit 100 (n) sweep signal of each shift cache unit 100 (n).After first order shift cache unit 100 (1) receives (the start pulse) of a triggering initial pulse from input end ST (O), shift cache unit 100 (1) will produce output signal pulses ST (1) every a standard frequency (clockcycle) output, next, each shift cache unit 100 (n) is according to first frequency signal CK, the previous stage shift cache unit 100 (n-1) of second frequency signal XCK and each shift cache unit 100 (n) is in the drive signal impulse of drive signal end ST (n-1) output, to export this each shift cache unit 100 (n) every the mode of a standard frequency in output terminal OUT (n) output one output signal, this output signal promptly scans signal pulse, is used for exporting and opening the transistor of corresponding pixel.First frequency signal CK spends with the phasic difference mutually 180 of second frequency signal XCK.
Each shift cache unit 100 (n) comprises one and promotes circuit (pull-up circuit) 102, one lifting driving circuit (pull-up driving circuit) 104 and one pull-down circuit (pull-downcircuit) 106.Promote circuit 102 and be coupled to first frequency signal CK, be used for providing output signal in output terminal OUT (n).Promote driving circuit 104 and be used for conducting when the drive signal impulse of the shift cache unit 100 (n-1) that receives previous stage and second frequency signal XCK.Pull-down circuit 106 is used to provide a supply voltage Vss.
See also Fig. 4 A, Fig. 4 A is the circuit diagram of the shift cache unit of the first embodiment of the present invention.Promote driving circuit 104 and be coupled to node Q (n) with lifting circuit 102.In the present embodiment, control circuit 108 comprises transistor seconds T2.The grid of transistor seconds T2 is coupled to the input node Q (n-1) of the shift cache unit 100 (n-1) of previous stage, and the drain electrode of transistor seconds T2 is coupled to second frequency signal XCK.The grid of the first transistor T1 is coupled to the source electrode of transistor seconds T2, and the drain electrode of the first transistor T1 is coupled to the drive signal end ST (n-1) of previous stage shift cache unit 100 (n-1), and the source electrode of the first transistor T1 is coupled to node Q (n).The grid of the 3rd transistor T 3 is coupled to first frequency signal CK, and the drain electrode of the 3rd transistor T 3 is coupled to the source electrode of this transistor seconds T2, and the source electrode of the 3rd transistor T 3 is coupled to the drive signal end ST (n+1) of next stage shift cache unit 100 (n+1).
Pull-down circuit 106 comprises one the 6th transistor T 6, is used to provide to import the voltage of node Q (n) to supply voltage Vss.The drain electrode of the 6th transistor T 6, grid and source electrode are respectively coupled to the drive signal end ST (n+1) and the supply voltage V of input node Q (n), next stage shift cache unit 100 (n+1)
Ss
Please also refer to Fig. 3 and Fig. 5, Fig. 5 is each signal of Fig. 3 and the sequential chart of node.During period t0-t1, first frequency signal CK is in the accurate position of low-voltage V
L, make transistor T 3 close.Simultaneously, the drive signal of the drive signal end ST (n-1) of second frequency signal XCK and previous stage shift cache unit 100 (n-1) is in the accurate position of high voltage V
H, the signal potential V of the input node Q (n-1) of previous stage shift cache unit 100 (n-1)
2Also be in the accurate position of high voltage, make transistor T 2 open (turn on) with conducting second frequency signal XCK to node P.Because the signal potential V of node Q (n-1)
2The current potential V that can be higher than second frequency signal XCK
HSo, the current potential meeting of transistor T 1 grid (that is node P) and the current potential V of second frequency signal XCK
HApproaching.That is to say the grid of transistor T 1 and the pressure reduction V between source electrode
GSBigger, so the charging current that produces can be higher.And the drive signal of the transistor T 1 meeting conducting drive signal end ST (n-1) that is unlocked allows the current potential of node Q (n) begin to draw high gradually to voltage quasi position V because of being recharged
2
During period t1-t2, first frequency signal CK is in the accurate position of high voltage V
H, make transistor T 3 open.Simultaneously, the drive signal of the drive signal end ST (n-1) of second frequency signal XCK and previous stage shift cache unit 100 (n-1) is in the accurate position of low-voltage, the input node Q (n-1) of previous stage shift cache unit 100 (n-1) is in the accurate position of low-voltage, make transistor T 2 close and the drive signal of the drive signal end ST (n+1) of conducting next stage shift cache unit 100 (n+1) to node P.Because this moment, the current potential of node P was in the accurate position of low-voltage, so transistor T 1, T6 are closed not conducting.But the current potential of node Q (n) can be because float (floating) be, because of transistorized capacity effect along with the rising of first frequency signal CK by accurate position V
2Jump to accurate position V
1When the current potential of Q (n) jumps to accurate position V
1Afterwards, transistor T 4 and the T5 conducting first frequency signal CK that can be unlocked causes the accurate position of output terminal OUT (n) and drive signal end ST (n) output HIGH voltage.Note that at time point t1 when the drive signal of drive signal end ST (n-1) was transformed into the accurate position of low-voltage by the accurate position of high voltage, second frequency signal XCK also was transformed into the accurate position of low-voltage V simultaneously
L, the grid-source electrode pressure reduction Vgs of transistor T 1 is near 0V (this state only exists first frequency signal CK and second frequency signal XCK to be all the extremely short moment of the accurate position of low-voltage) at this moment.When the drive signal of drive signal end ST (n-1) was pulled low to Vss, the grid voltage of transistor T 1 maintained the accurate position of low-voltage V
L, and the grid voltage of transistor T 1 can that is to say that the leakage current of transistor T 1 can improve via the bulk potential adjustment via the external circuit adjustment.
After period t3, first frequency signal CK is in the accurate position of high voltage V
H, make transistor T 3 open.Simultaneously, the drive signal of the drive signal end ST (n+1) of next stage shift cache unit 100 (n+1) is in the accurate position of low-voltage, and the current potential of node P is pulled down to the accurate position of low-voltage.That is to say that another function of transistor T 3 is when shift cache unit 100 (n) when not exporting, for increasing transistor T 1 stability, so the current potential of transistor T 1 grid is left behind to reach the purpose of voltage stabilizing.
See also Fig. 4 B, Fig. 4 B is the circuit diagram of shift cache unit 300 (n) of the offset buffer of second embodiment.In first embodiment, the grid of transistor T 3 and source electrode are respectively coupled to the drive signal end ST (n+1) of first frequency signal CK and next stage shift cache unit 100 (n+1).In second embodiment shown in Fig. 4 B, the grid of transistor T 3 can be coupled to node Q, first frequency signal CK or direct supply voltage V
DDOne of them, and the source electrode of transistor T 3 can receive the drive signal end ST (n+1) of second frequency signal XCK, next stage shift cache unit 100 (n+1) or the output terminal OUT (n+1) of next stage shift cache unit 100 (n+1) one of them.
See also Fig. 6 A, the circuit diagram of the shift cache unit 300 (n) of the offset buffer of Fig. 6 A third embodiment of the present invention.The lifting driving circuit 204 of the shift cache unit 300 (n) of Fig. 6 A has lacked the 3rd transistor T 3 than the lifting driving circuit 104 of the shift cache unit 100 (n) of Fig. 4 A, and this moment, the P point voltage still can be pulled low to V via T1
L, to reach the purpose of control T2 electric leakage.In the above-described embodiments, the grid of transistor T 2 and drain electrode are respectively coupled to the node Q (n-1) and the second frequency signal XCK of previous stage shift cache unit 100 (n-1).
See also Fig. 6 B, Fig. 6 B is the circuit diagram of shift cache unit 400 (n) of the offset buffer of the fourth embodiment of the present invention.In the present embodiment, the grid of transistor T 2 can be coupled to direct supply voltage V
DDOr the node Q (n-1) of previous stage shift cache unit 100 (n-1) one of them, and the drain electrode of transistor T 2 can be coupled to the drive signal end ST (n-1) of upper level shift cache unit 100 (n-1) or second frequency signal XCK one of them.No matter take any combination, the output of shift cache unit 400 (n) still is equivalent to the shift cache unit 300 (n) of Fig. 6 A.
The offset buffer of present embodiment can be applicable to the gate drivers of LCD.Offset buffer of the present invention uses transistor T 1 and T3 in shift cache unit, the voltage that can change transistor T 1 grid via T1 and T3 can change charging/leakage current, with the resistivity of the transistor T 1 characteristic drift that increases each shift cache unit.
The above person only is a better embodiment of the present invention, and equivalent modifications or variation that all those skilled in the art do according to spirit of the present invention all are covered by in the accompanying Claim book.
Claims (26)
1. an offset buffer is characterized in that, comprises:
A plurality of shift cache units, these a plurality of shift cache units connect in the mode of series connection, and each shift cache unit comprises:
One promotes circuit is coupled to a first frequency signal, is used to provide an output signal;
One promotes driving circuit, is coupled to this lifting circuit, and it comprises:
One control circuit, this control circuit comprises a first input end, one second input end and one the 3rd output terminal, this first input end of this control circuit be coupled to previous stage shift cache unit the lifting circuit one the input node, this of this control circuit second input end is coupled to a second frequency signal; And
One the first transistor, the grid of this first transistor is coupled to the 3rd output terminal of this control circuit, the drain electrode of this first transistor is coupled to a drive signal end of the previous stage shift cache unit of this each shift cache unit, and the source electrode of this first transistor is coupled to an input node of this lifting circuit; And
One pull-down circuit is used to provide voltage to one supply voltage of the input node of this lifting circuit.
2. offset buffer as claimed in claim 1, it is characterized in that, this control circuit comprises a transistor seconds, the grid of this transistor seconds is coupled to the first input end of this control circuit, the drain electrode of this transistor seconds is coupled to second input end of this control circuit, and the source electrode of this transistor seconds is coupled to the 3rd output terminal of this control circuit.
3. offset buffer as claimed in claim 2, it is characterized in that, the grid of this transistor seconds be coupled to previous stage shift cache unit the lifting circuit one the input node, the drain electrode of this transistor seconds is coupled to a second frequency signal, and the source electrode of this transistor seconds is coupled to the grid of this first transistor.
4. offset buffer as claimed in claim 3, it is characterized in that, this lifting driving circuit comprises one the 3rd transistor in addition, the 3rd transistorized grid is coupled to this first frequency signal, the 3rd transistor drain is coupled to the source electrode of this transistor seconds, and the 3rd transistorized source electrode is coupled to a drive signal end of the next stage shift cache unit of this each shift cache unit.
5. offset buffer as claimed in claim 3 is characterized in that, this lifting circuit comprises:
One the 4th transistor, the 4th transistor drain are coupled to this first frequency signal, and the 4th transistorized grid is coupled to the input node of this lifting circuit, and the 4th transistorized source electrode is coupled to an output node; And
One the 5th transistor, the 5th transistor drain are coupled to this first frequency signal, and the 5th transistorized grid is coupled to this input node, and the 5th transistorized source electrode is coupled to a drive signal end.
6. offset buffer as claimed in claim 3 is characterized in that, this first frequency signal is spent with the phasic difference mutually 180 of this second frequency signal.
7. offset buffer as claimed in claim 3, it is characterized in that, this pull-down circuit comprises one the 6th transistor, and its drain electrode, grid and source electrode are respectively coupled to this drive signal end and this supply voltage of next stage shift cache unit of this input node, this each shift cache unit of this lifting circuit.
8. offset buffer as claimed in claim 3 is characterized in that, is applied to a LCD.
9. a shift cache unit is characterized in that, comprises:
One promotes circuit, is coupled to a first frequency signal, is used to provide an output signal;
One promotes driving circuit, is coupled to this lifting circuit, and it comprises:
One control circuit, this control circuit comprises a first input end, one second input end and one the 3rd output terminal, this first input end of this control circuit be coupled to previous stage shift cache unit the lifting circuit one the input node, this of this control circuit second input end is coupled to a second frequency signal; And
One the first transistor, the grid of this first transistor is coupled to the 3rd output terminal of this control circuit, the drain electrode of this first transistor is coupled to a drive signal end of the previous stage shift cache unit of this each shift cache unit, and the source electrode of this first transistor is coupled to an input node of this lifting circuit; And
One pull-down circuit is used to provide voltage to one supply voltage of the input node of this lifting circuit.
10. shift cache unit as claimed in claim 9, it is characterized in that, this control circuit comprises a transistor seconds, the grid of this transistor seconds is coupled to the first input end of this control circuit, the drain electrode of this transistor seconds is coupled to second input end of this control circuit, and the source electrode of this transistor seconds is coupled to the 3rd output terminal of this control circuit.
11. shift cache unit as claimed in claim 10, it is characterized in that, the grid of this transistor seconds be coupled to previous stage shift cache unit the lifting circuit one the input node, the drain electrode of this transistor seconds is coupled to a second frequency signal, and the source electrode of this transistor seconds is coupled to the grid of this first transistor.
12. shift cache unit as claimed in claim 11, it is characterized in that, this lifting driving circuit comprises one the 3rd transistor in addition, the 3rd transistorized grid is coupled to this first frequency signal, the 3rd transistor drain is coupled to the source electrode of this transistor seconds, and the 3rd transistorized source electrode is coupled to a drive signal end of the next stage shift cache unit of this each shift cache unit.
13. shift cache unit as claimed in claim 11 is characterized in that, this lifting circuit comprises:
One the 4th transistor, the 4th transistor drain are coupled to this first frequency signal, and the 4th transistorized grid is coupled to the input node of this lifting circuit, and the 4th transistorized source electrode is coupled to an output node; And
One the 5th transistor, the 5th transistor drain are coupled to this first frequency signal, and the 5th transistorized grid is coupled to this input node, and the 5th transistorized source electrode is coupled to a drive signal end.
14. shift cache unit as claimed in claim 11, it is characterized in that, this pull-down circuit comprises one the 6th transistor, and its drain electrode, grid and source electrode are respectively coupled to this drive signal end and this supply voltage of next stage shift cache unit of this input node, this each shift cache unit of this lifting circuit.
15. shift cache unit as claimed in claim 11 is characterized in that, this first frequency signal is spent with the phasic difference mutually 180 of this second frequency signal.
16. an offset buffer is characterized in that, comprises:
A plurality of shift cache units, these a plurality of shift cache units connect in the mode of series connection, and each shift cache unit comprises:
One promotes circuit, is coupled to a first frequency signal, is used to provide an output signal;
One promotes driving circuit, is coupled to this lifting circuit, and it comprises:
One control circuit, this control circuit comprise a first input end, one second input end and one the 3rd output terminal, and this first input end of this control circuit is coupled to one first signal end, and this of this control circuit second input end is coupled to a secondary signal end; And
One the first transistor, the grid of this first transistor is coupled to the 3rd output terminal of this control circuit, the drain electrode of this first transistor is coupled to a drive signal end of the previous stage shift cache unit of this each shift cache unit, and the source electrode of this first transistor is coupled to an input node of this lifting circuit; And
One pull-down circuit is used to provide voltage to one first supply voltage of the input node of this lifting circuit.
17. offset buffer as claimed in claim 16, it is characterized in that, this control circuit comprises a transistor seconds, the grid of this transistor seconds is coupled to the first input end of this control circuit, the drain electrode of this transistor seconds is coupled to second input end of this control circuit, and the source electrode of this transistor seconds is coupled to the 3rd output terminal of this control circuit.
18. offset buffer as claimed in claim 17, it is characterized in that, the grid of this transistor seconds be coupled to previous stage shift cache unit the lifting circuit one the input node, the drain electrode of this transistor seconds is coupled to a second frequency signal, and the source electrode of this transistor seconds is coupled to the grid of this first transistor.
19. offset buffer as claimed in claim 17 is characterized in that, the grid of this transistor seconds is coupled to input node or the second source voltage of lifting circuit of the shift cache unit of previous stage.
20. offset buffer as claimed in claim 19, it is characterized in that, the drain electrode of this transistor seconds is coupled to this drive signal end of the previous stage shift cache unit of this each shift cache unit, or is coupled to an output terminal of the previous stage shift cache unit of this each shift cache unit.
21. offset buffer as claimed in claim 17, it is characterized in that, this lifting driving circuit comprises one the 3rd transistor in addition, the 3rd transistorized grid is coupled to one the 3rd signal end, the 3rd transistor drain is coupled to the source electrode of this transistor seconds, and the 3rd transistorized source electrode is coupled to one the 4th signal end.
22. offset buffer as claimed in claim 21, it is characterized in that, the 3rd transistor drain is coupled to the 3rd output terminal of this control circuit, and the 3rd transistorized grid is coupled to this first frequency signal or the input node of this lifting circuit or this second source voltage.
23. offset buffer as claimed in claim 22, it is characterized in that the 3rd transistorized source electrode is coupled to a drive signal end or a second frequency signal or the output terminal of the next stage shift cache unit of this each shift cache unit of the next stage shift cache unit of this each shift cache unit.
24. offset buffer as claimed in claim 16 is characterized in that, this lifting circuit comprises:
One the 4th transistor, the 4th transistor drain are coupled to this first frequency signal, and the 4th transistorized grid is coupled to the input node of this lifting circuit, and the 4th transistorized source electrode is coupled to an output node; And
One the 5th transistor, the 5th transistor drain are coupled to this first frequency signal, and the 5th transistorized grid is coupled to this input node, and the 5th transistorized source electrode is coupled to a drive signal end.
25. offset buffer as claimed in claim 23 is characterized in that, this first frequency signal is spent with the phasic difference mutually 180 of this second frequency signal.
26. offset buffer as claimed in claim 23, it is characterized in that, this pull-down circuit comprises one the 6th transistor, and its drain electrode, grid and source electrode are respectively coupled to this drive signal end and this first supply voltage of next stage shift cache unit of this input node, this each shift cache unit of this lifting circuit.
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|---|---|---|---|
| CN2008101612565A CN101364446B (en) | 2008-09-24 | 2008-09-24 | Shift buffer |
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|---|---|---|---|
| CN2008101612565A CN101364446B (en) | 2008-09-24 | 2008-09-24 | Shift buffer |
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| CN101364446B true CN101364446B (en) | 2010-08-18 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101752006B (en) * | 2009-12-25 | 2012-12-12 | 友达光电股份有限公司 | Shift register |
| TWI433101B (en) * | 2011-04-21 | 2014-04-01 | Au Optronics Corp | Electrophoretic display apparatus and image updating method thereof |
| TWI425473B (en) * | 2011-12-29 | 2014-02-01 | Au Optronics Corp | Gate driving circuit |
| CN105810142B (en) * | 2016-05-20 | 2019-09-27 | 上海天马有机发光显示技术有限公司 | Shifting deposit unit and its driving method, shift-register circuit, display device |
| CN106782365B (en) * | 2016-12-15 | 2019-05-03 | 武汉华星光电技术有限公司 | A kind of gate driving circuit and driving method, display device |
| CN106782374A (en) * | 2016-12-27 | 2017-05-31 | 武汉华星光电技术有限公司 | GOA circuits |
| TWI637371B (en) * | 2017-12-28 | 2018-10-01 | 友達光電股份有限公司 | Shift register circuit |
| US10777149B2 (en) | 2018-05-10 | 2020-09-15 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Driving circuit |
| CN108630163A (en) * | 2018-05-10 | 2018-10-09 | 武汉华星光电半导体显示技术有限公司 | A kind of driving circuit |
| CN111627404B (en) * | 2020-06-09 | 2021-11-23 | 武汉华星光电技术有限公司 | GOA circuit, display panel and display device |
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