KR20090083565A - Display device and driving method thereof - Google Patents

Abstract

A display device and a driving method thereof are provided to reduce the number of wirings by reducing the gate control signal inputted to the gate driving circuit. A display device comprises a display panel(30), a data driving circuit(32), a gate driving circuit(33), a controller(31) and a control signal generating section. The display panel has pixels. The pixels are arranged in the cross points of the gate lines and the data lines. The data driving circuit supplies the video data signal to the data lines. The gate driving circuit successively supplies the gate pulse to the gate lines. The controller generates the first signal. The first signal controls the output of the gate driving circuit. The control signal generating section generates the second and third control signals by delaying the first signal. The second controlling signal controls the shift operation of the gate driving circuit. The third control signal starts the operation of the gate driving circuit.

Description

Display device and driving method

The present invention relates to a display device and a driving method thereof for reducing a control signal input to a scan driving circuit.

The display device is applied to various information devices and office equipment as a medium for transmitting visual information. Cathode ray tube or cathode ray tube, which is the most widely used display device, has a problem of weight and volume. Many kinds of flat panel displays have been developed to overcome the limitations of the cathode ray tube.

The flat panel display includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting diode device (OLED). ). Among these, the liquid crystal display device can satisfy the light and thin trend of electronic products and mass production is improving, so that the cathode ray tube is rapidly replaced in many applications. In particular, an active matrix type liquid crystal display device that drives a liquid crystal cell using a thin film transistor (hereinafter referred to as "TFT") has advantages of high image quality and low power consumption. With the achievement of securing and R & D, it is rapidly developing into larger size and higher resolution.

The flat panel display device is arranged such that data lines and scan lines are orthogonal and pixels are arranged in a matrix. In a liquid crystal display or an organic light emitting diode device, the scan line is sometimes referred to as a gate line because the gate electrode of the TFT is connected to the scan lines. Data lines to be displayed are supplied to the data lines, and scan pulses (or gate pulses) are sequentially supplied to the scan lines. The video data voltage is supplied to the pixels of the display line to which the scan pulse is supplied, and all the display lines are sequentially scanned by the scan pulse to display the video data.

The scan driving circuit for supplying the scan pulse to the scan lines of the flat panel display device generally includes a plurality of integrated integrated circuits (hereinafter referred to as "ICs"). Each of the scan ICs basically includes a shift register because the scan pulses must be sequentially output, and may include circuits and output buffers for adjusting the output voltage of the shift register according to the driving characteristics of the display panel. This scan driving circuit operates in response to many control signals generated from the timing controller. Hereinafter, a scan driving circuit of the flat panel display will be described based on the gate driving circuit of the liquid crystal display.

1 shows a gate IC of a gate driving circuit applied to a liquid crystal display device. 2 shows a control signal for controlling the gate driving circuit and an output signal of the scan driving circuit.

1 and 2, a gate IC of a liquid crystal display includes a shift register 10, a level shifter 12, and a plurality of AND gates connected between the shift register 10 and the level shifter 12 (hereinafter, referred to as a gate IC). , An " AND gate "

The shift register 10 sequentially shifts the gate start pulse GSP according to the gate shift clock GSC using a plurality of D-flip flops connected in a cascade manner. Each of the AND gates 11 generates an output by ANDing the non-inverted output signal of the D-flip flop of the shift register 10 and the inverted signal of the gate output enable signal (GOE). The gate output enable signal GOE is inverted by the inverter 13 and input to one input terminal of the AND gate 11. The level shifter 12 shifts the output voltage swing width of the AND gate 11 to a swing width capable of operating the TFT of the liquid crystal display panel. The output signals G1 to Gk of the level shifter 12 are sequentially supplied to k (k is an integer) gate lines.

To control the gate IC, the timing controller must generate at least a gate start pulse GSP, a gate shift clock GSC and a gate output enable signal GOE. Therefore, it is difficult to reduce the number of pins or wirings of the connector and the cable for transmitting the control signal between the timing controller and the gate IC. Such a problem is an obstacle in solving the simplification and cost reduction of the driving circuit not only in the liquid crystal display but also in other flat panel display devices.

Accordingly, an object of the present invention is to provide a display device and a method of driving the same, which reduce the control signal input to the scan driving circuit.

In order to achieve the above object, a display device according to an embodiment of the present invention includes a display panel in which data lines and gate lines intersect and pixels are arranged in a matrix; A data driver circuit for supplying a video data signal to the data lines; A gate driving circuit which sequentially supplies gate pulses to the gate lines; And a controller for generating a first control signal for controlling the output of the gate driving circuit. And a control signal generator for delaying the first control signal to generate a second control signal for controlling the shift operation of the gate driving circuit and a third control signal for starting the operation of the gate driving circuit.

A display device according to an embodiment of the present invention comprises the steps of generating a first control signal for controlling the output of the gate driving circuit; And delaying the first control signal to generate a second control signal for controlling the shift operation of the gate driving circuit and a third control signal for starting the operation of the gate driving circuit.

According to an exemplary embodiment of the present invention, a display device and a driving method thereof reduce a gate control signal input to a gate driving circuit by minimizing a gate control signal generated by a timing controller and delaying the gate control signal to generate other gate control signals. Can be. Furthermore, the present invention can minimize the number of pins and wirings of a connector, a cable for transmitting a control signal between the timing controller and the gate IC by minimizing the gate control signal generated from the timing controller.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 12.

Referring to FIG. 3, the liquid crystal display according to the first embodiment of the present invention includes a liquid crystal display panel 30, a timing controller 31, a data driving circuit 32, and a gate driving circuit 33. The data driver circuit 32 includes a plurality of source ICs. The gate driving circuit 33 includes a plurality of gate ICs 331 to 335.

In the liquid crystal display panel 30, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 30 includes m × n liquid crystal cells Clc arranged in a matrix by a cross structure of m data lines 34 and n gate lines 35.

Data lines 34, gate lines 35, TFTs, and a storage capacitor Cst are formed on the lower glass substrate of the liquid crystal display panel 30. The liquid crystal cells Clc are connected to the TFT and are driven by an electric field between the pixel electrodes 1 and the common electrode 2. The black matrix, the color filter, and the common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel 30. Meanwhile, the common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, in plane switching (IPS) mode, and fringe field switching (FFS). In the horizontal electric field driving method as in the mode, the pixel electrode 1 is formed on the lower glass substrate. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 30, a polarizing plate is attached and an alignment film for setting the pre-tilt angle of the liquid crystal is formed at an interface in contact with the liquid crystal.

The timing controller 31 receives timing signals such as the vertical / horizontal synchronization signals Vsync and Hsync, the data enable signal DE, and the clock signal CLK, and the data driver circuit 32 and the gate driver circuit 33. Control signals for controlling the operation timing of the < RTI ID = 0.0 > These control signals include a gate timing control signal and a data timing control signal. The timing controller 31 also supplies digital video data RGB and black data to the data driving circuit 32.

The gate timing control signal generated by the timing controller 31 includes only a gate output enable signal GOE. Meanwhile, in the conventional LCD, the timing controller further generates a gate start pulse GSP, a gate shift clock signal GSC, and the like in addition to the gate output enable signal GOE. In the liquid crystal display according to the exemplary embodiment of the present invention, the gate start pulse GSP and the gate shift clock signal GSC are generated in the first gate IC 331 which first outputs the gate pulses, and thus the other gate IC 332. To 335). The gate start pulse GSP indicates the start line at which the scan is started so that the first gate pulse is generated from the first gate IC 331. The gate shift clock signal GSC is a clock signal for shifting the gate start pulse GSP. The shift registers of the gate ICs 331 to 335 shift the gate start pulse GSP at the rising edge of the gate shift clock signal GSC. The second to fifth gate ICs 332 to 335 receive the final output of the front gate IC as the gate start pulse GSP to generate the first gate pulse. The gate output enable signal GOE is input to the gate ICs 331 to 335 in common. The gate ICs 331 to 335 output the gate pulse for the low logic period of the gate output enable signal GOE, that is, immediately after the polling time of the pulse to just before the rising time of the next pulse. The outputs of the gate ICs 331 to 335 are blocked during the high logic period of the gate output enable signal GOE.

The data timing control signal generated by the timing controller 31 includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable. Signal (Source Output Enable, SOE) and the like. The source start pulse SSP indicates the start pixel in the line where data is to be displayed. The source sampling clock SSC instructs the latch operation of data in the data driving circuit 32 based on the rising or falling edge. The polarity control signal POL controls the polarity of the analog video data voltage output from the data driving circuit 32. The source output enable signal SOE controls the output of the source IC.

Each of the data drive ICs of the data driving circuit 32 includes a shift register, a latch, a digital-to-analog converter, an output buffer, and the like. The data driving circuit 32 latches the digital video data RGB under the control of the timing controller 31. The data driving circuit 32 supplies the charge share voltage to the data lines 34 in response to the source output enable signal SOE, and then the digital video data RGB in response to the polarity control signal POL. The black data is converted into an analog positive / negative gamma compensation voltage to generate a positive / negative analog data voltage and supply the voltages to the data lines 34.

Each of the gate ICs 331 to 335 of the gate driving circuit 33 includes a GSP & GSC generator, a shift register, an AND gate array, a level shifter, and the like. The gate ICs 331 to 335 may include a gate output enable signal GOE generated by the timing controller 31 and a gate starter pulse GSP and a gate shift generated inside the first gate IC 331. Gate pulses are sequentially supplied to the gate lines 35 in response to the clock GSC.

4 shows the GOE generator of the timing controller 31 and its input signals. 5 illustrates a gate output enable signal GOE output from the GOE generation unit.

4 and 5, the GOE generation unit includes a first GOE generation unit 41, a second GOE generation unit 42, and an OR gate 43 (hereinafter referred to as an “OR gate”) 43.

The first GOE generating unit 41 counts the data enable signal DE based on the clock signal CLK, and as a result of the count, a width of t2 smaller than the pulse width of the data enable signal DE as shown in FIG. 5. Pulses occur regularly. The data enable signal DE is generated at one horizontal period 1H. Therefore, in the output signal P1 of the first GOE generating section 41, pulses are generated in one horizontal period 1H period. The output signal P1 of the first GOE generation unit 41 is substantially the same as the gate output enable signal of the prior art.

The second GOE generating unit 42 receives the vertical synchronization signal Vsync and the clock signal CLK, counts the vertical synchronization signal Vsync based on the clock signal CLK, and according to the count result of FIG. 5 and FIG. Similarly, a pulse having a wider pulse width than the output signal P1 of the second GOE generation unit 42 is regularly generated. The vertical synchronization signal Vsync is generated at approximately one frame period. Therefore, in the output signal P2 of the second GOE generating section 42, a pulse is generated once at the beginning of one frame period and is generated in one frame period period. In the output signal P2 of the second GOE generation unit 42, the pulse width is generated as t1 (≧ 2 * t2). That is, the pulse width t1 of the output signal P2 output from the second GOE generation section 42 is wider than that t2 of the first GOE generation section 41.

The OR gate 43 generates a gate output enable signal GOE by ORing the output signal P1 of the first GOE generation unit 41 and the output signal P2 of the second GOE generation unit 42. In the gate output enable signal GOE, a pulse S1 having a wide pulse width is initially generated in every frame period, and thereafter, pulses S2 having a relatively small pulse width are generated in one horizontal period period.

6 shows a GSP & GSC generation unit 60 embedded in each of the gate ICs 331 to 335. 7 illustrates input / output waveforms of the GSP & GSC generator 60 and gate pulses output from the first gate ICs 331 to 335.

6 and 7, the GSP & GSC generation unit 60 includes a delay unit 61 and a D flip-flop 62.

The delay unit 61 generates the delay signals GOE1 to GOE3 by delaying the gate output enable signal GOE from the timing controller 31 using the first to third delay circuits 611 to 613. do. The first delay circuit 611 generates a first delay signal GOE1 by delaying the gate output enable signal GOE by t3. t3 is a time greater than zero and less than t2. The first delay signal GOE1 is used as the gate shift clock GSC. Hereinafter, the first delay signal GOE1 will be referred to as a gate shift clock GSC. The second delay circuit 612 delays the gate shift clock GSC by t3 to generate the second delay signal GOE2. The third delay circuit 613 generates the third delay signal GOE3 by delaying the second delay signal GOE2 by t3. Accordingly, the gate shift clock GSC is delayed in phase by t3 compared to the gate output enable signal GOE from the timing controller 31, and the second delay signal GOE2 is in phase compared to the gate shift clock GSC. As late as t3. The third delay signal GOE3 is later in phase than the second delay signal GOE2 by t3.

Each of the delay circuits 611 to 613 of the delay unit 61 includes a plurality of inverter pairs. The delay time of the delay circuits 611 to 613 is adjustable according to the number of inverter pairs. For example, the more inverter pairs connected in series, the longer the delay time of the input signal. The delay circuits 611 to 613 may be any known delay circuit as well as an inverter pair.

The D flip-flop 62 receives the gate output enable signal GOE from the timing controller 31 through its input terminal D. The third delay signal G3 is input to the clock terminal of the D flip-flop 62, and the enable signal EN is input to the enable terminal of the D flip-flop 62. The D flip-flop 62 is driven when the high logic enable signal EN (H) is input to the enable terminal, so that the gate output enable signal GOE is applied at the rising edge of the third delay signal GOE3. Output to generate a gate start pulse (GSP). Since the rising edge of the first pulse is generated in the third delay signal GOE3 while the D flip-flop 62 maintains the high logic section of the gate output enable signal GOE, as shown in FIG. After outputting the high logic of GOE to generate the pulse of the gate start pulse GSP, the gate output enable signal GOE remains low logic at the rising edge of the second pulse in the third delay signal GOE3. Outputs low logic. Subsequently, the D flip-flop 62 outputs low logic because the high logic section of the gate output enable signal does not overlap at the rising edge of the pulses after the second pulse in the third delay signal GOE3 as shown in FIG. 7. The gate start pulse GSP is generated again when the rising edge of the third delay signal GOE3 and the high logic section of the gate output enable signal GOE overlap each other at the beginning of the next frame period. When the low logic disable signal EN (L) is input to the enable terminal of the D flip-flop 62, it is disabled and does not generate an output.

Referring to FIG. 7, the shift registers of the gate ICs 331 to 335 receive the gate start pulse GSP generated by the GSP & GSC generator 60 of the first gate IC 331 from the rising edge of the gate shift clock GSC. Shift every time. The gate ICs 331 to 335 supply the output of the shift register to the level shifter during the low logic period of the gate output enable signal GOE. As a result, the gate ICs 331 to 335 sequentially output gate pulses. In Fig. 7, "G1" is a gate pulse supplied to the first gate line, "G2" is a gate pulse supplied to the second gate line, "G3" is a gate pulse supplied to the third gate line, and "G4" Are gate pulses supplied to the fourth gate line, and " G5 " represent gate pulses supplied to the fifth gate line, respectively. The configuration and operation of the gate ICs 331 to 335 will be described in detail with reference to FIG. 8.

8 shows the first and second gate ICs 331 and 332 in detail.

Referring to FIG. 8, the gate ICs 331 and 332 may include an OR gate 84 that outputs a logic sum signal of a signal from a GSP & GSC generator 60, a GSP & GSC generator 60, and a signal from a carry signal input terminal. A shift register 80, a level shifter 82, and a plurality of AND gates 81 connected between the shift register 80 and the level shifter 82 are provided.

Since the enable signal EN (H) of the high logic voltage is input to the enable terminal of the D-flop 62, the GSP & GSC generation unit 60 of the first gate IC 331 is configured as described above. The gate output enable signal GOE from 31 is delayed to generate the gate shift clock GSC and the gate start pulse GSP. On the other hand, the GSP & GSC generator 60 embedded in the gate ICs after the second gate IC 332 outputs the low logic voltage disable signal to the enable terminal of the D-flop 62. Does not occur.

The carry signal input terminal EIO1 of the first gate IC 331 is connected to a base voltage to receive a low logic voltage. The carry signal is input to the carry signal input terminal formed on the gate ICs after the second gate IC 332 connected to the first gate IC 331 from the last stage of the shift register of the previous gate IC. The OR gate 84 of the gate ICs 331 and 332 includes a first input terminal connected to a carry signal input terminal, a second input terminal to which an output signal of the GSP & GSC generating unit 60 is input, and a shift register 80. And an output terminal connected to the input terminal D of the first D flip-flop. In the OR gate 84 of the first gate IC 331, since the low logic voltage is continuously input to the carry signal input terminal, the shift register 80 receives the output of the GSP & GSC generator 60, that is, the gate start pulse GSP. To the first D-flop. The carry signal transmitted from the shift register of the first gate IC 331 is input to the carry signal input terminal of the OR gate 84 of the second gate IC 332, and the carry signal is disabled by the GSP & GSC generator 60. The carry signal from the input terminal is supplied to the first D-flop of the shift register 80 as it is.

The shift register 80 of the first gate IC 331 outputs the output of the GSP & GSC generator 60, that is, the gate start pulse, which is input through the OR gate 84 using a plurality of D-flip flops connected in a cascade manner. GSP) is shifted for each edge of the gate shift clock from the GSP & GSC generation unit 60. Accordingly, the shift register 80 of the first gate IC 331 sequentially generates an output through the output nodes between the D flip-flops. The AND gates 81 of the first gate IC 331 generate an AND product of the output of the shift register and the gate output enable signal GOE inverted by the inverter 83. Therefore, the level shifter 82 receives the output of the shift register 80 when the gate output enable signal GOE from the timing controller 31 is low logic. The level shifter 82 of the first gate IC 331 shifts the output voltage swing width of the AND gate 81 to a swing width capable of operating the TFT of the liquid crystal display panel 30. Gate pulses G1 to Gk generated from the level shifter 82 of the first gate IC 331 are sequentially supplied to k gate lines.

The shift register 80 of the second gate IC 332 carries a carry signal, i.e., a gate signal from the first gate IC 331, input through the OR gate 84 using a plurality of D-flip-flops that are cascaded. The start pulse GSP is shifted for each edge of the gate shift clock from the GSP & GSC generation unit 60. Accordingly, the shift register 80 of the second gate IC 332 sequentially generates output through output nodes between the D flip-flops. The AND gates 81 of the second gate IC 332 generate the logical product output of the output of the shift register 80 and the gate output enable signal GOE inverted by the inverter 83. Therefore, the level shifter 82 receives the output of the shift register 80 when the gate output enable signal GOE from the timing controller 31 is low. The level shifter 82 of the second gate IC 332 shifts the output voltage swing width of the AND gate 81 to a swing width capable of operating the TFTs formed in the pixel array of the liquid crystal display panel 30. Gate pulses Gk + 1 to G2k generated from the level shifter 82 of the second gate IC 332 are sequentially supplied to k gate lines. The gate ICs after the second gate IC 332 have a circuit configuration substantially the same as that of the second gate IC 332, and the operation thereof is also substantially the same as that of the second gate IC 332, and thus a detailed description thereof will be omitted. Shall be.

9 illustrates a connection relationship between input / output terminals of the gate ICs 331 to 335 illustrated in FIG. 3.

Referring to FIG. 9, the gate output enable signal GOE is commonly input from the timing controller 31 to the GOE input terminals of the gate ICs 331 to 335. 3

Since the first gate IC 331 starts to operate by the gate start pulse GSP outputted through the D flip-flop of the built-in GSP & GSC generator 60, the base voltage is applied to the EIO1 input terminal through a pull-down resistor R. (GND) is supplied. Since the second to fifth gate ICs 312 to 315 operate by receiving a carry signal transmitted from the gate IC of the previous stage as a gate start pulse, the carry signal is input from the CAR output terminal of the previous gate IC to the EIO1 input terminal. Is entered.

Since the gate start pulse is generated through the D flip-flop of the built-in GSP & GSC generator 60, the first gate IC 331 is supplied with a high logic voltage supply voltage VCCI. Since the second flip-flop of the built-in GSP & GSC generator 60 needs to be disabled, the second to fifth gate ICs 312 to 315 are supplied with a ground voltage GND through a pull-down resistor R to the EN input terminal. .

10 to 12 show a liquid crystal display according to a second embodiment of the present invention.

Referring to FIG. 10, the liquid crystal display according to the second exemplary embodiment includes a liquid crystal display panel 30, a timing controller 31, a data driving circuit 32, and a gate driving circuit 103. Since the liquid crystal display panel 30, the timing controller 31, and the data driving circuit 32 are substantially the same as those of the first embodiment described above, a detailed description thereof will be omitted.

In the gate driving circuit 103, the first gate IC 331 includes a GSP & GSC generation unit, a shift register, an AND gate array, a level shifter, and the like, as in the first embodiment described above, as shown in Figs. . The first gate IC 331 delays the gate enable signal GOE from the timing controller 31 to generate a gate start pulse GSP and a gate shift clock GSC, and control signals GSP and GSC. Is transmitted to the second gate IC 1032 as a carry signal.

Unlike the first embodiment, the second to fifth gate ICs 1032 to 1035 include a shift register, an AND gate array, a level shifter, and the like without a GSP & GSC generator. Accordingly, the second to fifth gate ICs 1032 to 1035 are substantially the same as the gate drive IC of the prior art, and thus may be compatible with the gate drive IC of the prior art. The second gate IC 1032 receives the gate start pulse GSP and the gate shift clock GSC generated from the first gate IC 331 and shifts the gate start pulse GSP according to the gate shift clock GSC. To generate the gate pulses sequentially. The third gate IC 1033 shifts the gate start pulse GSP received from the second gate IC 1032 according to the gate shift clock GSC from the first gate IC 331 to sequentially generate the gate pulses. do. The fourth gate IC 1034 sequentially shifts the gate start pulses GSP received from the third gate IC 1033 according to the gate shift clock GSC from the first gate IC 331. Occurs. The fifth gate IC 1035 shifts the gate start pulse GSP received from the fourth gate IC 1034 according to the gate shift clock GSC from the first gate IC 331 to sequentially generate the gate pulses. do. The gate ICs 331 and 1032 to 1035 supply gate pulses to the gate lines during the low logic period of the gate output enable signal GOE.

As shown in FIGS. 4 and 5, the timing controller 31 generates pulses having a wide pulse width at an initial stage every frame period and generates pulses having a relatively small pulse width at one horizontal period period thereafter. The output signal of the timing controller 31 generated as described above controls the output of the gate ICs 331, 1032 to 1035, and the gate output enable serving as a reference signal of the gate start pulse GSP and the gate shift clock GSC. Signal (GOE).

FIG. 11 shows the first and second gate ICs 331 and 1032 shown in FIG. 10 in detail. Since the third to fifth gate ICs 1033 to 1035 have substantially the same configuration as the second gate IC 1032, a detailed description thereof will be omitted.

Referring to FIG. 11, the first gate IC 331 includes an OR gate 84 for outputting the GSP & GSC generator 60, an output of the GSP & GSC generator 60, and a logic sum signal of a signal from a carry signal input terminal, and a shift. A register 80, a level shifter 82 and a plurality of AND gates 81 connected between the shift register 80 and the level shifter 82 are provided. The second gate IC 1032 includes a shift register 110, a level shifter 112, and a plurality of AND gates 111 connected between the shift register 110 and the level shifter 112. The second to fifth gate ICs 1032 to 1035 do not require the GSP & GSC generator 60 and the OR gate 84.

The GSP & GSC generation unit 60 of the first gate IC 331 receives the enable signal EN (H) of the high logic voltage from the enable terminal of the D-flop flop 62, so that the GSP & GSC generator 60 The gate output enable signal GOE is delayed to generate the gate shift clock GSC and the gate start pulse GSP. The carry signal input terminal EIO1 of the first gate IC 331 is connected to a base voltage to receive a low logic voltage. The carry signal is input to the carry signal input terminal formed on the gate ICs after the second gate IC 1032 connected to the first gate IC 331 from the last stage of the shift register of the previous gate IC. In the OR gate 84 of the first gate IC 331, since the low logic voltage is continuously input to the carry signal input terminal, the shift register 80 receives the output of the GSP & GSC generator 60, that is, the gate start pulse GSP. To the first D-flop. The shift register 80 of the first gate IC 331 outputs the output of the GSP & GSC generator 60, that is, the gate start pulse, which is input through the OR gate 84 using a plurality of D-flip flops connected in a cascade manner. GSP) is shifted for each edge of the gate shift clock from the GSP & GSC generation unit 60. Accordingly, the shift register 80 of the first gate IC 331 sequentially generates an output through the output nodes between the D flip-flops. The AND gates 81 of the first gate IC 331 generate an AND product of the output of the shift register and the gate output enable signal GOE inverted by the inverter 83. Therefore, the output of the shift register 80 is input to the level shifter 82 of the first gate IC 331 when the gate output enable signal GOE from the timing controller 31 is low. The level shifter 82 of the first gate IC 331 shifts the output voltage swing width of the AND gate 81 to a swing width capable of operating the TFT of the liquid crystal display panel. Gate pulses G1 to Gk generated from the level shifter 82 of the first gate IC 331 are sequentially supplied to k gate lines.

The shift register 110 of the second gate IC 1032 receives the carry signal from the first gate IC 331, that is, the gate start pulse GSP, by using a plurality of D-flip flops connected in a dependent manner. Shift is performed for each edge of the gate shift clock input from the IC 331. Accordingly, the shift register 110 of the second gate IC 1032 generates the output sequentially through the output nodes between the D flip-flops. The AND gates 111 of the second gate IC 1032 generate the logical product output of the output of the shift register and the gate output enable signal GOE inverted by the inverter. Accordingly, the output of the shift register 110 is input to the level shifter 112 of the second gate IC 1032 when the gate output enable signal GOE from the timing controller 31 is low. The level shifter 112 of the second gate IC 1032 shifts the output voltage swing width of the AND gate 111 to a swing width capable of operating the TFT of the liquid crystal display panel 30. Gate pulses Gk + 1 to G2k generated from the level shifter 112 of the second gate IC 1032 are sequentially supplied to k gate lines.

FIG. 12 shows a connection relationship between input / output terminals of the gate ICs 331 to 1035 shown in FIG.

Referring to FIG. 12, the gate output enable signal GOE is commonly input from the timing controller 31 to the GOE input terminal of the gate ICs 331 and 1032 to 1035.

Since the first gate IC 331 starts to operate by the gate start pulse GSP outputted through the D flip-flop of the built-in GSP & GSC generator 60, the base voltage is applied to the EIO1 input terminal through a pull-down resistor R. (GND) is supplied. Since the second to fifth gate ICs 1032 to 1035 operate by receiving the carry signal transmitted from the gate IC of the previous stage as the gate start pulse, the carry signal is applied from the CAR output terminal of the previous gate IC to the EIO1 input terminal. Is entered.

Since the gate start pulse is generated through the D flip-flop of the built-in GSP & GSC generator 60, the first gate IC 331 is supplied with a high logic voltage supply voltage VCCI. The second to fifth gate ICs 1032 to 1035 do not need the GSP & GSC generator 60, and thus do not require the EN input terminal.

The second to fifth gate ICs 1032 to 1035 receive a gate shift clock GSC generated from the GSP & GSC generator 60 of the first gate IC 331 through the GSC input terminal.

In the first exemplary embodiment, the liquid crystal display according to the present invention separates the GSP & GSC generator 60 from the gate ICs, and controls the output terminals of the GSP & GSC generator 60 corresponding to the gate ICs. Connect to the signal input terminal. In this case, the gate drive ICs may be compatible with the gate ICs of the prior art. According to another exemplary embodiment of the present invention, the liquid crystal display device separates the GSP & GSC generation unit 60 from the first gate IC in the second embodiment, and outputs the output terminals of the GSP & GSC generation unit 60 to the corresponding gate ICs. Connect to the control signal input terminal.

Although the above-described embodiments of the present invention have been described with reference to a liquid crystal display device, the present invention may be applied to other flat panel display devices such as a field emission display device (FED), a plasma display panel (PDP), and an organic light emitting diode device (OLED). It is also applicable to scan drive circuits such as the above.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a block diagram showing a gate IC of a scan driving circuit applied to a liquid crystal display device.

2 is a waveform diagram showing a control signal for controlling a scan driving circuit and an output signal of the scan driving circuit;

3 is a block diagram illustrating a liquid crystal display device according to a first embodiment of the present invention.

4 is a circuit diagram and waveform diagrams illustrating a GOE generating unit and its input signals of the timing controller shown in FIG.

FIG. 5 is a waveform diagram illustrating a gate output enable signal output from the GOE generation unit shown in FIG. 4. FIG.

FIG. 6 is a circuit diagram showing a GSP & GSC generating unit of the gate IC shown in FIG.

FIG. 7 is a waveform diagram illustrating input and output waveforms of the GSP & GSC generation unit and gate pulses output from the first gate IC of FIG. 6.

FIG. 8 is a circuit diagram illustrating in detail the first and second gate ICs shown in FIG. 3. FIG.

FIG. 9 shows input / output terminals of the gate ICs shown in FIG. 3; FIG.

10 is a block diagram illustrating a liquid crystal display according to a second embodiment of the present invention.

FIG. 11 is a circuit diagram illustrating in detail the first and second gate ICs shown in FIG. 10.

FIG. 12 is a diagram showing a connection relationship between input / output terminals of gate ICs shown in FIG. 10; FIG.

<Explanation of symbols for main parts of drawing>

31: timing controller 32: data drive circuit

33, 103: gate driving circuits 331 to 335, 1032 to 1035: gate IC

41: first GOE generator 42: second GOE generator

43, 84: OR gate 60: GSP & GSC generator

61: delay unit 62: D flip-flop

80: shift register 81: AND gate

82: level shifter

Claims (9)

A display panel in which data lines and gate lines intersect and pixels are arranged in a matrix; A data driver circuit for supplying a video data signal to the data lines; A gate driving circuit which sequentially supplies gate pulses to the gate lines; And A controller for generating a first control signal for controlling the output of the gate driving circuit; And a control signal generator for delaying the first control signal to generate a second control signal for controlling the shift operation of the gate driving circuit and a third control signal for starting the operation of the gate driving circuit. Device. The method of claim 1, The controller, A GOE for generating the first control signal by generating a first pulse having a wider pulse width at the beginning of the frame period every frame period, and then repeatedly outputting a second pulse having a narrower pulse width than the first pulse in one horizontal period period. A display device comprising a generator. The method of claim 1, The control signal generator, A delay unit generating the second control signal by delaying the first control signal and generating the delay signal by delaying the second control signal; And And a D-flip-flop that is enabled by an enable signal and outputs the first control signal at a rising edge of the delay signal to generate the third control signal and is disabled in response to the disable signal. Display. The method of claim 3, wherein The gate driving circuit includes a plurality of gate ICs, Each of the gate ICs, A shift register configured to sequentially shift the third control signal according to the second control signal; A level shifter for converting a swing width of an output signal of the shift register; An AND gate configured to supply an output signal of the shift register to the level shifter in response to the first control signal; And And an OR gate configured to logically output the output signal of the control signal generator and the third control signal inputted from the shift register of the previous gate IC. The method of claim 4, wherein And the control signal generator is embedded in each of the driving circuits. The method of claim 3, wherein The gate driving circuit includes a plurality of gate ICs, Each of the gate ICs, A shift register configured to sequentially shift the third control signal according to the second control signal; A level shifter for converting a swing width of an output signal of the shift register; And And an AND gate for supplying an output signal of the shift register to the level shifter in response to the first control signal. The method of claim 6, And the control signal generator is embedded only in a first driving IC which first outputs the gate pulse among the gate ICs. The method of claim 7, wherein Gate ICs that are dependently connected to the first gate IC and sequentially generate the gate pulses following the first gate IC are the second and third from the control signal generator built in the first gate IC. A display device characterized in that it operates by receiving a control signal. A display panel in which data lines and gate lines intersect and pixels are arranged in a matrix, a data driving circuit for supplying a video data signal to the data lines, and a gate driving circuit for sequentially supplying gate pulses to the gate lines. In the driving method of the display device provided with, Generating a first control signal for controlling the output of the gate driving circuit; And Generating a second control signal for controlling the shift operation of the gate driving circuit by delaying the first control signal and a third control signal for initiating the operation of the gate driving circuit. Driving method.

Images