CN106847202A - Signal processing circuit, display device and its control method - Google Patents
Signal processing circuit, display device and its control method Download PDFInfo
- Publication number
- CN106847202A CN106847202A CN201611110207.XA CN201611110207A CN106847202A CN 106847202 A CN106847202 A CN 106847202A CN 201611110207 A CN201611110207 A CN 201611110207A CN 106847202 A CN106847202 A CN 106847202A
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- China
- Prior art keywords
- signal
- input
- source electrode
- trigger
- electrode driver
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
Abstract
The invention discloses a kind of signal processing circuit, including：Trigger, the input of the trigger is connected with signal input part, and triggering end is connected with clock signal；Logical AND gate, the output end of the input of the logical AND gate respectively with the input signal and the trigger is connected, and output end is connected with signal output part, wherein, the signal processing circuit carries out noise reduction process to the input signal of signal input part.Present invention also offers a kind of display device and its control method, the cascade signal can be repaired in the cascade signal abnormal transmission of source electrode driver, there is picture exception caused by maloperation in source electrode driver when avoiding exception, improves the reliability of driving chip and reduces wiring.
Description
Technical field
The invention belongs to field of display, more particularly, to a kind of signal processing circuit, display device and its controlling party
Method.
Background technology
Recently, flat display apparatus have been increased by size such as liquid crystal display device.Large-scale plane shows
Device is by using being referred to as IC (integrated circuit) drive signal line of source electrode driver.Can be driven by each source electrode driver
The number of dynamic holding wire has limitation.There are the flat display apparatus for being exaggerated and highly being become more meticulous multiple source electrodes to drive
There is dynamic device, multiple source electrode drivers cascade Connection as shown in Figure 1 to construct.Flat display apparatus sequentially operate multiple sources
Driver, and drive for a horizontal all of holding wire.
As shown in fig. 1, the flat display apparatus 1 of prior art include controller 10, source electrode driver IC1 to IC4, with
And display 20.Clock signal clk, loading signal LOAD and data-signal DDO to DD5 are sent to source electrode by controller 10
Each in driver.Clock signal clk is the signal of the operating clock for generating source electrode driver IC1 to IC4.Data-signal
DD0 to DD5 is pixel data.Each in source electrode driver IC1 to IC4 is by the picture corresponding with data-signal DD0 to DD5
Display 12 is arrived in plain drive signal output.Loading signal LOAD is that data-signal DD0 to DD5 is put into source electrode driver IC1 extremely
The gating signal of each of IC4.This is loaded into signal LOAD outputs to source drive from controller 10 in each horizontal period
Device IC1 to IC4.In the example of fig. 1, for the simplification of accompanying drawing, the number of source electrode driver is restricted to four.However, it is possible to
Further use substantial amounts of source electrode driver.
However, power supply around the source electrode driver IC1 to IC4 of cascade structure, or the signal that has fluctuation disturb
During to cascade signal, cascade signal may produce noise, and then may cause the maloperation of source electrode driver IC, picture occur
It is abnormal.
The content of the invention
It is an object of the invention to provide a kind of signal processing circuit, display device and its control method.
According to an aspect of the present invention, there is provided a kind of signal processing circuit, including：Trigger, the input of the trigger
End is connected with signal input part, and triggering end is connected with clock signal；Logical AND gate, the input of the logical AND gate respectively with institute
The output end connection of input signal and the trigger is stated, output end is connected with signal output part, wherein, the signal transacting
Circuit carries out noise reduction process to the input signal of signal input part.
Preferably, the clock signal is synchronous with the input signal of the signal input part is set.
Preferably, when the input signal normal transmission of the signal input part, the output end output of the trigger is high
Level.
Preferably, when the input signal abnormal transmission of the signal input part, the output end output of the trigger is low
Level.
According to another aspect of the present invention, there is provided a kind of display device, including controller, multiple source electrode driver and aobvious
Show device,
Wherein, the controller sends into multiple source electrode drivers clock signal, loading signal and data-signal
Each；
Each described source electrode driver exports the pixel drive signal corresponding with the data-signal to display；
The display device also includes：
Signal processing circuit, the cascade signal with the source electrode driver is connected, for source electrode driver each described
Cascade signal carry out noise reduction process.
Preferably, the signal processing circuit includes：Trigger, input and the signal input part of the trigger connect
Connect, triggering end is connected with clock signal；Logical AND gate, the input of the logical AND gate respectively with the input signal and institute
The output end connection of trigger is stated, output end is connected with signal output part, wherein, the input signal of the signal input part is institute
State the cascade signal of source electrode driver.
Preferably, the clock signal is synchronous with the input signal of the signal input part is set.
Preferably, when the input signal normal transmission of the signal input part, the output end output of the trigger is high
Level.
Preferably, when the input signal abnormal transmission of the signal input part, the output end output of the trigger is low
Level.
Preferably, the signal processing circuit is located at the outside of the source electrode driver, is connected to the source electrode driver
Cascade signal and the source electrode driver between.
Present invention also offers a kind of control method of above-mentioned display device, including：By clock signal, loading signal and
Data-signal sends each into multiple source electrode drivers；Cascade signal to source electrode driver each described carries out noise reduction
Treatment；The pixel drive signal corresponding with the data-signal is exported to display.
Signal processing circuit, display device and its control method that the present invention is provided, in the cascade signal of source electrode driver
The cascade signal can be repaired during abnormal transmission, it is to avoid picture is different caused by maloperation occurs in source electrode driver when abnormal
Often, improve the reliability of driving chip and reduce wiring.
Brief description of the drawings
By description referring to the drawings to the embodiment of the present invention, of the invention above-mentioned and other purposes, feature and
Advantage will be apparent from, in the accompanying drawings：
Fig. 1 shows the structural representation of the display device of prior art；
Fig. 2 shows the circuit theory diagrams of signal processing circuit according to embodiments of the present invention；
Fig. 3 shows the signal input part of signal processing circuit according to embodiments of the present invention and the letter of signal output part
Number and clock signal oscillogram；
Fig. 4 shows the circuit theory diagrams of display device according to embodiments of the present invention；
Fig. 5 shows the flow chart of the control method of display device according to embodiments of the present invention.
Specific embodiment
Various embodiments of the present invention are more fully described hereinafter with reference to accompanying drawing.In various figures, identical element
Represented using same or similar reference.For the sake of clarity, the various pieces in accompanying drawing are not necessarily to scale.
The present invention can be presented in a variety of manners, some of them example explained below.
Fig. 2 shows the circuit theory diagrams of signal processing circuit according to embodiments of the present invention.As shown in figure 1, the letter
Number process circuit 30 includes trigger 301 and logical AND gate 302.
Wherein, the trigger 301 includes input D, triggering end C and output end Q.
In the present embodiment, the trigger is synchronizer trigger, the input D and signal input of the trigger 301
End IN connections, triggering end C is connected with clock signal clk.
Wherein, the clock signal clk and the input signal Vin of signal input part IN are synchronizing signal.Such as input signal
Vin is square pulse ripple, then the clock signal clk is and the identical square pulse ripples of the input signal Vin.
Logical AND gate 302 includes input 1, input 2 and output end 3.
In the present embodiment, the input 1 of the logical AND gate is connected with the input signal Vin.The logical AND gate
Input 2 be connected with the output end Q of the trigger 301, the output end 3 of the logical AND gate connects with signal output part OUT
Connect.
Specifically, as shown in figure 3, the input signal Vin of signal input part IN is a square pulse ripple, the then clock for setting
Signal is and the identical square pulse ripples of the input signal Vin.
Because trigger 301 is synchronizer trigger, when clock signal is high level, the output end of trigger 301 is by defeated
Enter signal Vin controls；When clock signal is low level, the state of the output end of trigger 301 remains low level.
When the input signal Vin normal transmissions of signal input part IN, when clock signal is high level, while input signal
Vin is also high level, then the output end Q of trigger 301 is consistent with input signal Vin, is also high level, and then logical AND gate
302 input 1 and input 2 is high level, and output end 3 is high level；When clock signal is low level, while being input into letter
Number Vin is also low level, then the state of the output end Q of trigger 301 remains low level, and then logical AND gate 302 is defeated
Enter end 1 and input 2 is low level, output end 3 is low level.Therefore, the output signal Vout of signal output part OUT with it is defeated
Enter signal Vin consistent.
When the input signal Vin abnormal transmissions of signal input part IN, when clock signal is low level, and input signal
Vin is high level, then the state of the output end Q of trigger 301 remains low level, so logical AND gate 302 input 1
For high level, input 2 are low level, then the output end 3 of logical AND gate 302 is low level.Therefore, signal output part OUT
Output signal Vout is consistent with original input signal Vin, input signal Vin is recovered normal.
The signal processing circuit that the present invention is provided, can believe the cascade in the cascade signal abnormal transmission of source electrode driver
Number repaired, it is to avoid picture exception caused by maloperation occurs in source electrode driver when abnormal, improved the reliability of driving chip
And reduce wiring.
Fig. 4 shows the structural representation of the display device of offer according to embodiments of the present invention.As shown in figure 4, described aobvious
Showing device includes controller 10, multiple source electrode driver IC1~IC4 and display 20.
Wherein, clock signal clk, loading signal LOAD and data-signal DDO to DD5 are sent to source by controller 10
Each in driver.Clock signal clk is the signal of the operating clock for generating source electrode driver IC1 to IC4.Data are believed
Number DD0 to DD5 is pixel data.Each in source electrode driver IC1 to IC4 will be corresponding with data-signal DD0 to DD5
Display 12 is arrived in pixel drive signal output.Loading signal LOAD is that data-signal DD0 to DD5 is put into source electrode driver IC1
To the gating signal of each of IC4.This is loaded into signal LOAD outputs from controller 10 in each horizontal period to be driven to source electrode
Dynamic device IC1 to IC4.In the example of fig. 1, for the simplification of accompanying drawing, the number of source electrode driver is restricted to four.However, can
Further to use substantial amounts of source electrode driver.
The display device also includes signal processing circuit 30, the cascade signal with the source electrode driver IC1~IC4
DIO is connected, and believing No. DIO for the cascade to source electrode driver each described carries out noise reduction process.
The signal processing circuit 30 includes trigger 301 and logical AND gate 302.
Wherein, the trigger 301 includes input D, triggering end C and output end Q.
In the present embodiment, the trigger is synchronizer trigger, the input D and signal input of the trigger 301
End IN connections, triggering end C is connected with clock signal clk.
Wherein, the clock signal clk and the input signal Vin of signal input part IN are synchronizing signal.Such as input signal
Vin is square pulse ripple, then the clock signal clk is and the identical square pulse ripples of the input signal Vin.
Logical AND gate 302 includes input 1, input 2 and output end 3.
In the present embodiment, the input 1 of the logical AND gate is connected with the input signal Vin.The logical AND gate
Input 2 be connected with the output end Q of the trigger 301, the output end 3 of the logical AND gate connects with signal output part OUT
Connect.
Specifically, as shown in figure 3, the input signal Vin of signal input part IN is a square pulse ripple, the then clock for setting
Signal is and the identical square pulse ripples of the input signal Vin.
Because trigger 301 is synchronizer trigger, when clock signal is high level, the output end of trigger 301 is by defeated
Enter signal Vin controls；When clock signal is low level, the state of the output end of trigger 301 remains low level.
When the input signal Vin normal transmissions of signal input part IN, when clock signal is high level, while input signal
Vin is also high level, then the output end Q of trigger 301 is consistent with input signal Vin, is also high level, and then logical AND gate
302 input 1 and input 2 is high level, and output end 3 is high level；When clock signal is low level, while being input into letter
Number Vin is also low level, then the state of the output end Q of trigger 301 remains low level, and then logical AND gate 302 is defeated
Enter end 1 and input 2 is low level, output end 3 is low level.Therefore, the output signal Vout of signal output part OUT with it is defeated
Enter signal Vin consistent.
When the input signal Vin abnormal transmissions of signal input part IN, when clock signal is low level, and input signal
Vin is high level, then the state of the output end Q of trigger 301 remains low level, so logical AND gate 302 input 1
For high level, input 2 are low level, then the output end 3 of logical AND gate 302 is low level.Therefore, signal output part OUT
Output signal Vout is consistent with original input signal Vin, input signal Vin is recovered normal.
In a preferred embodiment, the signal processing circuit 30 is located at the outer of the source electrode driver IC1~IC4
Portion, is connected between the cascade signal DIO of the source electrode driver and source electrode driver IC1~IC4.
Each described source electrode driver IC1 to IC4 by the pixel drive signal corresponding with the data-signal export to
Display.
The display device that the present invention is provided, can enter in the cascade signal abnormal transmission of source electrode driver to the cascade signal
Row is repaired, it is to avoid picture exception caused by maloperation occurs in source electrode driver when abnormal, improve driving chip reliability and
Reduce wiring.
Fig. 5 shows the flow chart of the control method of the display device of offer according to embodiments of the present invention.The control method
Suitable for display device.The display device includes controller 10, multiple source electrode driver IC1~IC4 and display 20.Such as
Shown in Fig. 5, the control method is comprised the following steps.
In step S01, clock signal, loading signal and data-signal are sent every into multiple source electrode drivers
One.
In the present embodiment, the controller 10 of the display device is by clock signal clk, loading signal LOAD and counts
It is believed that number DDO to DD5 is sent to each in source electrode driver.Clock signal clk is generation source electrode driver IC1 to IC4
Operating clock signal.Data-signal DD0 to DD5 is pixel data.Each in source electrode driver IC1 to IC4 will be with
Display 12 is arrived in data-signal DD0 to DD5 corresponding pixel drive signal output.Loading signal LOAD is by data-signal
DD0 to DD5 is put into the gating signal of each of source electrode driver IC1 to IC4.Each horizontal period from controller 10 by this
Load signal LOAD outputs to source electrode driver IC1 to IC4.
In step S02, the cascade signal to source electrode driver each described carries out noise reduction process.
In the present embodiment, the level of the signal processing circuit 30 of the display device and the source electrode driver IC1~IC4
The DIO connections of connection signal, believing No. DIO for the cascade to source electrode driver each described carries out noise reduction process.
In step S03, the pixel drive signal corresponding with the data-signal is exported to display.
The control method of the display device that the present invention is provided, can be to this during to the cascade signal abnormal transmission of source electrode driver
Cascade signal is repaired, it is to avoid picture exception caused by maloperation occurs in source electrode driver when abnormal, improves driving chip
Reliability and reduction wiring.
According to embodiments of the invention as described above, these embodiments do not have all of details of detailed descriptionthe, not yet
It is only described specific embodiment to limit the invention.Obviously, as described above, can make many modifications and variations.This explanation
Book is chosen and specifically describes these embodiments, is in order to preferably explain principle of the invention and practical application, so that affiliated
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.Protection model of the invention
The scope that enclosing should be defined by the claims in the present invention is defined.
Claims (10)
1. a kind of signal processing circuit, it is characterised in that including：
Trigger, the input of the trigger is connected with signal input part, and triggering end is connected with clock signal；
Logical AND gate, the input of the logical AND gate connects with the output end of the input signal and the trigger respectively
Connect, output end is connected with signal output part；
Wherein, the signal processing circuit carries out noise reduction process to the input signal of signal input part.
2. signal processing circuit according to claim 1, it is characterised in that the clock signal and the signal input part
Input signal synchronously set.
3. signal processing circuit according to claim 2, it is characterised in that when the signal input part input signal just
Often during transmission, the output end output high level of the trigger.
4. signal processing circuit according to claim 2, it is characterised in that when the input signal of the signal input part is different
Often during transmission, the output end output low level of the trigger.
5. a kind of display device, including controller, multiple source electrode drivers and display,
Characterized in that, the controller sends to multiple source electrode drivers clock signal, loading signal and data-signal
In each；
Each described source electrode driver exports the pixel drive signal corresponding with the data-signal to display；
The display device also includes：Signal processing circuit, the cascade signal with the source electrode driver is connected, for each
The cascade signal of the source electrode driver carries out noise reduction process；
The signal processing circuit includes：
Trigger, the input of the trigger is connected with signal input part, and triggering end is connected with clock signal；
Logical AND gate, the input of the logical AND gate connects with the output end of the input signal and the trigger respectively
Connect, output end is connected with signal output part,
Wherein, the input signal of the signal input part is the cascade signal of the source electrode driver.
6. display device according to claim 5, it is characterised in that the clock signal is defeated with the signal input part
Enter signal synchronously to set.
7. display device according to claim 6, it is characterised in that when the input signal of the signal input part is normally passed
When defeated, the output end output high level of the trigger.
8. display device according to claim 6, it is characterised in that when the input signal of the signal input part is passed extremely
When defeated, the output end output low level of the trigger.
9. display device according to claim 5, it is characterised in that the signal processing circuit is located at the source drive
The outside of device, is connected between the cascade signal of the source electrode driver and the source electrode driver.
10. a kind of control method of display device as described in claim any one of 5-9, it is characterised in that described display
The control method of device includes：
Clock signal, loading signal and data-signal are sent into each into multiple source electrode drivers；
Cascade signal to source electrode driver each described carries out noise reduction process；
The pixel drive signal corresponding with the data-signal is exported to display.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611110207.XA CN106847202B (en) | 2016-12-06 | 2016-12-06 | Signal processing circuit, display device and control method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611110207.XA CN106847202B (en) | 2016-12-06 | 2016-12-06 | Signal processing circuit, display device and control method thereof |
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| Publication Number | Publication Date |
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| CN106847202A true CN106847202A (en) | 2017-06-13 |
| CN106847202B CN106847202B (en) | 2020-04-24 |
Family
ID=59146369
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| CN201611110207.XA Active CN106847202B (en) | 2016-12-06 | 2016-12-06 | Signal processing circuit, display device and control method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113053277A (en) * | 2021-04-20 | 2021-06-29 | 合肥京东方显示技术有限公司 | Display panel and driving device and driving method thereof |
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